rt2x00: Reduce tx descriptor size
The tx descriptor values qid, cw_min, cw_max and aifs are directly accessible through the tx entry struct. So there's no need to copy them into the tx descriptor and passing them to the indiviual drivers. Instead we can just get the correct value from the tx entry. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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08e5310028
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@ -1193,9 +1193,9 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry,
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rt2x00_desc_read(txd, 2, &word);
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rt2x00_desc_read(txd, 2, &word);
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rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
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rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
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rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
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rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
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rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
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rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
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rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
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rt2x00_desc_write(txd, 2, word);
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rt2x00_desc_write(txd, 2, word);
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rt2x00_desc_read(txd, 3, &word);
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rt2x00_desc_read(txd, 3, &word);
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@ -1081,9 +1081,9 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry,
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
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rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
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rt2x00_desc_write(txd, 1, word);
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rt2x00_desc_write(txd, 1, word);
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rt2x00_desc_read(txd, 2, &word);
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rt2x00_desc_read(txd, 2, &word);
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@ -487,7 +487,7 @@ void rt2800_write_tx_data(struct queue_entry *entry,
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txdesc->key_idx : 0xff);
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txdesc->key_idx : 0xff);
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rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
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rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
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txdesc->length);
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txdesc->length);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, txdesc->qid);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
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rt2x00_desc_write(txwi, 1, word);
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rt2x00_desc_write(txwi, 1, word);
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@ -310,14 +310,6 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
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memset(txdesc, 0, sizeof(*txdesc));
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memset(txdesc, 0, sizeof(*txdesc));
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/*
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* Initialize information from queue
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*/
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txdesc->qid = entry->queue->qid;
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txdesc->cw_min = entry->queue->cw_min;
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txdesc->cw_max = entry->queue->cw_max;
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txdesc->aifs = entry->queue->aifs;
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/*
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/*
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* Header and frame information.
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* Header and frame information.
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*/
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*/
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@ -280,7 +280,6 @@ enum txentry_desc_flags {
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* Summary of information for the frame descriptor before sending a TX frame.
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* Summary of information for the frame descriptor before sending a TX frame.
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*
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*
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* @flags: Descriptor flags (See &enum queue_entry_flags).
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* @flags: Descriptor flags (See &enum queue_entry_flags).
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* @qid: Queue identification (See &enum data_queue_qid).
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* @length: Length of the entire frame.
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* @length: Length of the entire frame.
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* @header_length: Length of 802.11 header.
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* @header_length: Length of 802.11 header.
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* @length_high: PLCP length high word.
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* @length_high: PLCP length high word.
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@ -293,11 +292,8 @@ enum txentry_desc_flags {
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* @rate_mode: Rate mode (See @enum rate_modulation).
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* @rate_mode: Rate mode (See @enum rate_modulation).
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* @mpdu_density: MDPU density.
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* @mpdu_density: MDPU density.
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* @retry_limit: Max number of retries.
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* @retry_limit: Max number of retries.
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* @aifs: AIFS value.
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* @ifs: IFS value.
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* @ifs: IFS value.
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* @txop: IFS value for 11n capable chips.
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* @txop: IFS value for 11n capable chips.
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* @cw_min: cwmin value.
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* @cw_max: cwmax value.
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* @cipher: Cipher type used for encryption.
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* @cipher: Cipher type used for encryption.
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* @key_idx: Key index used for encryption.
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* @key_idx: Key index used for encryption.
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* @iv_offset: Position where IV should be inserted by hardware.
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* @iv_offset: Position where IV should be inserted by hardware.
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@ -306,8 +302,6 @@ enum txentry_desc_flags {
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struct txentry_desc {
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struct txentry_desc {
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unsigned long flags;
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unsigned long flags;
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enum data_queue_qid qid;
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u16 length;
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u16 length;
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u16 header_length;
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u16 header_length;
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@ -323,11 +317,8 @@ struct txentry_desc {
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u16 mpdu_density;
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u16 mpdu_density;
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short retry_limit;
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short retry_limit;
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short aifs;
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short ifs;
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short ifs;
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short txop;
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short txop;
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short cw_min;
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short cw_max;
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enum cipher cipher;
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enum cipher cipher;
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u16 key_idx;
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u16 key_idx;
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@ -1789,10 +1789,10 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
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* Start writing the descriptor words.
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* Start writing the descriptor words.
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*/
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*/
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
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rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
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rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
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rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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@ -1820,7 +1820,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
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rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
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rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
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rt2x00_desc_write(txd, 5, word);
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rt2x00_desc_write(txd, 5, word);
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if (txdesc->qid != QID_BEACON) {
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if (entry->queue->qid != QID_BEACON) {
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rt2x00_desc_read(txd, 6, &word);
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rt2x00_desc_read(txd, 6, &word);
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rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
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rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
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skbdesc->skb_dma);
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skbdesc->skb_dma);
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@ -1866,8 +1866,8 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
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* Register descriptor details in skb frame descriptor.
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* Register descriptor details in skb frame descriptor.
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*/
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*/
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skbdesc->desc = txd;
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skbdesc->desc = txd;
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skbdesc->desc_len =
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skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
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(txdesc->qid == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
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TXD_DESC_SIZE;
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}
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}
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/*
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/*
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@ -1472,10 +1472,10 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry,
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rt2x00_desc_write(txd, 0, word);
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rt2x00_desc_write(txd, 0, word);
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_desc_read(txd, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
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rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
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rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
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rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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