[PATCH] Another couple of alterations to the memory barrier doc
Make another couple of alterations to the memory barrier document following suggestions by Alan Stern and in co-operation with Paul McKenney: (*) Rework the point of introduction of memory barriers and the description of what they are to reiterate why they're needed. (*) Modify a statement about the use of data dependency barriers to note that other barriers can be used instead (as they imply DD-barriers). Signed-off-by: David Howells <dhowells@redhat.com> Acked-By: Paul E. McKenney <paulmck@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>hifive-unleashed-5.1
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@ -262,9 +262,14 @@ What is required is some way of intervening to instruct the compiler and the
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CPU to restrict the order.
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CPU to restrict the order.
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Memory barriers are such interventions. They impose a perceived partial
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Memory barriers are such interventions. They impose a perceived partial
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ordering between the memory operations specified on either side of the barrier.
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ordering over the memory operations on either side of the barrier.
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They request that the sequence of memory events generated appears to other
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parts of the system as if the barrier is effective on that CPU.
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Such enforcement is important because the CPUs and other devices in a system
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can use a variety of tricks to improve performance - including reordering,
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deferral and combination of memory operations; speculative loads; speculative
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branch prediction and various types of caching. Memory barriers are used to
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override or suppress these tricks, allowing the code to sanely control the
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interaction of multiple CPUs and/or devices.
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VARIETIES OF MEMORY BARRIER
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VARIETIES OF MEMORY BARRIER
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@ -461,8 +466,8 @@ Whilst this may seem like a failure of coherency or causality maintenance, it
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isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
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isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
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Alpha).
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Alpha).
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To deal with this, a data dependency barrier must be inserted between the
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To deal with this, a data dependency barrier or better must be inserted
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address load and the data load:
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between the address load and the data load:
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CPU 1 CPU 2
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CPU 1 CPU 2
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=============== ===============
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=============== ===============
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