drm/amdgpu: update RAS related dmesg print
prefix RAS error related dmesg print with pci device info Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -710,14 +710,16 @@ static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
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sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
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if (sec_count) {
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DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
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dev_info(adev->dev,
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"Instance[%d]: SubBlock %s, SEC %d\n", i,
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vml2_mems[i], sec_count);
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err_data->ce_count += sec_count;
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}
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ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
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if (ded_count) {
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DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
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dev_info(adev->dev,
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"Instance[%d]: SubBlock %s, DED %d\n", i,
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vml2_mems[i], ded_count);
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err_data->ue_count += ded_count;
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}
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@ -1539,8 +1539,11 @@ static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
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{ SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
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};
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static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
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uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
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static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
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const struct soc15_reg_entry *reg,
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uint32_t value,
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uint32_t *sec_count,
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uint32_t *ded_count)
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{
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uint32_t i;
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uint32_t sec_cnt, ded_cnt;
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@ -1553,7 +1556,7 @@ static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
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mmhub_v9_4_ras_fields[i].sec_count_mask) >>
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mmhub_v9_4_ras_fields[i].sec_count_shift;
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if (sec_cnt) {
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DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
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dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
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mmhub_v9_4_ras_fields[i].name,
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sec_cnt);
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*sec_count += sec_cnt;
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@ -1563,7 +1566,7 @@ static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
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mmhub_v9_4_ras_fields[i].ded_count_mask) >>
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mmhub_v9_4_ras_fields[i].ded_count_shift;
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if (ded_cnt) {
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DRM_INFO("MMHUB SubBlock %s, DED %d\n",
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dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
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mmhub_v9_4_ras_fields[i].name,
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ded_cnt);
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*ded_count += ded_cnt;
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@ -1588,7 +1591,7 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
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reg_value =
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RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
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if (reg_value)
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mmhub_v9_4_get_ras_error_count(&mmhub_v9_4_edc_cnt_regs[i],
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mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
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reg_value, &sec_count, &ded_count);
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}
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