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ARM: SoC platform updates for v5.4 

The main change this time around is a cleanup of some of the oldest
 platforms based on the XScale and ARM9 CPU cores, which are between 10
 and 20 years old.
 
 The Kendin/Micrel/Microchip KS8695, Winbond/Nuvoton W90x900 and Intel
 IOP33x/IOP13xx platforms are removed after we determined that nobody is
 using them any more.
 
 The TI Davinci and NXP LPC32xx platforms on the other hand are still in
 active use and are converted to the ARCH_MULTIPLATFORM build, meaning
 that we can compile a kernel that works on these along with most other
 ARMv5 platforms. Changes toward that goal are also merged for IOP32x,
 but additional work is needed to complete this. Patches for the
 remaining ARMv5 platforms have started but need more work and some
 testing.
 
 Support for the new ASpeed AST2600 gets added, this is based on the
 Cortex-A7 ARMv7 core, and is a newer version of the existing ARMv5 and
 ARMv6 chips in the same family.
 
 Other changes include a cleanup of the ST-Ericsson ux500 platform
 and the move of the TI Davinci platform to a new clocksource driver.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "The main change this time around is a cleanup of some of the oldest
  platforms based on the XScale and ARM9 CPU cores, which are between 10
  and 20 years old.

  The Kendin/Micrel/Microchip KS8695, Winbond/Nuvoton W90x900 and Intel
  IOP33x/IOP13xx platforms are removed after we determined that nobody
  is using them any more.

  The TI Davinci and NXP LPC32xx platforms on the other hand are still
  in active use and are converted to the ARCH_MULTIPLATFORM build,
  meaning that we can compile a kernel that works on these along with
  most other ARMv5 platforms. Changes toward that goal are also merged
  for IOP32x, but additional work is needed to complete this. Patches
  for the remaining ARMv5 platforms have started but need more work and
  some testing.

  Support for the new ASpeed AST2600 gets added, this is based on the
  Cortex-A7 ARMv7 core, and is a newer version of the existing ARMv5 and
  ARMv6 chips in the same family.

  Other changes include a cleanup of the ST-Ericsson ux500 platform and
  the move of the TI Davinci platform to a new clocksource driver"

[ The changes had marked INTEL_IOP_ADMA and USB_LPC32XX as being
  buildable on other platforms through COMPILE_TEST, but that causes new
  warnings that I most definitely do not want to see during the merge
  window as that could hide other issues.

  So the COMPILE_TEST option got disabled for them again   - Linus ]

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits)
  ARM: multi_v5_defconfig: make DaVinci part of the ARM v5 multiplatform build
  ARM: davinci: support multiplatform build for ARM v5
  arm64: exynos: Enable exynos-chipid driver
  ARM: OMAP2+: Delete an unnecessary kfree() call in omap_hsmmc_pdata_init()
  ARM: OMAP2+: move platform-specific asm-offset.h to arch/arm/mach-omap2
  ARM: davinci: dm646x: Fix a typo in the comment
  ARM: davinci: dm646x: switch to using the clocksource driver
  ARM: davinci: dm644x: switch to using the clocksource driver
  ARM: aspeed: Enable SMP boot
  ARM: aspeed: Add ASPEED AST2600 architecture
  ARM: aspeed: Select timer in each SoC
  dt-bindings: arm: cpus: Add ASPEED SMP
  ARM: imx: stop adjusting ar8031 phy tx delay
  mailmap: map old company name to new one @microchip.com
  MAINTAINERS: at91: remove the TC entry
  MAINTAINERS: at91: Collect all pinctrl/gpio drivers in same entry
  ARM: at91: move platform-specific asm-offset.h to arch/arm/mach-at91
  MAINTAINERS: Extend patterns for Samsung SoC, Security Subsystem and clock drivers
  ARM: s3c64xx: squash samsung_usb_phy.h into setup-usb-phy.c
  ARM: debug-ll: Add support for r7s9210
  ...
alistair/sunxi64-5.4-dsi
Linus Torvalds 2019-09-16 15:48:14 -07:00
parent d0a16fe934 0366977480
commit 2b97c39514
238 changed files with 601 additions and 12475 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@ -178,6 +178,7 @@ Morten Welinder <welinder@darter.rentec.com>
Morten Welinder <welinder@troll.com>
Mythri P K <mythripk@ti.com>
Nguyen Anh Quynh <aquynh@gmail.com>
Nicolas Ferre <nicolas.ferre@microchip.com> <nicolas.ferre@atmel.com>
Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>
Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>
Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>

1
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -175,6 +175,7 @@ properties:
- amlogic,meson8-smp
- amlogic,meson8b-smp
- arm,realview-smp
- aspeed,ast2600-smp
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm2836-smp

55
MAINTAINERS
View File

@ -1740,20 +1740,11 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-pxa/colibri-pxa270-income.c
ARM/INTEL IOP13XX ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IOP32X ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IOP33X ARM ARCHITECTURE
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Orphan
ARM/INTEL IQ81342EX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1912,12 +1903,6 @@ S: Maintained
F: drivers/phy/mediatek/
F: Documentation/devicetree/bindings/phy/phy-mtk-*
ARM/MICREL KS8695 ARCHITECTURE
M: Greg Ungerer <gerg@uclinux.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
F: arch/arm/mach-ks8695/
S: Odd Fixes
ARM/Microchip (AT91) SoC support
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
@ -1959,6 +1944,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-stu300.txt
F: arch/arm/mach-nomadik/
F: arch/arm/mach-u300/
F: arch/arm/mach-ux500/
F: drivers/soc/ux500/
F: arch/arm/boot/dts/ste-*
F: drivers/clk/clk-nomadik.c
F: drivers/clk/clk-u300.c
@ -2002,22 +1988,6 @@ F: drivers/*/*npcm*
F: Documentation/devicetree/bindings/*/*npcm*
F: Documentation/devicetree/bindings/*/*/*npcm*
ARM/NUVOTON W90X900 ARM ARCHITECTURE
M: Wan ZongShun <mcuos.com@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.mcuos.com
S: Maintained
F: arch/arm/mach-w90x900/
F: drivers/input/keyboard/w90p910_keypad.c
F: drivers/input/touchscreen/w90p910_ts.c
F: drivers/watchdog/nuc900_wdt.c
F: drivers/net/ethernet/nuvoton/w90p910_ether.c
F: drivers/mtd/nand/raw/nuc900_nand.c
F: drivers/rtc/rtc-nuc900.c
F: drivers/spi/spi-nuc900.c
F: drivers/usb/host/ehci-w90x900.c
F: drivers/video/fbdev/nuc900fb.c
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
W: http://wiki.openmoko.org/wiki/Neo_FreeRunner
@ -2210,8 +2180,9 @@ F: drivers/*/*s3c24*
F: drivers/*/*/*s3c24*
F: drivers/*/*s3c64xx*
F: drivers/*/*s5pv210*
F: drivers/memory/samsung/*
F: drivers/soc/samsung/*
F: drivers/memory/samsung/
F: drivers/soc/samsung/
F: include/linux/soc/samsung/
F: Documentation/arm/samsung/
F: Documentation/devicetree/bindings/arm/samsung/
F: Documentation/devicetree/bindings/sram/samsung-sram.txt
@ -10628,12 +10599,6 @@ M: Nicolas Ferre <nicolas.ferre@microchip.com>
S: Supported
F: drivers/power/reset/at91-sama5d2_shdwc.c
MICROCHIP SAMA5D2-COMPATIBLE PIOBU GPIO
M: Andrei Stefanescu <andrei.stefanescu@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-gpio@vger.kernel.org
F: drivers/gpio/gpio-sama5d2-piobu.c
MICROCHIP SPI DRIVER
M: Nicolas Ferre <nicolas.ferre@microchip.com>
S: Supported
@ -10646,13 +10611,6 @@ S: Supported
F: drivers/misc/atmel-ssc.c
F: include/linux/atmel-ssc.h
MICROCHIP TIMER COUNTER (TC) AND CLOCKSOURCE DRIVERS
M: Nicolas Ferre <nicolas.ferre@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: drivers/misc/atmel_tclib.c
F: drivers/clocksource/tcb_clksrc.c
MICROCHIP USBA UDC DRIVER
M: Cristian Birsan <cristian.birsan@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -12694,6 +12652,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-gpio@vger.kernel.org
S: Supported
F: drivers/pinctrl/pinctrl-at91*
F: drivers/gpio/gpio-sama5d2-piobu.c
PIN CONTROLLER - FREESCALE
M: Dong Aisheng <aisheng.dong@nxp.com>
@ -14127,6 +14086,8 @@ M: Kamil Konieczny <k.konieczny@partner.samsung.com>
L: linux-crypto@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/samsung-slimsss.txt
F: Documentation/devicetree/bindings/crypto/samsung-sss.txt
F: drivers/crypto/s5p-sss.c
SAMSUNG S5P/EXYNOS4 SOC SERIES CAMERA SUBSYSTEM DRIVERS
@ -14147,6 +14108,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: Documentation/devicetree/bindings/clock/exynos*.txt
F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: Documentation/devicetree/bindings/clock/samsung,s5p*
SAMSUNG SPI DRIVERS
M: Kukjin Kim <kgene@kernel.org>

98
arch/arm/Kconfig
View File

@ -267,8 +267,6 @@ config PHYS_OFFSET
default 0x00000000 if ARCH_EBSA110 || \
ARCH_FOOTBRIDGE || \
ARCH_INTEGRATOR || \
ARCH_IOP13XX || \
ARCH_KS8695 || \
ARCH_REALVIEW
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x20000000 if ARCH_S5PV210
@ -381,19 +379,6 @@ config ARCH_FOOTBRIDGE
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
select CPU_XSC3
select NEED_MACH_MEMORY_H
select NEED_RET_TO_USER
select FORCE_PCI
select PLAT_IOP
select VMSPLIT_1G
select SPARSE_IRQ
help
Support for Intel's IOP13XX (XScale) family of processors.
config ARCH_IOP32X
bool "IOP32x-based"
depends on MMU
@ -407,18 +392,6 @@ config ARCH_IOP32X
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
config ARCH_IOP33X
bool "IOP33x-based"
depends on MMU
select CPU_XSCALE
select GPIO_IOP
select GPIOLIB
select NEED_RET_TO_USER
select FORCE_PCI
select PLAT_IOP
help
Support for Intel's IOP33X (XScale) family of processors.
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
@ -455,48 +428,6 @@ config ARCH_DOVE
help
Support for the Marvell Dove SoC 88AP510
config ARCH_KS8695
bool "Micrel/Kendin KS8695"
select CLKSRC_MMIO
select CPU_ARM922T
select GENERIC_CLOCKEVENTS
select GPIOLIB
select NEED_MACH_MEMORY_H
help
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
config ARCH_W90X900
bool "Nuvoton W90X900 CPU"
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select GPIOLIB
help
Support for Nuvoton (Winbond logic dept.) ARM9 processor,
At present, the w90x900 has been renamed nuc900, regarding
the ARM series product line, you can login the following
link address to know more.
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
config ARCH_LPC32XX
bool "NXP LPC32XX"
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_LPC32XX
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_MULTI_HANDLER
select GPIOLIB
select SPARSE_IRQ
select USE_OF
help
Support for the NXP LPC32XX family of processors
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@ -582,27 +513,6 @@ config ARCH_S3C24XX
(<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
Samsung SMDK2410 development board (and derivatives).
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
select COMMON_CLK
select CPU_ARM926T
select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select GENERIC_IRQ_MULTI_HANDLER
select GPIOLIB
select HAVE_IDE
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select REGMAP_MMIO
select RESET_CONTROLLER
select SPARSE_IRQ
select USE_OF
select ZONE_DMA
help
Support for TI's DaVinci platform.
config ARCH_OMAP1
bool "TI OMAP1"
depends on MMU
@ -738,17 +648,13 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop13xx/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-iop33x/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
@ -834,8 +740,6 @@ source "arch/arm/plat-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-w90x900/Kconfig"
source "arch/arm/mach-zx/Kconfig"
source "arch/arm/mach-zynq/Kconfig"

41
arch/arm/Kconfig.debug
View File

@ -509,13 +509,6 @@ choice
Say Y here if you want the debug print routines to direct
their output to UART1 serial port on KEYSTONE2 devices.
config DEBUG_KS8695_UART
bool "KS8695 Debug UART"
depends on ARCH_KS8695
help
Say Y here if you want kernel low-level debugging support
on KS8695.
config DEBUG_LPC18XX_UART0
bool "Kernel low-level debugging via LPC18xx/43xx UART0"
depends on ARCH_LPC18XX
@ -924,6 +917,20 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas RZ/A1H (R7S72100).
config DEBUG_R7S9210_SCIF2
bool "Kernel low-level debugging messages via SCIF2 on R7S9210"
depends on ARCH_R7S9210
help
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas RZ/A2M (R7S9210).
config DEBUG_R7S9210_SCIF4
bool "Kernel low-level debugging messages via SCIF4 on R7S9210"
depends on ARCH_R7S9210
help
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/A2M (R7S9210).
config DEBUG_RCAR_GEN1_SCIF0
bool "Kernel low-level debugging messages via SCIF0 on R8A7778"
depends on ARCH_R8A7778
@ -1533,10 +1540,11 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX6SX_UART || \
DEBUG_IMX6UL_UART || \
DEBUG_IMX7D_UART
default "debug/ks8695.S" if DEBUG_KS8695_UART
default "debug/msm.S" if DEBUG_QCOM_UARTDM
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF2
default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF4
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
@ -1568,9 +1576,7 @@ config DEBUG_UART_PL01X
# Compatibility options for 8250
config DEBUG_UART_8250
def_bool ARCH_EBSA110 || \
ARCH_IOP13XX || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || \
ARCH_RPC
def_bool ARCH_EBSA110 || ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC
config DEBUG_UART_PHYS
hex "Physical base address of debug UART"
@ -1666,7 +1672,8 @@ config DEBUG_UART_PHYS
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xe8008000 if DEBUG_R7S72100_SCIF2 || DEBUG_R7S9210_SCIF2
default 0xe8009000 if DEBUG_R7S9210_SCIF4
default 0xf0000000 if DEBUG_DIGICOLOR_UA0
default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
@ -1683,7 +1690,6 @@ config DEBUG_UART_PHYS
default 0xffc02000 if DEBUG_SOCFPGA_UART0
default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xffd82340 if ARCH_IOP13XX
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
default 0xfff36000 if DEBUG_HIGHBANK_UART
@ -1693,12 +1699,12 @@ config DEBUG_UART_PHYS
default 0xfffe8600 if DEBUG_BCM63XX_UART
default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU
default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
default 0xfffff700 if ARCH_IOP33X
depends on ARCH_EP93XX || \
DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_R7S9210_SCIF2 || DEBUG_R7S9210_SCIF4 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
@ -1772,10 +1778,7 @@ config DEBUG_UART_VIRT
default 0xfc705000 if DEBUG_ZTE_ZX
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
default 0xfd012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_MV78XX0
default 0xfd883000 if DEBUG_ALPINE_UART0
default 0xfde12000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_DOVE
default 0xfe012000 if DEBUG_MVEBU_UART0_ALTERNATE && ARCH_ORION5X
default 0xfe017000 if DEBUG_MMP_UART2
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
@ -1790,7 +1793,7 @@ config DEBUG_UART_VIRT
default 0xfec02000 if DEBUG_SOCFPGA_UART0
default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
@ -1805,14 +1808,12 @@ config DEBUG_UART_VIRT
default 0xfedc0000 if DEBUG_EP93XX
default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfee82340 if ARCH_IOP13XX
default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xfefff700 if ARCH_IOP33X
default 0xff003000 if DEBUG_U300_UART
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU

6
arch/arm/Makefile
View File

@ -155,6 +155,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
machine-$(CONFIG_ARCH_ACTIONS) += actions
machine-$(CONFIG_ARCH_ALPINE) += alpine
machine-$(CONFIG_ARCH_ARTPEC) += artpec
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
@ -173,12 +174,9 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
machine-$(CONFIG_ARCH_IOP32X) += iop32x
machine-$(CONFIG_ARCH_IOP33X) += iop33x
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
@ -222,7 +220,6 @@ machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_W90X900) += w90x900
machine-$(CONFIG_ARCH_ZX) += zx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_SPEAR) += spear
@ -233,7 +230,6 @@ plat-$(CONFIG_ARCH_EXYNOS) += samsung
plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_ARCH_S5PV210) += samsung
plat-$(CONFIG_PLAT_IOP) += iop
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung

77
arch/arm/configs/acs5k_defconfig
View File

@ -1,77 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_KS8695=y
CONFIG_MACH_KS8695=y
CONFIG_MACH_DSM320=y
CONFIG_MACH_ACS5K=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCI=y
CONFIG_PCI_DEBUG=y
CONFIG_PCCARD=y
CONFIG_YENTA=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_KS8695_ETHER=y
CONFIG_PRISM54=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_KS8695=y
CONFIG_SERIAL_KS8695_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCA953X=y
CONFIG_WATCHDOG=y
CONFIG_KS8695_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_EXT2_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_RUBIN=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

69
arch/arm/configs/acs5k_tiny_defconfig
View File

@ -1,69 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_KS8695=y
CONFIG_MACH_ACS5K=y
# CONFIG_ARM_THUMB is not set
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAM0,115200 init=/bin/sh"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_KS8695_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_KS8695=y
CONFIG_SERIAL_KS8695_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCA953X=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_KS8695_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_RUBIN=y
CONFIG_SQUASHFS=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y

5
arch/arm/configs/davinci_all_defconfig
View File

@ -17,6 +17,9 @@ CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V7=n
CONFIG_ARCH_MULTI_V5=y
CONFIG_ARCH_DAVINCI=y
CONFIG_ARCH_DAVINCI_DM644x=y
CONFIG_ARCH_DAVINCI_DM355=y
@ -129,9 +132,11 @@ CONFIG_SPI=y
CONFIG_SPI_DAVINCI=m
CONFIG_PINCTRL_DA850_PUPD=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_RESET_CONTROLLER=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_SYSCON_REBOOT_MODE=m

118
arch/arm/configs/iop13xx_defconfig
View File

@ -1,118 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_IOP13XX=y
CONFIG_MACH_IQ81340SC=y
CONFIG_MACH_IQ81340MC=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=2
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=y
CONFIG_MD_RAID456=y
CONFIG_BLK_DEV_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_IOP3XX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_DMADEVICES=y
CONFIG_INTEL_IOP_ADMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_TMPFS=y
CONFIG_ECRYPT_FS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
CONFIG_SMB_FS=m
CONFIG_CIFS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS=y
CONFIG_DEBUG_USER=y
CONFIG_KEYS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRC_CCITT=y
CONFIG_LIBCRC32C=y

85
arch/arm/configs/iop33x_defconfig
View File

@ -1,85 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_IOP33X=y
CONFIG_ARCH_IQ80331=y
CONFIG_MACH_IQ80332=y
# CONFIG_ARM_THUMB is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc iop3xx_init_atu=y"
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID456=y
CONFIG_BLK_DEV_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IOP3XX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_DMADEVICES=y
CONFIG_INTEL_IOP_ADMA=y
CONFIG_NET_DMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_UART_8250=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRC32 is not set

67
arch/arm/configs/ks8695_defconfig
View File

@ -1,67 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_KS8695=y
CONFIG_MACH_KS8695=y
CONFIG_MACH_DSM320=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCI=y
CONFIG_PCI_DEBUG=y
CONFIG_PCCARD=y
CONFIG_YENTA=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_PRISM54=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_KS8695=y
CONFIG_SERIAL_KS8695_CONSOLE=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_EXT2_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_RUBIN=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

1
arch/arm/configs/lpc32xx_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_LPC32XX=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0

12
arch/arm/configs/multi_v5_defconfig
View File

@ -14,6 +14,18 @@ CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G4=y
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91SAM9=y
CONFIG_ARCH_DAVINCI=y
CONFIG_ARCH_DAVINCI_DM644x=y
CONFIG_ARCH_DAVINCI_DM355=y
CONFIG_ARCH_DAVINCI_DM646x=y
CONFIG_ARCH_DAVINCI_DA830=y
CONFIG_ARCH_DAVINCI_DA850=y
CONFIG_ARCH_DAVINCI_DM365=y
CONFIG_MACH_SFFSDR=y
CONFIG_MACH_NEUROS_OSD2=y
CONFIG_MACH_DM355_LEOPARD=y
CONFIG_MACH_MITYOMAPL138=y
CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_MX21ADS=y
CONFIG_MACH_MX27ADS=y

51
arch/arm/configs/nuc910_defconfig
View File

@ -1,51 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y
CONFIG_ARCH_W90X900=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_STORAGE=y
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
# CONFIG_CRC32 is not set

67
arch/arm/configs/nuc950_defconfig
View File

@ -1,67 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y
CONFIG_ARCH_W90X900=y
# CONFIG_MACH_W90P910EVB is not set
CONFIG_MACH_W90P950EVB=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_AOUT=y
CONFIG_BINFMT_MISC=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_NUC900=y
CONFIG_GPM1040A0_320X240=y
CONFIG_FB_NUC900_DEBUG=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FONTS=y
CONFIG_FONT_8x16=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_STORAGE=y
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y

57
arch/arm/configs/nuc960_defconfig
View File

@ -1,57 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y
CONFIG_ARCH_W90X900=y
# CONFIG_MACH_W90P910EVB is not set
CONFIG_MACH_W90N960EVB=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_AOUT=y
CONFIG_BINFMT_MISC=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_STORAGE=y
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
# CONFIG_CRC32 is not set

37
arch/arm/include/debug/ks8695.S
View File

@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/debug/ks8695.S
*
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
* Copyright (C) 2006 Simtec Electronics
*
* KS8695 - Debug macros
*/
#define KS8695_UART_PA 0x03ffe000
#define KS8695_UART_VA 0xf00fe000
#define KS8695_URTH (0x04)
#define KS8695_URLS (0x14)
#define URLS_URTE (1 << 6)
#define URLS_URTHRE (1 << 5)
.macro addruart, rp, rv, tmp
ldr \rp, =KS8695_UART_PA @ physical base address
ldr \rv, =KS8695_UART_VA @ virtual base address
.endm
.macro senduart, rd, rx
str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register
.endm
.macro busyuart, rd, rx
1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
tst \rd, #URLS_URTE @ Holding & Shift registers empty?
beq 1001b
.endm
.macro waituart, rd, rx
1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
tst \rd, #URLS_URTHRE @ Holding Register empty?
beq 1001b
.endm

6
arch/arm/include/debug/renesas-scif.S
View File

@ -11,7 +11,11 @@
#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS
#define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000
#if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
/* RZ/A2 SCIFA */
#define FTDR 0x06
#define FSR 0x08
#elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
/* SCIFA */
#define FTDR 0x20
#define FSR 0x14

9
arch/arm/include/debug/ux500.S
View File

@ -20,21 +20,16 @@
#define U8500_UART0_PHYS_BASE (0x80120000)
#define U8500_UART1_PHYS_BASE (0x80121000)
#define U8500_UART2_PHYS_BASE (0x80007000)
#define U8500_UART0_VIRT_BASE (0xf8120000)
#define U8500_UART1_VIRT_BASE (0xf8121000)
#define U8500_UART2_VIRT_BASE (0xf8007000)
#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE
#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE
#endif
#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART)
#if !defined(__UX500_PHYS_UART)
#error Unknown SOC
#endif
#define UX500_PHYS_UART(n) __UX500_PHYS_UART(n)
#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n)
#define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART)
#define UART_VIRT_BASE (0xfff07000)
.macro addruart, rp, rv, tmp
ldr \rp, =UART_PHYS_BASE @ no, physical address

17
arch/arm/mach-aspeed/Kconfig
View File

@ -1,11 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_ASPEED
bool "Aspeed BMC architectures"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7
select SRAM
select WATCHDOG
select ASPEED_WATCHDOG
select FTTMR010_TIMER
select MFD_SYSCON
select PINCTRL
help
@ -18,6 +17,7 @@ config MACH_ASPEED_G4
depends on ARCH_MULTI_V5
select CPU_ARM926T
select PINCTRL_ASPEED_G4
select FTTMR010_TIMER
help
Say yes if you intend to run on an Aspeed ast2400 or similar
fourth generation BMCs, such as those used by OpenPower Power8
@ -28,8 +28,21 @@ config MACH_ASPEED_G5
depends on ARCH_MULTI_V6
select CPU_V6
select PINCTRL_ASPEED_G5
select FTTMR010_TIMER
help
Say yes if you intend to run on an Aspeed ast2500 or similar
fifth generation Aspeed BMCs.
config MACH_ASPEED_G6
bool "Aspeed SoC 6th Generation"
depends on ARCH_MULTI_V7
select CPU_V7
select PINCTRL_ASPEED_G6
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
select HAVE_SMP
help
Say yes if you intend to run on an Aspeed ast2600 or similar
sixth generation Aspeed BMCs.
endif

5
arch/arm/mach-aspeed/Makefile 100644
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (C) ASPEED Technology Inc.
# Copyright IBM Corp.
obj-$(CONFIG_SMP) += platsmp.o

61
arch/arm/mach-aspeed/platsmp.c 100644
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright (C) ASPEED Technology Inc.
// Copyright IBM Corp.
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/smp.h>
#define BOOT_ADDR 0x00
#define BOOT_SIG 0x04
static struct device_node *secboot_node;
static int aspeed_g6_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
void __iomem *base;
base = of_iomap(secboot_node, 0);
if (!base) {
pr_err("could not map the secondary boot base!");
return -ENODEV;
}
writel_relaxed(0, base + BOOT_ADDR);
writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR);
writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG);
dsb_sev();
iounmap(base);
return 0;
}
static void __init aspeed_g6_smp_prepare_cpus(unsigned int max_cpus)
{
void __iomem *base;
secboot_node = of_find_compatible_node(NULL, NULL, "aspeed,ast2600-smpmem");
if (!secboot_node) {
pr_err("secboot device node found!!\n");
return;
}
base = of_iomap(secboot_node, 0);
if (!base) {
pr_err("could not map the secondary boot base!");
return;
}
__raw_writel(0xBADABABA, base + BOOT_SIG);
iounmap(base);
}
static const struct smp_operations aspeed_smp_ops __initconst = {
.smp_prepare_cpus = aspeed_g6_smp_prepare_cpus,
.smp_boot_secondary = aspeed_g6_boot_secondary,
};
CPU_METHOD_OF_DECLARE(aspeed_smp, "aspeed,ast2600-smp", &aspeed_smp_ops);

1
arch/arm/mach-at91/.gitignore vendored 100644
View File

@ -0,0 +1 @@
pm_data-offsets.h

5
arch/arm/mach-at91/Makefile
View File

@ -19,9 +19,10 @@ ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
endif
include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE
$(obj)/pm_data-offsets.h: $(obj)/pm_data-offsets.s FORCE
$(call filechk,offsets,__PM_DATA_OFFSETS_H__)
arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h
$(obj)/pm_suspend.o: $(obj)/pm_data-offsets.h
targets += pm_data-offsets.s
clean-files += pm_data-offsets.h

2
arch/arm/mach-at91/pm_suspend.S
View File

@ -10,7 +10,7 @@
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
#include "pm.h"
#include "generated/at91_pm_data-offsets.h"
#include "pm_data-offsets.h"
#define SRAMC_SELF_FRESH_ACTIVE 0x01
#define SRAMC_SELF_FRESH_EXIT 0x00

17
arch/arm/mach-davinci/Kconfig
View File

@ -1,11 +1,22 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_DAVINCI
bool "TI DaVinci"
depends on ARCH_MULTI_V5
select DAVINCI_TIMER
select ZONE_DMA
select ARCH_HAS_HOLES_MEMORYMODEL
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select REGMAP_MMIO
select HAVE_IDE
select PINCTRL_SINGLE
if ARCH_DAVINCI
config ARCH_DAVINCI_DMx
bool
menu "TI DaVinci Implementations"
comment "DaVinci Core Type"
config ARCH_DAVINCI_DM644x
@ -225,6 +236,4 @@ config DAVINCI_MUX_WARNINGS
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect DAVINCI_MUX for your product.
endmenu
endif

2
arch/arm/mach-davinci/Makefile
View File

@ -4,6 +4,8 @@
#
#
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
# Common objects
obj-y := time.o serial.o usb.o \
common.o sram.o

45
arch/arm/mach-davinci/da830.c
View File

@ -21,7 +21,8 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h"
#include "mux.h"
@ -676,32 +677,17 @@ int __init da830_register_gpio(void)
return da8xx_register_gpio(&da830_gpio_platform_data);
}
static struct davinci_timer_instance da830_timer_instance[2] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
.cmp_off = DA830_CMP12_0,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
.cmp_off = DA830_CMP12_0,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1),
},
};
/*
* T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
* T0_TOP: Timer 0, top : Used by DSP
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
* Bottom half of timer0 is used both for clock even and clocksource.
* Top half is used by DSP.
*/
static struct davinci_timer_info da830_timer_info = {
.timers = da830_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_BOT,
static const struct davinci_timer_cfg da830_timer_cfg = {
.reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
},
.cmp_off = DA830_CMP12_0,
};
static const struct davinci_soc_info davinci_soc_info_da830 = {
@ -713,7 +699,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
.timer_info = &da830_timer_info,
.emac_pdata = &da8xx_emac_pdata,
};
@ -743,6 +728,7 @@ void __init da830_init_time(void)
{
void __iomem *pll;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
@ -751,8 +737,13 @@ void __init da830_init_time(void)
da830_pll_init(NULL, pll, NULL);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &da830_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource da830_psc0_resources[] = {

50
arch/arm/mach-davinci/da850.c
View File

@ -35,7 +35,8 @@
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/pm.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h"
#include "mux.h"
@ -333,38 +334,16 @@ static struct davinci_id da850_ids[] = {
},
};
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
},
{
.base = DA850_TIMER64P2_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
},
{
.base = DA850_TIMER64P3_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
},
};
/*
* T0_BOT: Timer 0, bottom : Used for clock_event
* T0_TOP: Timer 0, top : Used for clocksource
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
* Bottom half of timer 0 is used for clock_event, top half for
* clocksource.
*/
static struct davinci_timer_info da850_timer_info = {
.timers = da850_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg da850_timer_cfg = {
.reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
},
};
#ifdef CONFIG_CPU_FREQ
@ -635,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
.timer_info = &da850_timer_info,
.emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE,
.sram_len = SZ_128K,
@ -672,6 +650,7 @@ void __init da850_init_time(void)
void __iomem *pll0;
struct regmap *cfgchip;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
@ -681,8 +660,13 @@ void __init da850_init_time(void)
da850_pll0_init(NULL, pll0, cfgchip);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &da850_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource da850_pll1_resources[] = {

3
arch/arm/mach-davinci/davinci.h
View File

@ -60,6 +60,9 @@ void davinci_map_sysmod(void);
#define DAVINCI_GPIO_BASE 0x01C67000
int davinci_gpio_register(struct resource *res, int size, void *pdata);
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
/* DM355 base addresses */
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000

28
arch/arm/mach-davinci/dm355.c
View File

@ -30,7 +30,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -620,15 +621,15 @@ static struct davinci_id dm355_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm355_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm355_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm355_serial0_platform_data[] = {
@ -706,7 +707,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm355_pins,
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
.timer_info = &dm355_timer_info,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
};
@ -733,6 +733,7 @@ void __init dm355_init_time(void)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
@ -743,8 +744,13 @@ void __init dm355_init_time(void)
dm355_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm355_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm355_pll2_resources[] = {

4
arch/arm/mach-davinci/dm365.c
View File

@ -784,6 +784,10 @@ void __init dm365_init_time(void)
dm365_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
}

28
arch/arm/mach-davinci/dm644x.c
View File

@ -27,7 +27,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -561,15 +562,15 @@ static struct davinci_id dm644x_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm644x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm644x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
@ -647,7 +648,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
.timer_info = &dm644x_timer_info,
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
.sram_len = SZ_16K,
@ -669,6 +669,7 @@ void __init dm644x_init_time(void)
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
@ -679,8 +680,13 @@ void __init dm644x_init_time(void)
dm644x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm644x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm644x_pll2_resources[] = {

30
arch/arm/mach-davinci/dm646x.c
View File

@ -1,5 +1,5 @@
/*
* TI DaVinci DM644x chip specific setup
* TI DaVinci DM646x chip specific setup
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
@ -28,7 +28,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@ -501,15 +502,15 @@ static struct davinci_id dm646x_ids[] = {
};
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
* Bottom half of timer0 is used for clockevent, top half is used for
* clocksource.
*/
static struct davinci_timer_info dm646x_timer_info = {
.timers = davinci_timer_instance,
.clockevent_id = T0_BOT,
.clocksource_id = T0_TOP,
static const struct davinci_timer_cfg dm646x_timer_cfg = {
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
.irq = {
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
},
};
static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
@ -587,7 +588,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
.timer_info = &dm646x_timer_info,
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
.sram_len = SZ_32K,
@ -652,6 +652,7 @@ void __init dm646x_init_time(unsigned long ref_clk_rate,
{
void __iomem *pll1, *psc;
struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
@ -663,8 +664,13 @@ void __init dm646x_init_time(unsigned long ref_clk_rate,
dm646x_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
if (WARN_ON(IS_ERR(clk))) {
pr_err("Unable to get the timer clock\n");
return;
}
davinci_timer_init(clk);
rv = davinci_timer_register(clk, &dm646x_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
}
static struct resource dm646x_pll2_resources[] = {

2
arch/arm/mach-davinci/include/mach/time.h
View File

@ -11,9 +11,7 @@
#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
#define __ARCH_ARM_MACH_DAVINCI_TIME_H
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
enum {
T0_BOT,

14
arch/arm/mach-davinci/time.c
View File

@ -398,17 +398,3 @@ void __init davinci_timer_init(struct clk *timer_clk)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
}
static int __init of_davinci_timer_init(struct device_node *np)
{
struct clk *clk;
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
return PTR_ERR(clk);
davinci_timer_init(clk);
return 0;
}
TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_init);

4
arch/arm/mach-dove/include/mach/bridge-regs.h → arch/arm/mach-dove/bridge-regs.h
View File

@ -1,6 +1,4 @@
/*
* arch/arm/mach-dove/include/mach/bridge-regs.h
*
* Mbus-L to Mbus Bridge Registers
*
* This file is licensed under the terms of the GNU General Public
@ -11,7 +9,7 @@
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/dove.h>
#include "dove.h"
#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)

3
arch/arm/mach-dove/cm-a510.c
View File

@ -22,8 +22,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dove.h>
#include "dove.h"
#include "common.h"
static struct mv643xx_eth_platform_data cm_a510_ge00_data = {

4
arch/arm/mach-dove/common.c
View File

@ -22,11 +22,11 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "bridge-regs.h"
#include "pm.h"
#include "common.h"
/* These can go away once Dove uses the mvebu-mbus DT binding */

2
arch/arm/mach-dove/dove-db-setup.c
View File

@ -24,7 +24,7 @@
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dove.h>
#include "dove.h"
#include "common.h"
static struct mv643xx_eth_platform_data dove_db_ge00_data = {

14
arch/arm/mach-dove/include/mach/dove.h → arch/arm/mach-dove/dove.h
View File

@ -1,6 +1,4 @@
/*
* arch/arm/mach-dove/include/mach/dove.h
*
* Generic definitions for Marvell Dove 88AP510 SoC
*
* This file is licensed under the terms of the GNU General Public
@ -11,7 +9,7 @@
#ifndef __ASM_ARCH_DOVE_H
#define __ASM_ARCH_DOVE_H
#include <mach/irqs.h>
#include "irqs.h"
/*
* Marvell Dove address maps.
@ -20,8 +18,8 @@
* c8000000 fdb00000 1M Cryptographic SRAM
* e0000000 @runtime 128M PCIe-0 Memory space
* e8000000 @runtime 128M PCIe-1 Memory space
* f1000000 fde00000 8M on-chip south-bridge registers
* f1800000 fe600000 8M on-chip north-bridge registers
* f1000000 fec00000 1M on-chip south-bridge registers
* f1800000 fe400000 8M on-chip north-bridge registers
* f2000000 fee00000 1M PCIe-0 I/O space
* f2100000 fef00000 1M PCIe-1 I/O space
*/
@ -44,11 +42,11 @@
#define DOVE_SCRATCHPAD_SIZE SZ_1M
#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
#define DOVE_SB_REGS_SIZE SZ_8M
#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
#define DOVE_SB_REGS_SIZE SZ_1M
#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
#define DOVE_NB_REGS_SIZE SZ_8M
#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000

19
arch/arm/mach-dove/include/mach/hardware.h
View File

@ -1,19 +0,0 @@
/*
* arch/arm/mach-dove/include/mach/hardware.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "dove.h"
/* Macros below are required for compatibility with PXA AC'97 driver. */
#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
DOVE_SB_REGS_VIRT_BASE)))
#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
DOVE_SB_REGS_PHYS_BASE)
#endif

8
arch/arm/mach-dove/include/mach/uncompress.h
View File

@ -1,15 +1,13 @@
/*
* arch/arm/mach-dove/include/mach/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/dove.h>
#define UART0_PHYS_BASE (0xf1000000 + 0x12000)
#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
#define LSR_THRE 0x20

5
arch/arm/mach-dove/irq.c
View File

@ -11,9 +11,12 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/exception.h>
#include <plat/irq.h>
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include "pm.h"
#include "bridge-regs.h"
#include "common.h"
static int __initdata gpio0_irqs[4] = {

2
arch/arm/mach-dove/include/mach/irqs.h → arch/arm/mach-dove/irqs.h
View File

@ -1,6 +1,4 @@
/*
* arch/arm/mach-dove/include/mach/irqs.h
*
* IRQ definitions for Marvell Dove 88AP510 SoC
*
* This file is licensed under the terms of the GNU General Public

2
arch/arm/mach-dove/mpp.c
View File

@ -12,8 +12,8 @@
#include <linux/gpio.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include <mach/dove.h>
#include <plat/orion-gpio.h>
#include "dove.h"
#include "mpp.h"
struct dove_mpp_grp {

4
arch/arm/mach-dove/pcie.c
View File

@ -17,9 +17,9 @@
#include <asm/setup.h>
#include <asm/delay.h>
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
#include <plat/addr-map.h>
#include "irqs.h"
#include "bridge-regs.h"
#include "common.h"
struct pcie_port {

4
arch/arm/mach-dove/include/mach/pm.h → arch/arm/mach-dove/pm.h
View File

@ -1,6 +1,4 @@
/*
* arch/arm/mach-dove/include/mach/pm.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
@ -10,7 +8,7 @@
#define __ASM_ARCH_PM_H
#include <asm/errno.h>
#include <mach/irqs.h>
#include "irqs.h"
#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
#define CLOCK_GATING_BIT_USB0 0

1
arch/arm/mach-exynos/Kconfig
View File

@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS
select ARM_AMBA
select ARM_GIC
select COMMON_CLK_SAMSUNG
select EXYNOS_CHIPID
select EXYNOS_THERMAL
select EXYNOS_PMU
select EXYNOS_SROM

6
arch/arm/mach-imx/mach-imx7d.c
View File

@ -30,12 +30,6 @@ static int ar8031_phy_fixup(struct phy_device *dev)
val &= ~(0x1 << 8);
phy_write(dev, 0xe, val);
/* introduce tx clock delay */
phy_write(dev, 0x1d, 0x5);
val = phy_read(dev, 0x1e);
val |= 0x0100;
phy_write(dev, 0x1e, val);
return 0;
}

21
arch/arm/mach-iop13xx/Kconfig
View File

@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
if ARCH_IOP13XX
menu "IOP13XX Implementation Options"
comment "IOP13XX Platform Support"
config MACH_IQ81340SC
bool "Enable IQ81340SC Hardware Support"
help
Say Y here if you want to support running on the Intel IQ81340SC
evaluation kit.
config MACH_IQ81340MC
bool "Enable IQ81340MC Hardware Support"
help
Say Y here if you want to support running on the Intel IQ81340MC
evaluation kit.
endmenu
endif

9
arch/arm/mach-iop13xx/Makefile
View File

@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARCH_IOP13XX) += setup.o
obj-$(CONFIG_ARCH_IOP13XX) += irq.o
obj-$(CONFIG_ARCH_IOP13XX) += pci.o
obj-$(CONFIG_ARCH_IOP13XX) += io.o
obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o
obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
obj-$(CONFIG_PCI_MSI) += msi.o

4
arch/arm/mach-iop13xx/Makefile.boot
View File

@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

608
arch/arm/mach-iop13xx/include/mach/adma.h
View File

@ -1,608 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright(c) 2006, Intel Corporation.
*/
#ifndef _ADMA_H
#define _ADMA_H
#include <linux/types.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/hardware/iop_adma.h>
#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
#define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
#define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
struct iop13xx_adma_src {
u32 src_addr;
union {
u32 upper_src_addr;
struct {
unsigned int pq_upper_src_addr:24;
unsigned int pq_dmlt:8;
};
};
};
struct iop13xx_adma_desc_ctrl {
unsigned int int_en:1;
unsigned int xfer_dir:2;
unsigned int src_select:4;
unsigned int zero_result:1;
unsigned int block_fill_en:1;
unsigned int crc_gen_en:1;
unsigned int crc_xfer_dis:1;
unsigned int crc_seed_fetch_dis:1;
unsigned int status_write_back_en:1;
unsigned int endian_swap_en:1;
unsigned int reserved0:2;
unsigned int pq_update_xfer_en:1;
unsigned int dual_xor_en:1;
unsigned int pq_xfer_en:1;
unsigned int p_xfer_dis:1;
unsigned int reserved1:10;
unsigned int relax_order_en:1;
unsigned int no_snoop_en:1;
};
struct iop13xx_adma_byte_count {
unsigned int byte_count:24;
unsigned int host_if:3;
unsigned int reserved:2;
unsigned int zero_result_err_q:1;
unsigned int zero_result_err:1;
unsigned int tx_complete:1;
};
struct iop13xx_adma_desc_hw {
u32 next_desc;
union {
u32 desc_ctrl;
struct iop13xx_adma_desc_ctrl desc_ctrl_field;
};
union {
u32 crc_addr;
u32 block_fill_data;
u32 q_dest_addr;
};
union {
u32 byte_count;
struct iop13xx_adma_byte_count byte_count_field;
};
union {
u32 dest_addr;
u32 p_dest_addr;
};
union {
u32 upper_dest_addr;
u32 pq_upper_dest_addr;
};
struct iop13xx_adma_src src[1];
};
struct iop13xx_adma_desc_dual_xor {
u32 next_desc;
u32 desc_ctrl;
u32 reserved;
u32 byte_count;
u32 h_dest_addr;
u32 h_upper_dest_addr;
u32 src0_addr;
u32 upper_src0_addr;
u32 src1_addr;
u32 upper_src1_addr;
u32 h_src_addr;
u32 h_upper_src_addr;
u32 d_src_addr;
u32 d_upper_src_addr;
u32 d_dest_addr;
u32 d_upper_dest_addr;
};
struct iop13xx_adma_desc_pq_update {
u32 next_desc;
u32 desc_ctrl;
u32 reserved;
u32 byte_count;
u32 p_dest_addr;
u32 p_upper_dest_addr;
u32 src0_addr;
u32 upper_src0_addr;
u32 src1_addr;
u32 upper_src1_addr;
u32 p_src_addr;
u32 p_upper_src_addr;
u32 q_src_addr;
struct {
unsigned int q_upper_src_addr:24;
unsigned int q_dmlt:8;
};
u32 q_dest_addr;
u32 q_upper_dest_addr;
};
static inline int iop_adma_get_max_xor(void)
{
return 16;
}
#define iop_adma_get_max_pq iop_adma_get_max_xor
static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
{
return __raw_readl(ADMA_ADAR(chan));
}
static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
u32 next_desc_addr)
{
__raw_writel(next_desc_addr, ADMA_ANDAR(chan));
}
#define ADMA_STATUS_BUSY (1 << 13)
static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
{
if (__raw_readl(ADMA_ACSR(chan)) &
ADMA_STATUS_BUSY)
return 1;
else
return 0;
}
static inline int
iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
{
return 1;
}
#define iop_desc_is_aligned(x, y) 1
static inline int
iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
{
*slots_per_op = 1;
return 1;
}
#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
static inline int
iop_chan_memset_slot_count(size_t len, int *slots_per_op)
{
*slots_per_op = 1;
return 1;
}
static inline int
iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
{
static const char slot_count_table[] = { 1, 2, 2, 2,
2, 3, 3, 3,
3, 4, 4, 4,
4, 5, 5, 5,
};
*slots_per_op = slot_count_table[src_cnt - 1];
return *slots_per_op;
}
#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
#define iop_chan_pq_slot_count iop_chan_xor_slot_count
#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count
static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
return hw_desc->byte_count_field.byte_count;
}
static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan,
int src_idx)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
return hw_desc->src[src_idx].src_addr;
}
static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
return hw_desc->desc_ctrl_field.src_select + 1;
}
static inline void
iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
hw_desc->crc_addr = 0;
}
static inline void
iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.block_fill_en = 1;
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
hw_desc->crc_addr = 0;
}
/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
static inline void
iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.src_select = src_cnt - 1;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
hw_desc->crc_addr = 0;
}
#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
static inline int
iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.src_select = src_cnt - 1;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.zero_result = 1;
u_desc_ctrl.field.status_write_back_en = 1;
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
hw_desc->crc_addr = 0;
return 1;
}
static inline void
iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.src_select = src_cnt - 1;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.pq_xfer_en = 1;
u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
}
static inline void
iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
unsigned long flags)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
union {
u32 value;
struct iop13xx_adma_desc_ctrl field;
} u_desc_ctrl;
u_desc_ctrl.value = 0;
u_desc_ctrl.field.src_select = src_cnt - 1;
u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
u_desc_ctrl.field.zero_result = 1;
u_desc_ctrl.field.status_write_back_en = 1;
u_desc_ctrl.field.pq_xfer_en = 1;
u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
hw_desc->desc_ctrl = u_desc_ctrl.value;
}
static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan,
u32 byte_count)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->byte_count = byte_count;
}
static inline void
iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
{
int slots_per_op = desc->slots_per_op;
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
int i = 0;
if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
hw_desc->byte_count = len;
} else {
do {
iter = iop_hw_desc_slot_idx(hw_desc, i);
iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
i += slots_per_op;
} while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
if (len) {
iter = iop_hw_desc_slot_idx(hw_desc, i);
iter->byte_count = len;
}
}
}
#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count
static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan,
dma_addr_t addr)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->dest_addr = addr;
hw_desc->upper_dest_addr = 0;
}
static inline void
iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->dest_addr = addr[0];
hw_desc->q_dest_addr = addr[1];
hw_desc->upper_dest_addr = 0;
}
static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
dma_addr_t addr)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->src[0].src_addr = addr;
hw_desc->src[0].upper_src_addr = 0;
}
static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
int src_idx, dma_addr_t addr)
{
int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
int i = 0;
do {
iter = iop_hw_desc_slot_idx(hw_desc, i);
iter->src[src_idx].src_addr = addr;
iter->src[src_idx].upper_src_addr = 0;
slot_cnt -= slots_per_op;
if (slot_cnt) {
i += slots_per_op;
addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
}
} while (slot_cnt);
}
static inline void
iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
dma_addr_t addr, unsigned char coef)
{
int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
struct iop13xx_adma_src *src;
int i = 0;
do {
iter = iop_hw_desc_slot_idx(hw_desc, i);
src = &iter->src[src_idx];
src->src_addr = addr;
src->pq_upper_src_addr = 0;
src->pq_dmlt = coef;
slot_cnt -= slots_per_op;
if (slot_cnt) {
i += slots_per_op;
addr += IOP_ADMA_PQ_MAX_BYTE_COUNT;
}
} while (slot_cnt);
}
static inline void
iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
struct iop_adma_chan *chan)
{
iop_desc_init_memcpy(desc, 1);
iop_desc_set_byte_count(desc, chan, 0);
iop_desc_set_dest_addr(desc, chan, 0);
iop_desc_set_memcpy_src_addr(desc, 0);
}
#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
static inline void
iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
dma_addr_t *src)
{
iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]);
iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]);
}
static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
u32 next_desc_addr)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
iop_paranoia(hw_desc->next_desc);
hw_desc->next_desc = next_desc_addr;
}
static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
return hw_desc->next_desc;
}
static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->next_desc = 0;
}
static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
u32 val)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
hw_desc->block_fill_data = val;
}
static inline enum sum_check_flags
iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
{
struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
enum sum_check_flags flags;
BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
flags = byte_count.zero_result_err_q << SUM_CHECK_Q;
flags |= byte_count.zero_result_err << SUM_CHECK_P;
return flags;
}
static inline void iop_chan_append(struct iop_adma_chan *chan)
{
u32 adma_accr;
adma_accr = __raw_readl(ADMA_ACCR(chan));
adma_accr |= 0x2;
__raw_writel(adma_accr, ADMA_ACCR(chan));
}
static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
{
return __raw_readl(ADMA_ACSR(chan));
}
static inline void iop_chan_disable(struct iop_adma_chan *chan)
{
u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
adma_chan_ctrl &= ~0x1;
__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
}
static inline void iop_chan_enable(struct iop_adma_chan *chan)
{
u32 adma_chan_ctrl;
adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
adma_chan_ctrl |= 0x1;
__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
}
static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
{
u32 status = __raw_readl(ADMA_ACSR(chan));
status &= (1 << 12);
__raw_writel(status, ADMA_ACSR(chan));
}
static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
{
u32 status = __raw_readl(ADMA_ACSR(chan));
status &= (1 << 11);
__raw_writel(status, ADMA_ACSR(chan));
}
static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
{
u32 status = __raw_readl(ADMA_ACSR(chan));
status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
__raw_writel(status, ADMA_ACSR(chan));
}
static inline int
iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
{
return test_bit(9, &status);
}
static inline int
iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
{
return test_bit(5, &status);
}
static inline int
iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
{
return test_bit(4, &status);
}
static inline int
iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
{
return test_bit(3, &status);
}
static inline int
iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
{
return 0;
}
static inline int
iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
{
return 0;
}
static inline int
iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
{
return 0;
}
#endif /* _ADMA_H */

29
arch/arm/mach-iop13xx/include/mach/entry-macro.S
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@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* iop13xx low level irq macros
* Copyright (c) 2005-2006, Intel Corporation.
*/
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
.endm
/*
* Note: a 1-cycle window exists where iintvec will return the value
* of iintbase, so we explicitly check for "bad zeros"
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
cmp \irqnr, #0
mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
.endm
.macro arch_ret_to_user, tmp1, tmp2
mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm

22
arch/arm/mach-iop13xx/include/mach/hardware.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/types.h>
#ifndef __ASSEMBLY__
extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void);
#endif
/*
* Generic chipset bits
*
*/
#include "iop13xx.h"
/*
* Board specific bits
*/
#include "iq81340.h"
#endif /* _ASM_ARCH_HARDWARE_H */

508
arch/arm/mach-iop13xx/include/mach/iop13xx.h
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@ -1,508 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_HW_H_
#define _IOP13XX_HW_H_
#ifndef __ASSEMBLY__
enum reboot_mode;
/* The ATU offsets can change based on the strapping */
extern u32 iop13xx_atux_pmmr_offset;
extern u32 iop13xx_atue_pmmr_offset;
void iop13xx_init_early(void);
void iop13xx_init_irq(void);
void iop13xx_map_io(void);
void iop13xx_platform_init(void);
void iop13xx_add_tpmi_devices(void);
void iop13xx_init_irq(void);
void iop13xx_restart(enum reboot_mode, const char *);
/* CPUID CP6 R0 Page 0 */
static inline int iop13xx_cpu_id(void)
{
int id;
asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
return id;
}
/* WDTCR CP6 R7 Page 9 */
static inline u32 read_wdtcr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtcr(u32 val)
{
asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
}
/* WDTSR CP6 R8 Page 9 */
static inline u32 read_wdtsr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtsr(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
}
/* RCSR - Reset Cause Status Register */
static inline u32 read_rcsr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
return val;
}
extern unsigned long get_iop_tick_rate(void);
#endif
/*
* IOP13XX I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
/* PCI MAP
* bus range cpu phys cpu virt note
* 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
* 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
* 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
*
* IO MAP
* 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
* 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
*/
#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
IOP13XX_PCIX_LOWER_MEM_BA)
#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
IOP13XX_PCIX_LOWER_MEM_BA)
/* PCI-E ranges */
#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
IOP13XX_PCIE_LOWER_MEM_BA)
#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
IOP13XX_PCIE_LOWER_MEM_BA)
/* PBI Ranges */
#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
/*
* IOP13XX chipset registers
*/
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+ IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+ IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
/* ATU selection flags */
/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
#define IOP13XX_INIT_ATU_DEFAULT (0)
#define IOP13XX_INIT_ATU_ATUX (1 << 0)
#define IOP13XX_INIT_ATU_ATUE (1 << 1)
#define IOP13XX_INIT_ATU_NONE (1 << 2)
/* UART selection flags */
/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
#define IOP13XX_INIT_UART_DEFAULT (0)
#define IOP13XX_INIT_UART_0 (1 << 0)
#define IOP13XX_INIT_UART_1 (1 << 1)
/* I2C selection flags */
/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
#define IOP13XX_INIT_I2C_DEFAULT (0)
#define IOP13XX_INIT_I2C_0 (1 << 0)
#define IOP13XX_INIT_I2C_1 (1 << 1)
#define IOP13XX_INIT_I2C_2 (1 << 2)
/* ADMA selection flags */
/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
#define IOP13XX_INIT_ADMA_DEFAULT (0)
#define IOP13XX_INIT_ADMA_0 (1 << 0)
#define IOP13XX_INIT_ADMA_1 (1 << 1)
#define IOP13XX_INIT_ADMA_2 (1 << 2)
/* Platform devices */
#define IQ81340_NUM_UART 2
#define IQ81340_NUM_I2C 3
#define IQ81340_NUM_PHYS_MAP_FLASH 1
#define IQ81340_NUM_ADMA 3
#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
IQ81340_NUM_I2C + \
IQ81340_NUM_PHYS_MAP_FLASH + \
IQ81340_NUM_ADMA)
/*========================== PMMR offsets for key registers ============*/
#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
#define IOP13XX_MU_PMMR_OFFSET 0x00004000
#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
#define IOP13XX_CONTROLLER_ONLY (1 << 14)
#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
/*================================ATU===================================*/
#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atux_pmmr_offset + (ofs))
#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x2)
#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x4)
#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x6)
#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atue_pmmr_offset + (ofs))
#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x2)
#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x4)
#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x6)
#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0xe2)
#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
#define IOP13XX_ATUE_OCCAR_REG (2)
#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
#define IOP13XX_ATUE_STAT_PME (1 << 27)
#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
#define IOP13XX_ATUE_STAT_IVM (1 << 25)
#define IOP13XX_ATUE_STAT_BIST (1 << 24)
#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
/*=======================================================================*/
/*============================MESSAGING UNIT=============================*/
#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
(ofs))
#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
#define IOP13XX_MU_BASE_PHYS (0xff000000)
#define IOP13XX_MU_BASE_PCI (0xff000000)
#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
#define IOP13XX_MU_MIMR_CORE_SELECT (15)
/*=======================================================================*/
/*==============================ADMA UNITS===============================*/
#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
/*==============================XSI BRIDGE===============================*/
#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUE_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUX_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
/*=======================================================================*/
#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
(ofs))
#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
/* Watchdog timer definitions */
#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
#define IOP_WDTCR_EN 0xe1e1e1e1
#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
#define IOP_WDTCR_DIS 0xf1f1f1f1
#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
#define IOP13XX_WDTCR_IB_RESET (1 << 0)
#endif /* _IOP13XX_HW_H_ */

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arch/arm/mach-iop13xx/include/mach/iq81340.h
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@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IQ81340_H_
#define _IQ81340_H_
#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
#endif /* _IQ81340_H_ */

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arch/arm/mach-iop13xx/include/mach/irqs.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_IRQS_H_
#define _IOP13XX_IRQS_H_
#ifndef __ASSEMBLER__
#include <linux/types.h>
/* INTPND0 CP6 R0 Page 3
*/
static inline u32 read_intpnd_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
return val;
}
/* INTPND1 CP6 R1 Page 3
*/
static inline u32 read_intpnd_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
return val;
}
/* INTPND2 CP6 R2 Page 3
*/
static inline u32 read_intpnd_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
return val;
}
/* INTPND3 CP6 R3 Page 3
*/
static inline u32 read_intpnd_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
return val;
}
#endif
#define INTBASE 0
#define INTSIZE_4 1
/*
* iop34x chipset interrupts
*/
#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
/*
* On IRQ or FIQ register
*/
#define IRQ_IOP13XX_ADMA0_EOT (0)
#define IRQ_IOP13XX_ADMA0_EOC (1)
#define IRQ_IOP13XX_ADMA1_EOT (2)
#define IRQ_IOP13XX_ADMA1_EOC (3)
#define IRQ_IOP13XX_ADMA2_EOT (4)
#define IRQ_IOP13XX_ADMA2_EOC (5)
#define IRQ_IOP134_WATCHDOG (6)
#define IRQ_IOP13XX_RSVD_7 (7)
#define IRQ_IOP13XX_TIMER0 (8)
#define IRQ_IOP13XX_TIMER1 (9)
#define IRQ_IOP13XX_I2C_0 (10)
#define IRQ_IOP13XX_I2C_1 (11)
#define IRQ_IOP13XX_MSG (12)
#define IRQ_IOP13XX_MSGIBQ (13)
#define IRQ_IOP13XX_ATU_IM (14)
#define IRQ_IOP13XX_ATU_BIST (15)
#define IRQ_IOP13XX_PPMU (16)
#define IRQ_IOP13XX_COREPMU (17)
#define IRQ_IOP13XX_CORECACHE (18)
#define IRQ_IOP13XX_RSVD_19 (19)
#define IRQ_IOP13XX_RSVD_20 (20)
#define IRQ_IOP13XX_RSVD_21 (21)
#define IRQ_IOP13XX_RSVD_22 (22)
#define IRQ_IOP13XX_RSVD_23 (23)
#define IRQ_IOP13XX_XINT0 (24)
#define IRQ_IOP13XX_XINT1 (25)
#define IRQ_IOP13XX_XINT2 (26)
#define IRQ_IOP13XX_XINT3 (27)
#define IRQ_IOP13XX_XINT4 (28)
#define IRQ_IOP13XX_XINT5 (29)
#define IRQ_IOP13XX_XINT6 (30)
#define IRQ_IOP13XX_XINT7 (31)
/* IINTSRC1 bit */
#define IRQ_IOP13XX_XINT8 (32) /* 0 */
#define IRQ_IOP13XX_XINT9 (33) /* 1 */
#define IRQ_IOP13XX_XINT10 (34) /* 2 */
#define IRQ_IOP13XX_XINT11 (35) /* 3 */
#define IRQ_IOP13XX_XINT12 (36) /* 4 */
#define IRQ_IOP13XX_XINT13 (37) /* 5 */
#define IRQ_IOP13XX_XINT14 (38) /* 6 */
#define IRQ_IOP13XX_XINT15 (39) /* 7 */
#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
#define IRQ_IOP13XX_UART0 (51) /* 19 */
#define IRQ_IOP13XX_UART1 (52) /* 20 */
#define IRQ_IOP13XX_PBIE (53) /* 21 */
#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
/* IINTSRC2 bit */
#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
/* IINTSRC3 bit */
#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
#define IRQ_IOP13XX_IMU (100) /* 4 */
#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */
#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
#define IRQ_IOP13XX_HPI (127) /* 31 */
#ifdef CONFIG_PCI_MSI
#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1)
#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128)
#else
#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
#endif
#endif /* _IOP13XX_IRQ_H_ */

68
arch/arm/mach-iop13xx/include/mach/memory.h
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@ -1,68 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <mach/hardware.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_IOP13XX)
#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
static inline dma_addr_t __virt_to_lbus(void __iomem *x)
{
return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
}
static inline void __iomem *__lbus_to_virt(dma_addr_t x)
{
return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
}
#define __is_lbus_dma(a) \
((a) >= IOP13XX_PMMR_P_START && (a) < IOP13XX_PMMR_P_END)
#define __is_lbus_virt(a) \
((a) >= IOP13XX_PMMR_V_START && (a) < IOP13XX_PMMR_V_END)
/* Device is an lbus device if it is on the platform bus of the IOP13XX */
#define is_lbus_device(dev) \
(dev && strncmp(dev->bus->name, "platform", 8) == 0)
#define __arch_dma_to_virt(dev, addr) \
({ \
void * __virt; \
dma_addr_t __dma = addr; \
if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
__virt = __lbus_to_virt(__dma); \
else \
__virt = (void *)__phys_to_virt(__dma); \
__virt; \
})
#define __arch_virt_to_dma(dev, addr) \
({ \
void * __virt = addr; \
dma_addr_t __dma; \
if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
__dma = __virt_to_lbus(__virt); \
else \
__dma = __virt_to_phys((unsigned long)__virt); \
__dma; \
})
#define __arch_pfn_to_dma(dev, pfn) \
({ \
/* __is_lbus_virt() can never be true for RAM pages */ \
(dma_addr_t)__pfn_to_phys(pfn); \
})
#define __arch_dma_to_pfn(dev, addr) __phys_to_pfn(addr)
#endif /* CONFIG_ARCH_IOP13XX */
#endif /* !ASSEMBLY */
#endif

127
arch/arm/mach-iop13xx/include/mach/time.h
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@ -1,127 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_TIME_H_
#define _IOP13XX_TIME_H_
#include <mach/irqs.h>
#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
#define IOP_TMR_EN 0x02
#define IOP_TMR_RELOAD 0x04
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1 0x00
#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
#define IOP13XX_CORE_FREQ_MASK (7 << 16)
#define IOP13XX_CORE_FREQ_600 (0 << 16)
#define IOP13XX_CORE_FREQ_667 (1 << 16)
#define IOP13XX_CORE_FREQ_800 (2 << 16)
#define IOP13XX_CORE_FREQ_933 (3 << 16)
#define IOP13XX_CORE_FREQ_1000 (4 << 16)
#define IOP13XX_CORE_FREQ_1200 (5 << 16)
void iop_init_time(unsigned long tickrate);
static inline unsigned long iop13xx_core_freq(void)
{
unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
freq &= IOP13XX_CORE_FREQ_MASK;
switch (freq) {
case IOP13XX_CORE_FREQ_600:
return 600000000;
case IOP13XX_CORE_FREQ_667:
return 667000000;
case IOP13XX_CORE_FREQ_800:
return 800000000;
case IOP13XX_CORE_FREQ_933:
return 933000000;
case IOP13XX_CORE_FREQ_1000:
return 1000000000;
case IOP13XX_CORE_FREQ_1200:
return 1200000000;
default:
printk("%s: warning unknown frequency, defaulting to 800MHz\n",
__func__);
}
return 800000000;
}
static inline unsigned long iop13xx_xsi_bus_ratio(void)
{
unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
switch (ratio) {
case IOP13XX_XSI_FREQ_RATIO_2:
return 2;
case IOP13XX_XSI_FREQ_RATIO_3:
return 3;
case IOP13XX_XSI_FREQ_RATIO_4:
return 4;
default:
printk("%s: warning unknown ratio, defaulting to 2\n",
__func__);
}
return 2;
}
static inline u32 read_tmr0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
return val;
}
static inline void write_tmr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
}
static inline void write_tmr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
}
static inline u32 read_tcr0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
return val;
}
static inline void write_tcr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
}
static inline u32 read_tcr1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
return val;
}
static inline void write_tcr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
}
static inline void write_trr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
}
static inline void write_trr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
}
static inline void write_tisr(u32 val)
{
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
}
#endif

23
arch/arm/mach-iop13xx/include/mach/uncompress.h
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@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <asm/types.h>
#include <linux/serial_reg.h>
#include <mach/hardware.h>
#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
UART_BASE[UART_TX] = c;
}
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()

77
arch/arm/mach-iop13xx/io.c
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@ -1,77 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* iop13xx custom ioremap implementation
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "pci.h"
static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
size_t size, unsigned int mtype, void *caller)
{
void __iomem * retval;
switch (cookie) {
case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
if (unlikely(!iop13xx_atux_mem_base))
retval = NULL;
else
retval = (iop13xx_atux_mem_base +
(cookie - IOP13XX_PCIX_LOWER_MEM_RA));
break;
case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
if (unlikely(!iop13xx_atue_mem_base))
retval = NULL;
else
retval = (iop13xx_atue_mem_base +
(cookie - IOP13XX_PCIE_LOWER_MEM_RA));
break;
case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA +
(cookie - IOP13XX_PBI_LOWER_MEM_RA),
size, mtype, __builtin_return_address(0));
break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break;
default:
retval = __arm_ioremap_caller(cookie, size, mtype,
caller);
}
return retval;
}
static void __iop13xx_iounmap(volatile void __iomem *addr)
{
if (iop13xx_atue_mem_base)
if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
addr < (void __iomem *) (iop13xx_atue_mem_base +
iop13xx_atue_mem_size))
goto skip;
if (iop13xx_atux_mem_base)
if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
addr < (void __iomem *) (iop13xx_atux_mem_base +
iop13xx_atux_mem_size))
goto skip;
switch ((u32) addr) {
case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
goto skip;
}
__iounmap(addr);
skip:
return;
}
void __init iop13xx_init_early(void)
{
arch_ioremap_caller = __iop13xx_ioremap_caller;
arch_iounmap = __iop13xx_iounmap;
}

84
arch/arm/mach-iop13xx/iq81340mc.c
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@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* iq81340mc board support
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/pci.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "pci.h"
#include <asm/mach/time.h>
#include <mach/time.h>
extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
static int __init
iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
{
switch (idsel) {
case 1:
switch (pin) {
case 1: return ATUX_INTB;
case 2: return ATUX_INTC;
case 3: return ATUX_INTD;
case 4: return ATUX_INTA;
default: return -1;
}
case 2:
switch (pin) {
case 1: return ATUX_INTC;
case 2: return ATUX_INTD;
case 3: return ATUX_INTC;
case 4: return ATUX_INTD;
default: return -1;
}
default: return -1;
}
}
static struct hw_pci iq81340mc_pci __initdata = {
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.map_irq = iq81340mc_pcix_map_irq,
.scan = iop13xx_scan_bus,
.preinit = iop13xx_pci_init,
};
static int __init iq81340mc_pci_init(void)
{
iop13xx_atu_select(&iq81340mc_pci);
pci_common_init(&iq81340mc_pci);
iop13xx_map_pci_memory();
return 0;
}
static void __init iq81340mc_init(void)
{
iop13xx_platform_init();
iq81340mc_pci_init();
iop13xx_add_tpmi_devices();
}
static void __init iq81340mc_timer_init(void)
{
unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
iop_init_time(bus_freq);
}
MACHINE_START(IQ81340MC, "Intel IQ81340MC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.atag_offset = 0x100,
.init_early = iop13xx_init_early,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.init_time = iq81340mc_timer_init,
.init_machine = iq81340mc_init,
.restart = iop13xx_restart,
.nr_irqs = NR_IOP13XX_IRQS,
MACHINE_END

86
arch/arm/mach-iop13xx/iq81340sc.c
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@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* iq81340sc board support
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/pci.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "pci.h"
#include <asm/mach/time.h>
#include <mach/time.h>
extern int init_atu;
static int __init
iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel < 1 || idsel > 2);
switch (idsel) {
case 1:
switch (pin) {
case 1: return ATUX_INTB;
case 2: return ATUX_INTC;
case 3: return ATUX_INTD;
case 4: return ATUX_INTA;
default: return -1;
}
case 2:
switch (pin) {
case 1: return ATUX_INTC;
case 2: return ATUX_INTC;
case 3: return ATUX_INTC;
case 4: return ATUX_INTC;
default: return -1;
}
default: return -1;
}
}
static struct hw_pci iq81340sc_pci __initdata = {
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.scan = iop13xx_scan_bus,
.map_irq = iq81340sc_atux_map_irq,
.preinit = iop13xx_pci_init
};
static int __init iq81340sc_pci_init(void)
{
iop13xx_atu_select(&iq81340sc_pci);
pci_common_init(&iq81340sc_pci);
iop13xx_map_pci_memory();
return 0;
}
static void __init iq81340sc_init(void)
{
iop13xx_platform_init();
iq81340sc_pci_init();
iop13xx_add_tpmi_devices();
}
static void __init iq81340sc_timer_init(void)
{
unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
iop_init_time(bus_freq);
}
MACHINE_START(IQ81340SC, "Intel IQ81340SC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.atag_offset = 0x100,
.init_early = iop13xx_init_early,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.init_time = iq81340sc_timer_init,
.init_machine = iq81340sc_init,
.restart = iop13xx_restart,
.nr_irqs = NR_IOP13XX_IRQS,
MACHINE_END

227
arch/arm/mach-iop13xx/irq.c
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@ -1,227 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* iop13xx IRQ handling / support functions
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/sysctl.h>
#include <linux/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include "msi.h"
/* INTCTL0 CP6 R0 Page 4
*/
static u32 read_intctl_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
return val;
}
static void write_intctl_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
}
/* INTCTL1 CP6 R1 Page 4
*/
static u32 read_intctl_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
return val;
}
static void write_intctl_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
}
/* INTCTL2 CP6 R2 Page 4
*/
static u32 read_intctl_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
return val;
}
static void write_intctl_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
}
/* INTCTL3 CP6 R3 Page 4
*/
static u32 read_intctl_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
return val;
}
static void write_intctl_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
}
/* INTSTR0 CP6 R0 Page 5
*/
static void write_intstr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
}
/* INTSTR1 CP6 R1 Page 5
*/
static void write_intstr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
}
/* INTSTR2 CP6 R2 Page 5
*/
static void write_intstr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
}
/* INTSTR3 CP6 R3 Page 5
*/
static void write_intstr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
}
/* INTBASE CP6 R0 Page 2
*/
static void write_intbase(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
}
/* INTSIZE CP6 R2 Page 2
*/
static void write_intsize(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
}
/* 0 = Interrupt Masked and 1 = Interrupt not masked */
static void
iop13xx_irq_mask0 (struct irq_data *d)
{
write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0)));
}
static void
iop13xx_irq_mask1 (struct irq_data *d)
{
write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32)));
}
static void
iop13xx_irq_mask2 (struct irq_data *d)
{
write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64)));
}
static void
iop13xx_irq_mask3 (struct irq_data *d)
{
write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96)));
}
static void
iop13xx_irq_unmask0(struct irq_data *d)
{
write_intctl_0(read_intctl_0() | (1 << (d->irq - 0)));
}
static void
iop13xx_irq_unmask1(struct irq_data *d)
{
write_intctl_1(read_intctl_1() | (1 << (d->irq - 32)));
}
static void
iop13xx_irq_unmask2(struct irq_data *d)
{
write_intctl_2(read_intctl_2() | (1 << (d->irq - 64)));
}
static void
iop13xx_irq_unmask3(struct irq_data *d)
{
write_intctl_3(read_intctl_3() | (1 << (d->irq - 96)));
}
static struct irq_chip iop13xx_irqchip1 = {
.name = "IOP13xx-1",
.irq_ack = iop13xx_irq_mask0,
.irq_mask = iop13xx_irq_mask0,
.irq_unmask = iop13xx_irq_unmask0,
};
static struct irq_chip iop13xx_irqchip2 = {
.name = "IOP13xx-2",
.irq_ack = iop13xx_irq_mask1,
.irq_mask = iop13xx_irq_mask1,
.irq_unmask = iop13xx_irq_unmask1,
};
static struct irq_chip iop13xx_irqchip3 = {
.name = "IOP13xx-3",
.irq_ack = iop13xx_irq_mask2,
.irq_mask = iop13xx_irq_mask2,
.irq_unmask = iop13xx_irq_unmask2,
};
static struct irq_chip iop13xx_irqchip4 = {
.name = "IOP13xx-4",
.irq_ack = iop13xx_irq_mask3,
.irq_mask = iop13xx_irq_mask3,
.irq_unmask = iop13xx_irq_unmask3,
};
extern void iop_init_cp6_handler(void);
void __init iop13xx_init_irq(void)
{
unsigned int i;
iop_init_cp6_handler();
/* disable all interrupts */
write_intctl_0(0);
write_intctl_1(0);
write_intctl_2(0);
write_intctl_3(0);
/* treat all as IRQ */
write_intstr_0(0);
write_intstr_1(0);
write_intstr_2(0);
write_intstr_3(0);
/* initialize the interrupt vector generator */
write_intbase(INTBASE);
write_intsize(INTSIZE_4);
for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
if (i < 32)
irq_set_chip(i, &iop13xx_irqchip1);
else if (i < 64)
irq_set_chip(i, &iop13xx_irqchip2);
else if (i < 96)
irq_set_chip(i, &iop13xx_irqchip3);
else
irq_set_chip(i, &iop13xx_irqchip4);
irq_set_handler(i, handle_level_irq);
irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
}
iop13xx_msi_init();
}

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arch/arm/mach-iop13xx/msi.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-iop13xx/msi.c
*
* PCI MSI support for the iop13xx processor
*
* Copyright (c) 2006, Intel Corporation.
*/
#include <linux/pci.h>
#include <linux/msi.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/irqs.h>
/* IMIPR0 CP6 R8 Page 1
*/
static u32 read_imipr_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
return val;
}
static void write_imipr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
}
/* IMIPR1 CP6 R9 Page 1
*/
static u32 read_imipr_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
return val;
}
static void write_imipr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
}
/* IMIPR2 CP6 R10 Page 1
*/
static u32 read_imipr_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
return val;
}
static void write_imipr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
}
/* IMIPR3 CP6 R11 Page 1
*/
static u32 read_imipr_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
return val;
}
static void write_imipr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
}
static u32 (*read_imipr[])(void) = {
read_imipr_0,
read_imipr_1,
read_imipr_2,
read_imipr_3,
};
static void (*write_imipr[])(u32) = {
write_imipr_0,
write_imipr_1,
write_imipr_2,
write_imipr_3,
};
static void iop13xx_msi_handler(struct irq_desc *desc)
{
int i, j;
unsigned long status;
/* read IMIPR registers and find any active interrupts,
* then call ISR for each active interrupt
*/
for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
status = (read_imipr[i])();
if (!status)
continue;
do {
j = find_first_bit(&status, 32);
(write_imipr[i])(1 << j); /* write back to clear bit */
generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
status = (read_imipr[i])();
} while (status);
}
}
void __init iop13xx_msi_init(void)
{
irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
}
static void iop13xx_msi_nop(struct irq_data *d)
{
return;
}
static struct irq_chip iop13xx_msi_chip = {
.name = "PCI-MSI",
.irq_ack = iop13xx_msi_nop,
.irq_enable = pci_msi_unmask_irq,
.irq_disable = pci_msi_mask_irq,
.irq_mask = pci_msi_mask_irq,
.irq_unmask = pci_msi_unmask_irq,
};
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
struct msi_msg msg;
if (irq < 0)
return irq;
if (irq >= NR_IOP13XX_IRQS) {
irq_free_desc(irq);
return -ENOSPC;
}
irq_set_msi_desc(irq, desc);
msg.address_hi = 0x0;
msg.address_lo = IOP13XX_MU_MIMR_PCI;
id = iop13xx_cpu_id();
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
pci_write_msi_msg(irq, &msg);
irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
return 0;
}
void arch_teardown_msi_irq(unsigned int irq)
{
irq_free_desc(irq);
}

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arch/arm/mach-iop13xx/msi.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_MSI_H_
#define _IOP13XX_MSI_H_
#ifdef CONFIG_PCI_MSI
void iop13xx_msi_init(void);
#else
static inline void iop13xx_msi_init(void)
{
return;
}
#endif
#endif

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arch/arm/mach-iop13xx/pci.c
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arch/arm/mach-iop13xx/pci.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_PCI_H_
#define _IOP13XX_PCI_H_
#include <linux/io.h>
#include <mach/irqs.h>
#include <linux/types.h>
extern void __iomem *iop13xx_atue_mem_base;
extern void __iomem *iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
struct pci_sys_data;
struct pci_host_bridge;
struct hw_pci;
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge);
void iop13xx_atu_select(struct hw_pci *plat_pci);
void iop13xx_pci_init(void);
void iop13xx_map_pci_memory(void);
#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
PCI_STATUS_SIG_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_DETECTED_PARITY)
#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
IOP13XX_ATUE_STAT_ERR_COR | \
IOP13XX_ATUE_STAT_ERR_UNCOR | \
IOP13XX_ATUE_STAT_CRS | \
IOP13XX_ATUE_STAT_DET_PAR_ERR | \
IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
IOP13XX_ATUE_STAT_SIG_TABORT | \
IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
IOP13XX_ATUX_STAT_REC_SCEM | \
IOP13XX_ATUX_STAT_TX_SERR | \
IOP13XX_ATUX_STAT_DET_PAR_ERR | \
IOP13XX_ATUX_STAT_INT_REC_MABORT | \
IOP13XX_ATUX_STAT_REC_SERR | \
IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
/* PCI interrupts
*/
#define ATUX_INTA IRQ_IOP13XX_XINT0
#define ATUX_INTB IRQ_IOP13XX_XINT1
#define ATUX_INTC IRQ_IOP13XX_XINT2
#define ATUX_INTD IRQ_IOP13XX_XINT3
#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
#endif /* _IOP13XX_PCI_H_ */

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arch/arm/mach-iop13xx/setup.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* iop13xx platform Initialization
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
#include <linux/reboot.h>
#ifdef CONFIG_MTD_PHYSMAP
#include <linux/mtd/physmap.h>
#endif
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/hardware/iop_adma.h>
#include <mach/irqs.h>
#define IOP13XX_UART_XTAL 33334000
#define IOP13XX_SETUP_DEBUG 0
#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
/* Standard IO mapping for all IOP13XX based systems
*/
static struct map_desc iop13xx_std_desc[] __initdata = {
{ /* mem mapped registers */
.virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE,
},
};
static struct resource iop13xx_uart0_resources[] = {
[0] = {
.start = IOP13XX_UART0_PHYS,
.end = IOP13XX_UART0_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_UART0,
.end = IRQ_IOP13XX_UART0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_uart1_resources[] = {
[0] = {
.start = IOP13XX_UART1_PHYS,
.end = IOP13XX_UART1_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_UART1,
.end = IRQ_IOP13XX_UART1,
.flags = IORESOURCE_IRQ
}
};
static struct plat_serial8250_port iop13xx_uart0_data[] = {
{
.membase = IOP13XX_UART0_VIRT,
.mapbase = IOP13XX_UART0_PHYS,
.irq = IRQ_IOP13XX_UART0,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct plat_serial8250_port iop13xx_uart1_data[] = {
{
.membase = IOP13XX_UART1_VIRT,
.mapbase = IOP13XX_UART1_PHYS,
.irq = IRQ_IOP13XX_UART1,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_uart0 = {
.name = "serial8250",
.id = 0,
.dev.platform_data = iop13xx_uart0_data,
.num_resources = 2,
.resource = iop13xx_uart0_resources,
};
static struct platform_device iop13xx_uart1 = {
.name = "serial8250",
.id = 0,
.dev.platform_data = iop13xx_uart1_data,
.num_resources = 2,
.resource = iop13xx_uart1_resources
};
static struct resource iop13xx_i2c_0_resources[] = {
[0] = {
.start = IOP13XX_I2C0_PHYS,
.end = IOP13XX_I2C0_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_0,
.end = IRQ_IOP13XX_I2C_0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_i2c_1_resources[] = {
[0] = {
.start = IOP13XX_I2C1_PHYS,
.end = IOP13XX_I2C1_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_1,
.end = IRQ_IOP13XX_I2C_1,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_i2c_2_resources[] = {
[0] = {
.start = IOP13XX_I2C2_PHYS,
.end = IOP13XX_I2C2_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_2,
.end = IRQ_IOP13XX_I2C_2,
.flags = IORESOURCE_IRQ
}
};
/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
* we just use the same device name.
*/
/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_i2c_0_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_0_resources
};
static struct platform_device iop13xx_i2c_1_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_1_resources
};
static struct platform_device iop13xx_i2c_2_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_2_resources
};
#ifdef CONFIG_MTD_PHYSMAP
/* PBI Flash Device
*/
static struct physmap_flash_data iq8134x_flash_data = {
.width = 2,
};
static struct resource iq8134x_flash_resource = {
.start = IQ81340_FLASHBASE,
.end = 0,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq8134x_flash = {
.name = "physmap-flash",
.id = 0,
.dev = { .platform_data = &iq8134x_flash_data, },
.num_resources = 1,
.resource = &iq8134x_flash_resource,
};
static unsigned long iq8134x_probe_flash_size(void)
{
uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
int i;
char query[3];
unsigned long size = 0;
int width = iq8134x_flash_data.width;
if (flash_addr) {
/* send CFI 'query' command */
writew(0x98, flash_addr);
/* check for CFI compliance */
for (i = 0; i < 3 * width; i += width)
query[i / width] = readb(flash_addr + (0x10 * width) + i);
/* read the size */
if (memcmp(query, "QRY", 3) == 0)
size = 1 << readb(flash_addr + (0x27 * width));
/* send CFI 'read array' command */
writew(0xff, flash_addr);
iounmap(flash_addr);
}
return size;
}
#endif
/* ADMA Channels */
static struct resource iop13xx_adma_0_resources[] = {
[0] = {
.start = IOP13XX_ADMA_PHYS_BASE(0),
.end = IOP13XX_ADMA_UPPER_PA(0),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_ADMA0_EOT,
.end = IRQ_IOP13XX_ADMA0_EOT,
.flags = IORESOURCE_IRQ
},
[2] = {
.start = IRQ_IOP13XX_ADMA0_EOC,
.end = IRQ_IOP13XX_ADMA0_EOC,
.flags = IORESOURCE_IRQ
},
[3] = {
.start = IRQ_IOP13XX_ADMA0_ERR,
.end = IRQ_IOP13XX_ADMA0_ERR,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_adma_1_resources[] = {
[0] = {
.start = IOP13XX_ADMA_PHYS_BASE(1),
.end = IOP13XX_ADMA_UPPER_PA(1),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_ADMA1_EOT,
.end = IRQ_IOP13XX_ADMA1_EOT,
.flags = IORESOURCE_IRQ
},
[2] = {
.start = IRQ_IOP13XX_ADMA1_EOC,
.end = IRQ_IOP13XX_ADMA1_EOC,
.flags = IORESOURCE_IRQ
},
[3] = {
.start = IRQ_IOP13XX_ADMA1_ERR,
.end = IRQ_IOP13XX_ADMA1_ERR,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_adma_2_resources[] = {
[0] = {
.start = IOP13XX_ADMA_PHYS_BASE(2),
.end = IOP13XX_ADMA_UPPER_PA(2),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_ADMA2_EOT,
.end = IRQ_IOP13XX_ADMA2_EOT,
.flags = IORESOURCE_IRQ
},
[2] = {
.start = IRQ_IOP13XX_ADMA2_EOC,
.end = IRQ_IOP13XX_ADMA2_EOC,
.flags = IORESOURCE_IRQ
},
[3] = {
.start = IRQ_IOP13XX_ADMA2_ERR,
.end = IRQ_IOP13XX_ADMA2_ERR,
.flags = IORESOURCE_IRQ
}
};
static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32);
static struct iop_adma_platform_data iop13xx_adma_0_data = {
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct iop_adma_platform_data iop13xx_adma_1_data = {
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct iop_adma_platform_data iop13xx_adma_2_data = {
.hw_id = 2,
.pool_size = PAGE_SIZE,
};
/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_adma_0_channel = {
.name = "iop-adma",
.id = 0,
.num_resources = 4,
.resource = iop13xx_adma_0_resources,
.dev = {
.dma_mask = &iop13xx_adma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = (void *) &iop13xx_adma_0_data,
},
};
static struct platform_device iop13xx_adma_1_channel = {
.name = "iop-adma",
.id = 0,
.num_resources = 4,
.resource = iop13xx_adma_1_resources,
.dev = {
.dma_mask = &iop13xx_adma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = (void *) &iop13xx_adma_1_data,
},
};
static struct platform_device iop13xx_adma_2_channel = {
.name = "iop-adma",
.id = 0,
.num_resources = 4,
.resource = iop13xx_adma_2_resources,
.dev = {
.dma_mask = &iop13xx_adma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = (void *) &iop13xx_adma_2_data,
},
};
void __init iop13xx_map_io(void)
{
/* Initialize the Static Page Table maps */
iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
}
static int init_uart;
static int init_i2c;
static int init_adma;
void __init iop13xx_platform_init(void)
{
int i;
u32 uart_idx, i2c_idx, adma_idx, plat_idx;
struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
/* set the bases so we can read the device id */
iop13xx_set_atu_mmr_bases();
memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
switch (iop13xx_dev_id()) {
/* enable both uarts on iop341 */
case 0x3380:
case 0x3384:
case 0x3388:
case 0x338c:
init_uart |= IOP13XX_INIT_UART_0;
init_uart |= IOP13XX_INIT_UART_1;
break;
/* only enable uart 1 */
default:
init_uart |= IOP13XX_INIT_UART_1;
}
}
if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
switch (iop13xx_dev_id()) {
/* enable all i2c units on iop341 and iop342 */
case 0x3380:
case 0x3384:
case 0x3388:
case 0x338c:
case 0x3382:
case 0x3386:
case 0x338a:
case 0x338e:
init_i2c |= IOP13XX_INIT_I2C_0;
init_i2c |= IOP13XX_INIT_I2C_1;
init_i2c |= IOP13XX_INIT_I2C_2;
break;
/* only enable i2c 1 and 2 */
default:
init_i2c |= IOP13XX_INIT_I2C_1;
init_i2c |= IOP13XX_INIT_I2C_2;
}
}
if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
init_adma |= IOP13XX_INIT_ADMA_0;
init_adma |= IOP13XX_INIT_ADMA_1;
init_adma |= IOP13XX_INIT_ADMA_2;
}
plat_idx = 0;
uart_idx = 0;
i2c_idx = 0;
/* uart 1 (if enabled) is ttyS0 */
if (init_uart & IOP13XX_INIT_UART_1) {
PRINTK("Adding uart1 to platform device list\n");
iop13xx_uart1.id = uart_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_uart1;
}
if (init_uart & IOP13XX_INIT_UART_0) {
PRINTK("Adding uart0 to platform device list\n");
iop13xx_uart0.id = uart_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_uart0;
}
for(i = 0; i < IQ81340_NUM_I2C; i++) {
if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
printk("Adding i2c%d to platform device list\n", i);
switch(init_i2c & (1 << i)) {
case IOP13XX_INIT_I2C_0:
iop13xx_i2c_0_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_0_controller;
break;
case IOP13XX_INIT_I2C_1:
iop13xx_i2c_1_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_1_controller;
break;
case IOP13XX_INIT_I2C_2:
iop13xx_i2c_2_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_2_controller;
break;
}
}
/* initialize adma channel ids and capabilities */
adma_idx = 0;
for (i = 0; i < IQ81340_NUM_ADMA; i++) {
struct iop_adma_platform_data *plat_data;
if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
printk(KERN_INFO
"Adding adma%d to platform device list\n", i);
switch (init_adma & (1 << i)) {
case IOP13XX_INIT_ADMA_0:
iop13xx_adma_0_channel.id = adma_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
plat_data = &iop13xx_adma_0_data;
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
dma_cap_set(DMA_XOR, plat_data->cap_mask);
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
break;
case IOP13XX_INIT_ADMA_1:
iop13xx_adma_1_channel.id = adma_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
plat_data = &iop13xx_adma_1_data;
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
dma_cap_set(DMA_XOR, plat_data->cap_mask);
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
break;
case IOP13XX_INIT_ADMA_2:
iop13xx_adma_2_channel.id = adma_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
plat_data = &iop13xx_adma_2_data;
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
dma_cap_set(DMA_XOR, plat_data->cap_mask);
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
dma_cap_set(DMA_PQ, plat_data->cap_mask);
dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
break;
}
}
#ifdef CONFIG_MTD_PHYSMAP
iq8134x_flash_resource.end = iq8134x_flash_resource.start +
iq8134x_probe_flash_size() - 1;
if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
iop13xx_devices[plat_idx++] = &iq8134x_flash;
else
printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
#endif
platform_add_devices(iop13xx_devices, plat_idx);
}
static int __init iop13xx_init_uart_setup(char *str)
{
if (str) {
while (*str != '\0') {
switch(*str) {
case '0':
init_uart |= IOP13XX_INIT_UART_0;
break;
case '1':
init_uart |= IOP13XX_INIT_UART_1;
break;
case ',':
case '=':
break;
default:
PRINTK("\"iop13xx_init_uart\" malformed"
" at character: \'%c\'", *str);
*(str + 1) = '\0';
init_uart = IOP13XX_INIT_UART_DEFAULT;
}
str++;
}
}
return 1;
}
static int __init iop13xx_init_i2c_setup(char *str)
{
if (str) {
while (*str != '\0') {
switch(*str) {
case '0':
init_i2c |= IOP13XX_INIT_I2C_0;
break;
case '1':
init_i2c |= IOP13XX_INIT_I2C_1;
break;
case '2':
init_i2c |= IOP13XX_INIT_I2C_2;
break;
case ',':
case '=':
break;
default:
PRINTK("\"iop13xx_init_i2c\" malformed"
" at character: \'%c\'", *str);
*(str + 1) = '\0';
init_i2c = IOP13XX_INIT_I2C_DEFAULT;
}
str++;
}
}
return 1;
}
static int __init iop13xx_init_adma_setup(char *str)
{
if (str) {
while (*str != '\0') {
switch (*str) {
case '0':
init_adma |= IOP13XX_INIT_ADMA_0;
break;
case '1':
init_adma |= IOP13XX_INIT_ADMA_1;
break;
case '2':
init_adma |= IOP13XX_INIT_ADMA_2;
break;
case ',':
case '=':
break;
default:
PRINTK("\"iop13xx_init_adma\" malformed"
" at character: \'%c\'", *str);
*(str + 1) = '\0';
init_adma = IOP13XX_INIT_ADMA_DEFAULT;
}
str++;
}
}
return 1;
}
__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
void iop13xx_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Reset the internal bus (warning both cores are reset)
*/
write_wdtcr(IOP_WDTCR_EN_ARM);
write_wdtcr(IOP_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
}

244
arch/arm/mach-iop13xx/tpmi.c
View File

@ -1,244 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* iop13xx tpmi device resources
* Copyright (c) 2005-2006, Intel Corporation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <linux/sizes.h>
#include <mach/irqs.h>
/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
#define IOP13XX_TPMI_MEM_SIZE (255)
#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
#define IOP13XX_TPMI_RESOURCE_MMR 0
#define IOP13XX_TPMI_RESOURCE_MEM 1
#define IOP13XX_TPMI_RESOURCE_CTRL 2
#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
#define IOP13XX_TPMI_RESOURCE_IRQ 4
static struct resource iop13xx_tpmi_0_resources[] = {
[IOP13XX_TPMI_RESOURCE_MMR] = {
.start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
.end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_MEM] = {
.start = IOP13XX_TPMI_MEM(0),
.end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_CTRL] = {
.start = IOP13XX_TPMI_CTRL(0),
.end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
.start = IOP13XX_TPMI_IOP_CTRL(0),
.end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IRQ] = {
.start = IRQ_IOP13XX_TPMI0_OUT,
.end = IRQ_IOP13XX_TPMI0_OUT,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_tpmi_1_resources[] = {
[IOP13XX_TPMI_RESOURCE_MMR] = {
.start = IOP13XX_TPMI_MMR(1),
.end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_MEM] = {
.start = IOP13XX_TPMI_MEM(1),
.end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_CTRL] = {
.start = IOP13XX_TPMI_CTRL(1),
.end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
.start = IOP13XX_TPMI_IOP_CTRL(1),
.end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IRQ] = {
.start = IRQ_IOP13XX_TPMI1_OUT,
.end = IRQ_IOP13XX_TPMI1_OUT,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_tpmi_2_resources[] = {
[IOP13XX_TPMI_RESOURCE_MMR] = {
.start = IOP13XX_TPMI_MMR(2),
.end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_MEM] = {
.start = IOP13XX_TPMI_MEM(2),
.end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_CTRL] = {
.start = IOP13XX_TPMI_CTRL(2),
.end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
.start = IOP13XX_TPMI_IOP_CTRL(2),
.end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IRQ] = {
.start = IRQ_IOP13XX_TPMI2_OUT,
.end = IRQ_IOP13XX_TPMI2_OUT,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_tpmi_3_resources[] = {
[IOP13XX_TPMI_RESOURCE_MMR] = {
.start = IOP13XX_TPMI_MMR(3),
.end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_MEM] = {
.start = IOP13XX_TPMI_MEM(3),
.end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_CTRL] = {
.start = IOP13XX_TPMI_CTRL(3),
.end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
.start = IOP13XX_TPMI_IOP_CTRL(3),
.end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
.flags = IORESOURCE_MEM,
},
[IOP13XX_TPMI_RESOURCE_IRQ] = {
.start = IRQ_IOP13XX_TPMI3_OUT,
.end = IRQ_IOP13XX_TPMI3_OUT,
.flags = IORESOURCE_IRQ
}
};
u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32);
static struct platform_device iop13xx_tpmi_0_device = {
.name = "iop-tpmi",
.id = 0,
.num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
.resource = iop13xx_tpmi_0_resources,
.dev = {
.dma_mask = &iop13xx_tpmi_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device iop13xx_tpmi_1_device = {
.name = "iop-tpmi",
.id = 1,
.num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
.resource = iop13xx_tpmi_1_resources,
.dev = {
.dma_mask = &iop13xx_tpmi_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device iop13xx_tpmi_2_device = {
.name = "iop-tpmi",
.id = 2,
.num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
.resource = iop13xx_tpmi_2_resources,
.dev = {
.dma_mask = &iop13xx_tpmi_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device iop13xx_tpmi_3_device = {
.name = "iop-tpmi",
.id = 3,
.num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
.resource = iop13xx_tpmi_3_resources,
.dev = {
.dma_mask = &iop13xx_tpmi_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
__init void iop13xx_add_tpmi_devices(void)
{
unsigned short device_id;
/* tpmi's not present on iop341 or iop342 */
if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
/* ATUE must be present */
device_id = __raw_readw(IOP13XX_ATUE_DID);
else
/* ATUX must be present */
device_id = __raw_readw(IOP13XX_ATUX_DID);
switch (device_id) {
/* iop34[1|2] 0-tpmi */
case 0x3380:
case 0x3384:
case 0x3388:
case 0x338c:
case 0x3382:
case 0x3386:
case 0x338a:
case 0x338e:
return;
/* iop348 1-tpmi */
case 0x3310:
case 0x3312:
case 0x3314:
case 0x3318:
case 0x331a:
case 0x331c:
case 0x33c0:
case 0x33c2:
case 0x33c4:
case 0x33c8:
case 0x33ca:
case 0x33cc:
case 0x33b0:
case 0x33b2:
case 0x33b4:
case 0x33b8:
case 0x33ba:
case 0x33bc:
case 0x3320:
case 0x3322:
case 0x3324:
case 0x3328:
case 0x332a:
case 0x332c:
platform_device_register(&iop13xx_tpmi_0_device);
return;
default:
platform_device_register(&iop13xx_tpmi_0_device);
platform_device_register(&iop13xx_tpmi_1_device);
platform_device_register(&iop13xx_tpmi_2_device);
platform_device_register(&iop13xx_tpmi_3_device);
return;
}
}

10
arch/arm/mach-iop32x/Makefile
View File

@ -3,7 +3,15 @@
# Makefile for the linux kernel.
#
obj-y := irq.o
obj-$(CONFIG_ARCH_IOP32X) += irq.o
obj-$(CONFIG_ARCH_IOP32X) += i2c.o
obj-$(CONFIG_ARCH_IOP32X) += pci.o
obj-$(CONFIG_ARCH_IOP32X) += setup.o
obj-$(CONFIG_ARCH_IOP32X) += time.o
obj-$(CONFIG_ARCH_IOP32X) += cp6.o
obj-$(CONFIG_ARCH_IOP32X) += adma.o
obj-$(CONFIG_ARCH_IOP32X) += pmu.o
obj-$(CONFIG_ARCH_IOP32X) += restart.o
obj-$(CONFIG_MACH_GLANTANK) += glantank.o
obj-$(CONFIG_ARCH_IQ80321) += iq80321.o

37
arch/arm/plat-iop/adma.c → arch/arm/mach-iop32x/adma.c
View File

@ -4,12 +4,12 @@
* Copyright © 2006, Intel Corporation.
*/
#include <linux/platform_device.h>
#include <asm/hardware/iop3xx.h>
#include <linux/dma-mapping.h>
#include <mach/adma.h>
#include <asm/hardware/iop_adma.h>
#include <linux/platform_data/dma-iop32x.h>
#include "iop3xx.h"
#include "irqs.h"
#ifdef CONFIG_ARCH_IOP32X
#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
@ -21,20 +21,7 @@
#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
#endif
#ifdef CONFIG_ARCH_IOP33X
#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
#endif
/* AAU and DMA Channels */
static struct resource iop3xx_dma_0_resources[] = {
[0] = {
@ -161,30 +148,14 @@ struct platform_device iop3xx_aau_channel = {
static int __init iop3xx_adma_cap_init(void)
{
#ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
#else
dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
#endif
#ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
#else
dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
#endif
#ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
#else
dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
#endif
return 0;
}

0
arch/arm/plat-iop/cp6.c → arch/arm/mach-iop32x/cp6.c
View File

5
arch/arm/mach-iop32x/em7210.c
View File

@ -21,7 +21,6 @@
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/mach/arch.h>
@ -29,8 +28,10 @@
#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <mach/time.h>
#include "hardware.h"
#include "gpio-iop32x.h"
#include "irqs.h"
static void __init em7210_timer_init(void)
{

5
arch/arm/mach-iop32x/glantank.c
View File

@ -22,7 +22,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -30,8 +29,10 @@
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <mach/time.h>
#include "hardware.h"
#include "gpio-iop32x.h"
#include "irqs.h"
/*
* GLAN Tank timer tick configuration.

2
arch/arm/mach-iop32x/include/mach/glantank.h → arch/arm/mach-iop32x/glantank.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/glantank.h
*
* IO-Data GLAN Tank board registers
*/

6
arch/arm/mach-iop32x/include/mach/hardware.h → arch/arm/mach-iop32x/hardware.h
View File

@ -1,8 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/hardware.h
*/
#ifndef __HARDWARE_H
#define __HARDWARE_H
@ -28,7 +24,7 @@ void iop32x_init_irq(void);
/*
* Generic chipset bits
*/
#include "iop32x.h"
#include "iop3xx.h"
/*
* Board specific bits

21
arch/arm/plat-iop/i2c.c → arch/arm/mach-iop32x/i2c.c
View File

@ -22,18 +22,11 @@
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/hardware/iop3xx.h>
#include <asm/mach/arch.h>
#ifdef CONFIG_ARCH_IOP32X
#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0
#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1
#endif
#ifdef CONFIG_ARCH_IOP33X
#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0
#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1
#endif
#include "hardware.h"
#include "iop3xx.h"
#include "irqs.h"
/*
* Each of the I2C busses have corresponding GPIO lines, and the driver
@ -65,8 +58,8 @@ static struct resource iop3xx_i2c0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP3XX_I2C_0,
.end = IRQ_IOP3XX_I2C_0,
.start = IRQ_IOP32X_I2C_0,
.end = IRQ_IOP32X_I2C_0,
.flags = IORESOURCE_IRQ,
},
};
@ -86,8 +79,8 @@ static struct resource iop3xx_i2c1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP3XX_I2C_1,
.end = IRQ_IOP3XX_I2C_1,
.start = IRQ_IOP32X_I2C_1,
.end = IRQ_IOP32X_I2C_1,
.flags = IORESOURCE_IRQ,
}
};

6
arch/arm/mach-iop32x/include/mach/adma.h
View File

@ -1,6 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef IOP32X_ADMA_H
#define IOP32X_ADMA_H
#include <asm/hardware/iop3xx-adma.h>
#endif

2
arch/arm/mach-iop32x/include/mach/entry-macro.S
View File

@ -7,8 +7,6 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/iop32x.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)

31
arch/arm/mach-iop32x/include/mach/iop32x.h
View File

@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-iop32x/include/mach/iop32x.h
*
* Intel IOP32X Chip definitions
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
* Copyright (C) 2004 Intel Corp.
*/
#ifndef __IOP32X_H
#define __IOP32X_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
#include <asm/hardware/iop3xx.h>
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ physical ram on top of pci in the memory map
*/
#define IOP32X_MAX_RAM_SIZE 0x40000000UL
#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
#endif

33
arch/arm/mach-iop32x/include/mach/irqs.h
View File

@ -9,39 +9,6 @@
#ifndef __IRQS_H
#define __IRQS_H
/*
* IOP80321 chipset interrupts
*/
#define IRQ_IOP32X_DMA0_EOT 0
#define IRQ_IOP32X_DMA0_EOC 1
#define IRQ_IOP32X_DMA1_EOT 2
#define IRQ_IOP32X_DMA1_EOC 3
#define IRQ_IOP32X_AA_EOT 6
#define IRQ_IOP32X_AA_EOC 7
#define IRQ_IOP32X_CORE_PMON 8
#define IRQ_IOP32X_TIMER0 9
#define IRQ_IOP32X_TIMER1 10
#define IRQ_IOP32X_I2C_0 11
#define IRQ_IOP32X_I2C_1 12
#define IRQ_IOP32X_MESSAGING 13
#define IRQ_IOP32X_ATU_BIST 14
#define IRQ_IOP32X_PERFMON 15
#define IRQ_IOP32X_CORE_PMU 16
#define IRQ_IOP32X_BIU_ERR 17
#define IRQ_IOP32X_ATU_ERR 18
#define IRQ_IOP32X_MCU_ERR 19
#define IRQ_IOP32X_DMA0_ERR 20
#define IRQ_IOP32X_DMA1_ERR 21
#define IRQ_IOP32X_AA_ERR 23
#define IRQ_IOP32X_MSG_ERR 24
#define IRQ_IOP32X_SSP 25
#define IRQ_IOP32X_XINT0 27
#define IRQ_IOP32X_XINT1 28
#define IRQ_IOP32X_XINT2 29
#define IRQ_IOP32X_XINT3 30
#define IRQ_IOP32X_HPI 31
#define NR_IRQS 32
#endif

5
arch/arm/mach-iop32x/include/mach/time.h
View File

@ -1,5 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP32X_TIME_H_
#define _IOP32X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
#endif

18
arch/arm/mach-iop32x/include/mach/uncompress.h
View File

@ -6,9 +6,8 @@
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#include <mach/hardware.h>
volatile u8 *uart_base;
#define uart_base ((volatile u8 *)0xfe800000)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@ -23,17 +22,4 @@ static inline void flush(void)
{
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
if (machine_is_iq80321())
uart_base = (volatile u8 *)IQ80321_UART;
else if (machine_is_iq31244() || machine_is_em7210())
uart_base = (volatile u8 *)IQ31244_UART;
else
uart_base = (volatile u8 *)0xfe800000;
}
/*
* nothing to do
*/
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#define arch_decomp_setup() do { } while (0)

18
arch/arm/include/asm/hardware/iop3xx.h → arch/arm/mach-iop32x/iop3xx.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/include/asm/hardware/iop3xx.h
*
* Intel IOP32X and IOP33X register definitions
*
* Author: Rory Bolt <rorybolt@pacbell.net>
@ -12,6 +10,22 @@
#ifndef __IOP3XX_H
#define __IOP3XX_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
#include "iop3xx.h"
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ physical ram on top of pci in the memory map
*/
#define IOP32X_MAX_RAM_SIZE 0x40000000UL
#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
/*
* IOP3XX GPIO handling
*/

5
arch/arm/mach-iop32x/iq31244.c
View File

@ -23,7 +23,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/cputype.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@ -33,7 +32,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/iq31244.h → arch/arm/mach-iop32x/iq31244.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/iq31244.h
*
* Intel IQ31244 evaluation board registers
*/

5
arch/arm/mach-iop32x/iq80321.c
View File

@ -20,7 +20,6 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -29,7 +28,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/iq80321.h → arch/arm/mach-iop32x/iq80321.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/iq80321.h
*
* Intel IQ80321 evaluation board registers
*/

3
arch/arm/mach-iop32x/irq.c
View File

@ -13,9 +13,10 @@
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include "hardware.h"
static u32 iop32x_mask;
static void intctl_write(u32 val)

42
arch/arm/mach-iop32x/irqs.h 100644
View File

@ -0,0 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright: (C) 2002 Rory Bolt
*/
#ifndef __IOP32X_IRQS_H
#define __IOP32X_IRQS_H
/*
* IOP80321 chipset interrupts
*/
#define IRQ_IOP32X_DMA0_EOT 0
#define IRQ_IOP32X_DMA0_EOC 1
#define IRQ_IOP32X_DMA1_EOT 2
#define IRQ_IOP32X_DMA1_EOC 3
#define IRQ_IOP32X_AA_EOT 6
#define IRQ_IOP32X_AA_EOC 7
#define IRQ_IOP32X_CORE_PMON 8
#define IRQ_IOP32X_TIMER0 9
#define IRQ_IOP32X_TIMER1 10
#define IRQ_IOP32X_I2C_0 11
#define IRQ_IOP32X_I2C_1 12
#define IRQ_IOP32X_MESSAGING 13
#define IRQ_IOP32X_ATU_BIST 14
#define IRQ_IOP32X_PERFMON 15
#define IRQ_IOP32X_CORE_PMU 16
#define IRQ_IOP32X_BIU_ERR 17
#define IRQ_IOP32X_ATU_ERR 18
#define IRQ_IOP32X_MCU_ERR 19
#define IRQ_IOP32X_DMA0_ERR 20
#define IRQ_IOP32X_DMA1_ERR 21
#define IRQ_IOP32X_AA_ERR 23
#define IRQ_IOP32X_MSG_ERR 24
#define IRQ_IOP32X_SSP 25
#define IRQ_IOP32X_XINT0 27
#define IRQ_IOP32X_XINT1 28
#define IRQ_IOP32X_XINT2 29
#define IRQ_IOP32X_XINT3 30
#define IRQ_IOP32X_HPI 31
#endif

5
arch/arm/mach-iop32x/n2100.c
View File

@ -28,7 +28,6 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -37,7 +36,9 @@
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <mach/time.h>
#include "hardware.h"
#include "irqs.h"
#include "gpio-iop32x.h"
/*

2
arch/arm/mach-iop32x/include/mach/n2100.h → arch/arm/mach-iop32x/n2100.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/n2100.h
*
* Thecus N2100 board registers
*/

4
arch/arm/plat-iop/pci.c → arch/arm/mach-iop32x/pci.c
View File

@ -17,9 +17,9 @@
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/signal.h>
#include <mach/hardware.h>
#include <asm/mach/pci.h>
#include <asm/hardware/iop3xx.h>
#include "hardware.h"
#include "iop3xx.h"
// #define DEBUG

8
arch/arm/plat-iop/pmu.c → arch/arm/mach-iop32x/pmu.c
View File

@ -5,17 +5,11 @@
*/
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include "irqs.h"
static struct resource pmu_resource = {
#ifdef CONFIG_ARCH_IOP32X
.start = IRQ_IOP32X_CORE_PMU,
.end = IRQ_IOP32X_CORE_PMU,
#endif
#ifdef CONFIG_ARCH_IOP33X
.start = IRQ_IOP33X_CORE_PMU,
.end = IRQ_IOP33X_CORE_PMU,
#endif
.flags = IORESOURCE_IRQ,
};

4
arch/arm/plat-iop/restart.c → arch/arm/mach-iop32x/restart.c
View File

@ -4,9 +4,9 @@
*
* Copyright (C) 2001 MontaVista Software, Inc.
*/
#include <asm/hardware/iop3xx.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "hardware.h"
#include "iop3xx.h"
void iop3xx_restart(enum reboot_mode mode, const char *cmd)
{

2
arch/arm/plat-iop/setup.c → arch/arm/mach-iop32x/setup.c
View File

@ -10,7 +10,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <asm/hardware/iop3xx.h>
#include "iop3xx.h"
/*
* Standard IO mapping for all IOP3xx based systems. Note that

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