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clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support

Add support for the R-Car M3-W+ (R8A77961) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.

R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.  R-Car M3-W+ lacks a few modules, so their
clocks must be nullified.

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023122941.12342-5-geert+renesas@glider.be
alistair/sunxi64-5.5-dsi
Geert Uytterhoeven 2019-10-23 14:29:41 +02:00
parent 92d1ebae9a
commit 2ba738d56d
4 changed files with 32 additions and 4 deletions

View File

@ -22,6 +22,7 @@ config CLK_RENESAS
select CLK_R8A7794 if ARCH_R8A7794
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
select CLK_R8A77961 if ARCH_R8A77961
select CLK_R8A77965 if ARCH_R8A77965
select CLK_R8A77970 if ARCH_R8A77970
select CLK_R8A77980 if ARCH_R8A77980
@ -113,6 +114,10 @@ config CLK_R8A77960
bool "R-Car M3-W clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
config CLK_R8A77961
bool "R-Car M3-W+ clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
config CLK_R8A77965
bool "R-Car M3-N clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG

View File

@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o

View File

@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
* r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
* Reset
*
* Copyright (C) 2016 Glider bvba
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2016-2019 Glider bvba
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@ -14,6 +15,7 @@
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
@ -116,7 +118,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
@ -304,6 +306,14 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
{ 2, 192, 1, 192, 1, 32, },
};
/*
* Fixups for R-Car M3-W+
*/
static const unsigned int r8a77961_mod_nullify[] __initconst = {
MOD_CLK_ID(617), /* FCPCI0 */
};
static int __init r8a7796_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
@ -320,6 +330,12 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev)
return -EINVAL;
}
if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr"))
mssr_mod_nullify(r8a7796_mod_clks,
ARRAY_SIZE(r8a7796_mod_clks),
r8a77961_mod_nullify,
ARRAY_SIZE(r8a77961_mod_nullify));
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}

View File

@ -755,6 +755,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7796_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A77961
{
.compatible = "renesas,r8a77961-cpg-mssr",
.data = &r8a7796_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A77965
{
.compatible = "renesas,r8a77965-cpg-mssr",