[POWERPC] ppc32: fix CPCI405 board support
Hi,
this patch brings the CPCI405 board support up to date and fixes several
outstanding issues:
-add bios_fixup()
-enable RTC only when CONFIG_GEN_RTC defined
-corrected CompactPCI interrupt map
-added cpci405_early_serial_map for correct UART clocking
-removed unused code
Matthias
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Matthias Fuchs
Paul Mackerras
parent
4312dc76a8
commit
2ba73b1d6f
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@ -183,7 +183,7 @@ config IBM_EMAC4
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config BIOS_FIXUP
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bool
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depends on BUBINGA || EP405 || SYCAMORE || WALNUT
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depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
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default y
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# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
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@ -1,10 +1,12 @@
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/*
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* Board setup routines for the esd CPCI-405 cPCI Board.
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*
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* Author: Stefan Roese
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* stefan.roese@esd-electronics.com
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* Copyright 2001-2006 esd electronic system design - hannover germany
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*
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* Copyright 2001 esd electronic system design - hannover germany
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* Authors: Matthias Fuchs
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* matthias.fuchs@esd-electronics.com
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* Stefan Roese
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* stefan.roese@esd-electronics.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -20,9 +22,17 @@
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/todc.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <asm/ocp.h>
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#include <asm/ibm_ocp_pci.h>
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#include <platforms/4xx/ibm405gp.h>
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#ifdef CONFIG_GEN_RTC
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void *cpci405_nvram;
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#endif
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extern bd_t __res;
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/*
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* Some IRQs unique to CPCI-405.
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@ -36,18 +46,69 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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* A B C D
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*/
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{
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{28, 28, 28, 28}, /* IDSEL 15 - cPCI slot 8 */
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{29, 29, 29, 29}, /* IDSEL 16 - cPCI slot 7 */
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{30, 30, 30, 30}, /* IDSEL 17 - cPCI slot 6 */
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{27, 27, 27, 27}, /* IDSEL 18 - cPCI slot 5 */
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{28, 28, 28, 28}, /* IDSEL 19 - cPCI slot 4 */
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{29, 29, 29, 29}, /* IDSEL 20 - cPCI slot 3 */
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{30, 30, 30, 30}, /* IDSEL 21 - cPCI slot 2 */
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{28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
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{29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
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{30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
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{27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
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{28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
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{29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
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{30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
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};
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const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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/* The serial clock for the chip is an internal clock determined by
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* different clock speeds/dividers.
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* Calculate the proper input baud rate and setup the serial driver.
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*/
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static void __init
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cpci405_early_serial_map(void)
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{
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u32 uart_div;
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int uart_clock;
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struct uart_port port;
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/* Calculate the serial clock input frequency
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*
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* The uart clock is the cpu frequency (provided in the board info
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* structure) divided by the external UART Divisor.
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*/
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uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
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uart_clock = __res.bi_procfreq / uart_div;
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/* Setup serial port access */
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memset(&port, 0, sizeof(port));
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#if defined(CONFIG_UART0_TTYS0)
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port.membase = (void*)UART0_IO_BASE;
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port.irq = UART0_INT;
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#else
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port.membase = (void*)UART1_IO_BASE;
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port.irq = UART1_INT;
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#endif
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port.uartclk = uart_clock;
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port.regshift = 0;
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port.iotype = UPIO_MEM;
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port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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#if defined(CONFIG_UART0_TTYS0)
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port.membase = (void*)UART1_IO_BASE;
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port.irq = UART1_INT;
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#else
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port.membase = (void*)UART0_IO_BASE;
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port.irq = UART0_INT;
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#endif
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port.line = 1;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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}
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void __init
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cpci405_setup_arch(void)
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{
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@ -55,14 +116,68 @@ cpci405_setup_arch(void)
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ibm_ocp_set_emac(0, 0);
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TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
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cpci405_early_serial_map();
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#ifdef CONFIG_GEN_RTC
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TODC_INIT(TODC_TYPE_MK48T35,
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cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
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#endif
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}
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void __init
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bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
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{
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unsigned int bar_response, bar;
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/* Disable region first */
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out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
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/* PLB starting addr, PCI: 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
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/* PCI start addr, 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
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/* 512MB range of PLB to PCI */
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out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
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/* Enable no pre-fetch, enable region */
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out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
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(PPC405_PCI_UPPER_MEM -
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PPC405_PCI_MEM_BASE)) | 0x01));
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/* Disable region one */
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm1ms), 0x00000001);
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/* Disable region two */
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm2ms), 0x00000000);
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out_le32((void *) &(pcip->ptm2la), 0x00000000);
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/* Zero config bars */
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
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early_write_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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0x00000000);
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early_read_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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&bar_response);
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}
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}
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void __init
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cpci405_map_io(void)
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{
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ppc4xx_map_io();
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#ifdef CONFIG_GEN_RTC
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cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
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#endif
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}
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void __init
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@ -74,9 +189,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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ppc_md.setup_arch = cpci405_setup_arch;
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ppc_md.setup_io_mappings = cpci405_map_io;
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#ifdef CONFIG_GEN_RTC
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#endif
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}
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@ -1,37 +1,29 @@
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/*
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* CPCI-405 board specific definitions
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*
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* Copyright (c) 2001 Stefan Roese (stefan.roese@esd-electronics.com)
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* Copyright 2001-2006 esd electronic system design - hannover germany
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*
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* Authors: Matthias Fuchs
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* matthias.fuchs@esd-electronics.com
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* Stefan Roese
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* stefan.roese@esd-electronics.com
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_CPCI405_H__
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#define __ASM_CPCI405_H__
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#ifndef __CPCI405_H__
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#define __CPCI405_H__
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#include <linux/config.h>
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/* We have a 405GP core */
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#include <platforms/4xx/ibm405gp.h>
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#include <asm/ppcboot.h>
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#ifndef __ASSEMBLY__
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/* Some 4xx parts use a different timebase frequency from the internal clock.
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*/
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#define bi_tbfreq bi_intfreq
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/* Map for the NVRAM space */
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#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
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#define CPCI405_NVRAM_SIZE ((uint)32*1024)
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#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
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#define BASE_BAUD 201600
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#else
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#define BASE_BAUD 691200
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#endif
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#define BASE_BAUD 0
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#define PPC4xx_MACHINE_NAME "esd CPCI-405"
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#define PPC4xx_MACHINE_NAME "esd CPCI-405"
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_CPCI405_H__ */
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#endif /* __CPCI405_H__ */
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#endif /* __KERNEL__ */
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