Merge branch 'samsung-fixes' into samsung-next-base
This commit is contained in:
commit
2bb00c68e0
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@ -159,6 +159,8 @@ clock which they consume.
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mixer 343
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mixer 343
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hdmi 344
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hdmi 344
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g2d 345
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g2d 345
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mdma0 346
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smmu_mdma0 347
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[Clock Muxes]
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[Clock Muxes]
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@ -559,7 +559,7 @@
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compatible = "arm,pl330", "arm,primecell";
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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reg = <0x10800000 0x1000>;
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interrupts = <0 33 0>;
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interrupts = <0 33 0>;
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clocks = <&clock 271>;
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clocks = <&clock 346>;
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clock-names = "apb_pclk";
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-channels = <8>;
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@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data;
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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#define ASS_CLK_GATE 0x8
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/* list of all parent clock list */
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static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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#ifdef CONFIG_PM_SLEEP
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static unsigned long reg_save[][2] = {
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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{ASS_CLK_SRC, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_GATE, 0},
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{ASS_CLK_GATE, 0},
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};
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};
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/* list of all parent clock list */
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static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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#ifdef CONFIG_PM_SLEEP
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static int exynos_audss_clk_suspend(void)
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static int exynos_audss_clk_suspend(void)
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{
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{
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int i;
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int i;
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@ -39,7 +39,7 @@
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#define SRC_TOP1 0xc214
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#define SRC_TOP1 0xc214
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#define SRC_CAM 0xc220
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#define SRC_CAM 0xc220
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#define SRC_TV 0xc224
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#define SRC_TV 0xc224
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#define SRC_MFC 0xcc28
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#define SRC_MFC 0xc228
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#define SRC_G3D 0xc22c
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#define SRC_G3D 0xc22c
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#define E4210_SRC_IMAGE 0xc230
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#define E4210_SRC_IMAGE 0xc230
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#define SRC_LCD0 0xc234
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#define SRC_LCD0 0xc234
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@ -25,6 +25,7 @@
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#define MPLL_LOCK 0x4000
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#define MPLL_LOCK 0x4000
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#define MPLL_CON0 0x4100
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#define MPLL_CON0 0x4100
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#define SRC_CORE1 0x4204
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#define SRC_CORE1 0x4204
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#define GATE_IP_ACP 0x8800
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#define CPLL_LOCK 0x10020
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#define CPLL_LOCK 0x10020
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#define EPLL_LOCK 0x10030
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#define EPLL_LOCK 0x10030
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#define VPLL_LOCK 0x10040
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#define VPLL_LOCK 0x10040
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@ -75,7 +76,6 @@
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#define SRC_CDREX 0x20200
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#define SRC_CDREX 0x20200
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#define PLL_DIV2_SEL 0x20a24
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#define PLL_DIV2_SEL 0x20a24
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#define GATE_IP_DISP1 0x10928
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#define GATE_IP_DISP1 0x10928
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#define GATE_IP_ACP 0x10000
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/* list of PLLs to be registered */
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/* list of PLLs to be registered */
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enum exynos5250_plls {
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enum exynos5250_plls {
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@ -120,7 +120,8 @@ enum exynos5250_clks {
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spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
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spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
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hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
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hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
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tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
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tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
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wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
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wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
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smmu_mdma0,
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/* mux clocks */
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/* mux clocks */
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mout_hdmi = 1024,
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mout_hdmi = 1024,
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@ -354,8 +355,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
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GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
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GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
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GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
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GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
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GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
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GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
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GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
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GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
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GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
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GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0),
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GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
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GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
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GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
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GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
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GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
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GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
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@ -406,7 +407,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
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GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
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GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
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GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
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GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
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GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
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GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
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GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
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GATE(sysreg, "sysreg", "aclk66",
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GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
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GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
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GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
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GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
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GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
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GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
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GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
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@ -492,6 +494,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
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GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
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GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
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GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
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GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
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GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
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GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
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GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
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GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
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};
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};
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static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
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static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
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