MIPS: Move cop2 save/restore to switch_to()
Move the common code for saving and restoring platform specific COP2 registers to switch_to(). This will make supporting new platforms (like Netlogic XLP) easier. The platform specific COP2 definitions are to be specified in asm/processor.h and in asm/cop2.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5411/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Jayachandran C
Ralf Baechle
parent
79f8511c83
commit
2c952e06e4
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@ -11,6 +11,25 @@
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#include <linux/notifier.h>
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#if defined(CONFIG_CPU_CAVIUM_OCTEON)
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extern void octeon_cop2_save(struct octeon_cop2_state *);
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extern void octeon_cop2_restore(struct octeon_cop2_state *);
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#define cop2_save(r) octeon_cop2_save(r)
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#define cop2_restore(r) octeon_cop2_restore(r)
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#define cop2_present 1
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#define cop2_lazy_restore 1
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#else
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#define cop2_present 0
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#define cop2_lazy_restore 0
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#define cop2_save(r)
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#define cop2_restore(r)
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#endif
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enum cu2_ops {
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CU2_EXCEPTION,
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CU2_LWC2_OP,
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@ -137,7 +137,7 @@ union mips_watch_reg_state {
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struct mips3264_watch_reg_state mips3264;
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};
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#if defined(CONFIG_CPU_CAVIUM_OCTEON)
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struct octeon_cop2_state {
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/* DMFC2 rt, 0x0201 */
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@ -182,13 +182,16 @@ struct octeon_cop2_state {
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/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
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unsigned long cop2_gfm_result[2];
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};
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#define INIT_OCTEON_COP2 {0,}
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#define COP2_INIT \
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.cp2 = {0,},
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struct octeon_cvmseg_state {
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unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
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[cpu_dcache_line_size() / sizeof(unsigned long)];
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};
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#else
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#define COP2_INIT
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#endif
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typedef struct {
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@ -245,13 +248,6 @@ struct thread_struct {
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#define FPAFF_INIT
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#endif /* CONFIG_MIPS_MT_FPAFF */
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define OCTEON_INIT \
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.cp2 = INIT_OCTEON_COP2,
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#else
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#define OCTEON_INIT
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#define INIT_THREAD { \
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/* \
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* Saved main processor registers \
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@ -300,9 +296,9 @@ struct thread_struct {
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.cp0_baduaddr = 0, \
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.error_code = 0, \
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/* \
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* Cavium Octeon specifics (null if not Octeon) \
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* Platform specific cop2 registers(null if no COP2) \
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*/ \
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OCTEON_INIT \
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COP2_INIT \
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}
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struct task_struct;
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@ -15,6 +15,7 @@
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#include <asm/cpu-features.h>
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#include <asm/watch.h>
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#include <asm/dsp.h>
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#include <asm/cop2.h>
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struct task_struct;
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@ -66,10 +67,18 @@ do { \
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#define switch_to(prev, next, last) \
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do { \
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u32 __usedfpu; \
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u32 __usedfpu, __c0_stat; \
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__mips_mt_fpaff_switch_to(prev); \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \
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if (cop2_lazy_restore) \
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KSTK_STATUS(prev) &= ~ST0_CU2; \
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__c0_stat = read_c0_status(); \
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write_c0_status(__c0_stat | ST0_CU2); \
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cop2_save(&prev->thread.cp2); \
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write_c0_status(__c0_stat & ~ST0_CU2); \
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} \
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__clear_software_ll_bit(); \
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__usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \
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(last) = resume(prev, next, task_thread_info(next), __usedfpu); \
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@ -77,6 +86,14 @@ do { \
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#define finish_arch_switch(prev) \
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do { \
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u32 __c0_stat; \
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if (cop2_present && !cop2_lazy_restore && \
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(KSTK_STATUS(current) & ST0_CU2)) { \
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__c0_stat = read_c0_status(); \
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write_c0_status(__c0_stat | ST0_CU2); \
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cop2_restore(¤t->thread.cp2); \
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write_c0_status(__c0_stat & ~ST0_CU2); \
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} \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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if (cpu_has_userlocal) \
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@ -40,33 +40,6 @@
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cpu_save_nonscratch a0
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LONG_S ra, THREAD_REG31(a0)
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/* check if we need to save COP2 registers */
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PTR_L t2, TASK_THREAD_INFO(a0)
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LONG_L t0, ST_OFF(t2)
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bbit0 t0, 30, 1f
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/* Disable COP2 in the stored process state */
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li t1, ST0_CU2
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xor t0, t1
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LONG_S t0, ST_OFF(t2)
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/* Enable COP2 so we can save it */
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mfc0 t0, CP0_STATUS
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or t0, t1
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mtc0 t0, CP0_STATUS
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/* Save COP2 */
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daddu a0, THREAD_CP2
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jal octeon_cop2_save
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dsubu a0, THREAD_CP2
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/* Disable COP2 now that we are done */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU2
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xor t0, t1
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mtc0 t0, CP0_STATUS
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1:
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#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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/* Check if we need to store CVMSEG state */
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mfc0 t0, $11,7 /* CvmMemCtl */
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