Devicetree updates for v5.5:
- DT schemas for PWM, syscon, power domains, SRAM, syscon-reboot, syscon-poweroff, renesas-irqc, simple-pm-bus, renesas-bsc, pwm-rcar, Renesas tpu, at24 eeprom, rtc-sh, Allwinner PS/2, sharp,ld-d5116z01b panel, Arm SMMU, max77650, Meson CEC, Amlogic canvas and DWC3 glue, Allwinner A10 mUSB and CAN, TI Davinci MDIO, QCom QCS404 interconnect, Unisoc/Spreadtrum SoCs and UART - Convert a bunch of Samsung bindings to DT schema - Convert a bunch of ST stm32 bindings to DT schema - Realtek and Exynos additions to Arm Mali bindings - Fix schema errors in RiscV CPU schema - Various schema fixes from improved meta-schema checks - Improve the handling of 'dma-ranges' and in particular fix DMA mask setup on PCI bridges - Fix a memory leak in add_changeset_property() and DT unit tests. - Several documentation improvements for schema validation - Rework build rules to improve schema validation errors - Color output for dtx_diff -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl3djLcQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw0mbEACocS2QpgxblYJfcHbMGmNajD0/jAWa6wwY eWNsx/Y+F1Xuz8uOsB5U9ZF5zQPTsqaN65osMljopjsib2TjUyCDZxAizzrMaFMK GyzS08lIh+pLYmwCmXP3YB1BaKI0j4UN+qY129jJPLfN2PrBBB0JQT9jxFQJNiB/ XHCWT/n5sh3d/JiqGs1kHgFIwSX1jz69pU94ZTn6Nw7xgTrNl1lOXVBMaHvNGU/C hLXSRY+T/L0tyf33i3pm922cXxLgtAaDnAqxuPaD26hNRWw4RhvRtXJLJ2HTsCj2 Pclc0sg6PZamyCP2vCQ5zm7nhGwbqDTSTVt3+n26DQ0Xi2SJvfbjehR3us5E0Uxe /CRgbwbLQxOFq/S/xeb3pqArOzsg2Uacb+lLLmKD+XCY0htObD/isLfMUxzXpB6A MMQkJfkcbeH5MSps2LBo6ip1JGhateJEpcaT93MK9mgH9Lzh+b/CUdq0BnvAnIKc t/LL57YTI7wnhEXFr6urD8xIbo0rNDlu4keaSnDaAQdh59wAvKCxAfw+rbhXA4je ZOi4qA70aWSOb31LXTK2S31e50LTQiQeJ/CwZ5t7RSxzTk1hFwC4YJ05aO7+qW9V xL6r5httEqVyTHkcbc8eaUBPTjL6iysKPUyJ7EwC2t/dTSDsQukHXq/JPQqK+0u/ SRSY5mq0vw== =L6uq -----END PGP SIGNATURE----- Merge tag 'devicetree-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree updates from Rob Herring: - DT schemas for PWM, syscon, power domains, SRAM, syscon-reboot, syscon-poweroff, renesas-irqc, simple-pm-bus, renesas-bsc, pwm-rcar, Renesas tpu, at24 eeprom, rtc-sh, Allwinner PS/2, sharp,ld-d5116z01b panel, Arm SMMU, max77650, Meson CEC, Amlogic canvas and DWC3 glue, Allwinner A10 mUSB and CAN, TI Davinci MDIO, QCom QCS404 interconnect, Unisoc/Spreadtrum SoCs and UART - Convert a bunch of Samsung bindings to DT schema - Convert a bunch of ST stm32 bindings to DT schema - Realtek and Exynos additions to Arm Mali bindings - Fix schema errors in RiscV CPU schema - Various schema fixes from improved meta-schema checks - Improve the handling of 'dma-ranges' and in particular fix DMA mask setup on PCI bridges - Fix a memory leak in add_changeset_property() and DT unit tests. - Several documentation improvements for schema validation - Rework build rules to improve schema validation errors - Color output for dtx_diff * tag 'devicetree-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (138 commits) libfdt: define INT32_MAX and UINT32_MAX in libfdt_env.h dt-bindings: arm: Remove leftover axentia.txt of: unittest: fix memory leak in attach_node_and_children of: overlay: add_changeset_property() memory leak dt-bindings: interrupt-controller: arm,gic-v3: Add missing type to interrupt-partition-* nodes dt-bindings: firmware: ixp4xx: Drop redundant minItems/maxItems dt-bindings: power: Rename back power_domain.txt bindings to fix references dt-bindings: i2c: stm32: Migrate i2c-stm32 documentation to yaml dt-bindings: mtd: Convert stm32 fmc2-nand bindings to json-schema dt-bindings: remoteproc: convert stm32-rproc to json-schema dt-bindings: mailbox: convert stm32-ipcc to json-schema dt-bindings: mfd: Convert stm32 low power timers bindings to json-schema dt-bindings: interrupt-controller: Convert stm32-exti to json-schema dt-bindings: crypto: Convert stm32 HASH bindings to json-schema dt-bindings: rng: Convert stm32 RNG bindings to json-schema dt-bindings: pwm: Convert Samsung PWM bindings to json-schema dt-bindings: pwm: Convert PWM bindings to json-schema dt-bindings: serial: Add a new compatible string for SC9863A dt-bindings: serial: Convert sprd-uart to json-schema dt-bindings: arm: Add bindings for Unisoc SC9863A ...alistair/sunxi64-5.5-dsi
Linus Torvalds
commit
2c97b5ae83
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@ -12,7 +12,6 @@ $(obj)/%.example.dts: $(src)/%.yaml FORCE
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$(call if_changed,chk_binding)
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DT_TMP_SCHEMA := processed-schema.yaml
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extra-y += $(DT_TMP_SCHEMA)
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quiet_cmd_mk_schema = SCHEMA $@
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs)
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@ -26,8 +25,12 @@ DT_DOCS = $(shell \
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DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))
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ifeq ($(CHECK_DTBS),)
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extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-y += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
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endif
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$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE
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$(call if_changed,mk_schema)
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extra-y += $(DT_TMP_SCHEMA)
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@ -1,32 +0,0 @@
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Amlogic Meson8 and Meson8b SRAM for smp bringup:
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------------------------------------------------
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Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
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Once the core gets powered up it executes the code that is residing at a
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specific location.
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Therefore a reserved section sub-node has to be added to the mmio-sram
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declaration.
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Required sub-node properties:
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- compatible : depending on the SoC this should be one of:
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"amlogic,meson8-smp-sram"
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"amlogic,meson8b-smp-sram"
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The rest of the properties should follow the generic mmio-sram discription
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found in ../../misc/sram.txt
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Example:
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sram: sram@d9000000 {
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compatible = "mmio-sram";
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reg = <0xd9000000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xd9000000 0x20000>;
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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@ -100,7 +100,7 @@ Required sub-node properties:
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/thermal/thermal.txt
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[4] Documentation/devicetree/bindings/sram/sram.txt
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[5] Documentation/devicetree/bindings/reset/reset.txt
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@ -110,7 +110,7 @@ Required properties:
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] Documentation/devicetree/bindings/sram/sram.txt
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[4] Documentation/devicetree/bindings/power/power_domain.txt
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[4] Documentation/devicetree/bindings/power/power-domain.yaml
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Example:
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@ -1,28 +0,0 @@
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Device tree bindings for Axentia ARM devices
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============================================
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Linea CPU module
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----------------
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Required root node properties:
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compatible = "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from atmel-at91.txt for a sama5d31 SoC.
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Nattis v2 board with Natte v2 power board
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-----------------------------------------
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Required root node properties:
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compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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TSE-850 v3 board
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----------------
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Required root node properties:
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compatible = "axentia,tse850v3", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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@ -124,7 +124,7 @@ Required properties for Pinctrl sub nodes:
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CONFIG settings.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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RTC bindings based on SCU Message Protocol
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@ -1,12 +0,0 @@
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SAMSUNG Exynos SoCs Chipid driver.
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Required properties:
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- compatible : Should at least contain "samsung,exynos4210-chipid".
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- reg: offset and length of the register set
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Example:
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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@ -0,0 +1,39 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC series Chipid driver
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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properties:
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compatible:
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items:
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- const: samsung,exynos4210-chipid
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reg:
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maxItems: 1
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samsung,asv-bin:
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description:
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Adaptive Supply Voltage bin selection. This can be used
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to determine the ASV bin of an SoC if respective information
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is missing in the CHIPID registers or in the OTP memory.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 0, 1, 2, 3 ]
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required:
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- compatible
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- reg
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examples:
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- |
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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samsung,asv-bin = <2>;
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};
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@ -1,72 +0,0 @@
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SAMSUNG Exynos SoC series PMU Registers
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Properties:
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- compatible : should contain two values. First value must be one from following list:
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- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
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- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
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- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
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- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
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- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
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- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
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- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
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- "samsung,exynos5433-pmu" - for Exynos5433 SoC.
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- "samsung,exynos7-pmu" - for Exynos7 SoC.
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second value must be always "syscon".
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- reg : offset and length of the register set.
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- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
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The single specifier cell is used as index to list of clocks
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provided by PMU, which is currently:
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0 : SoC clock output (CLKOUT pin)
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- clock-names : list of clock names for particular CLKOUT mux inputs in
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following format:
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"clkoutN", where N is a decimal number corresponding to
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CLKOUT mux control bits value for given input, e.g.
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"clkout0", "clkout7", "clkout15".
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- clocks : list of phandles and specifiers to all input clocks listed in
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clock-names property.
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Optional properties:
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Some PMUs are capable of behaving as an interrupt controller (mostly
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to wake up a suspended PMU). In which case, they can have the
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following properties:
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- interrupt-controller: indicate that said PMU is an interrupt controller
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- #interrupt-cells: must be identical to the that of the parent interrupt
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controller.
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Optional nodes:
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- nodes defining the restart and poweroff syscon children
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Example :
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pmu_system_controller: system-controller@10040000 {
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compatible = "samsung,exynos5250-pmu", "syscon";
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reg = <0x10040000 0x5000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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#clock-cells = <1>;
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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};
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Example of clock consumer :
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usb3503: usb3503@8 {
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/* ... */
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clock-names = "refclk";
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clocks = <&pmu_system_controller 0>;
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/* ... */
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};
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@ -0,0 +1,105 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC series Power Management Unit (PMU)
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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# Custom select to avoid matching all nodes with 'syscon'
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select:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos3250-pmu
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- samsung,exynos4210-pmu
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- samsung,exynos4412-pmu
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- samsung,exynos5250-pmu
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- samsung,exynos5260-pmu
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- samsung,exynos5410-pmu
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- samsung,exynos5420-pmu
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- samsung,exynos5433-pmu
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- samsung,exynos7-pmu
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- samsung,exynos3250-pmu
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- samsung,exynos4210-pmu
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- samsung,exynos4412-pmu
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- samsung,exynos5250-pmu
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- samsung,exynos5260-pmu
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- samsung,exynos5410-pmu
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- samsung,exynos5420-pmu
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- samsung,exynos5433-pmu
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- samsung,exynos7-pmu
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clock-names:
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description:
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List of clock names for particular CLKOUT mux inputs
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minItems: 1
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maxItems: 32
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items:
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pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
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clocks:
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minItems: 1
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maxItems: 32
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interrupt-controller:
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description:
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Some PMUs are capable of behaving as an interrupt controller (mostly
|
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to wake up a suspended PMU).
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'#interrupt-cells':
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description:
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Must be identical to the that of the parent interrupt controller.
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const: 3
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syscon-poweroff:
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$ref: "../../power/reset/syscon-poweroff.yaml#"
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type: object
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description:
|
||||
Node for power off method
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||||
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syscon-reboot:
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$ref: "../../power/reset/syscon-reboot.yaml#"
|
||||
type: object
|
||||
description:
|
||||
Node for reboot method
|
||||
|
||||
required:
|
||||
- compatible
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||||
- reg
|
||||
- '#clock-cells'
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
|
||||
pmu_system_controller: system-controller@10040000 {
|
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compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout16";
|
||||
clocks = <&clock CLK_FIN_PLL>;
|
||||
};
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
* Samsung's Exynos and S5P SoC based boards
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,aries" - for S5PV210-based Samsung Aries board.
|
||||
- "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
|
||||
- "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
|
||||
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
|
||||
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
|
||||
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
|
||||
- "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
|
||||
- "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
|
||||
- "samsung,midas" - for Exynos4412-based Samsung Midas board.
|
||||
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
|
||||
- "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
|
||||
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
|
||||
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
|
||||
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
|
||||
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
|
||||
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
|
||||
- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
|
||||
- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
|
||||
|
||||
* Other companies Exynos SoC based
|
||||
* FriendlyARM
|
||||
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
|
||||
TINY4412 board.
|
||||
* TOPEET
|
||||
- "topeet,itop4412-elite" - for Exynos4412-based TOPEET
|
||||
Elite base board.
|
||||
|
||||
* Google
|
||||
- "google,pi" - for Exynos5800-based Google Peach Pi
|
||||
Rev 10+ board,
|
||||
also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
|
||||
"google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
|
||||
"google,pi-rev10", "google,peach".
|
||||
|
||||
- "google,pit" - for Exynos5420-based Google Peach Pit
|
||||
Rev 6+ (Exynos5420),
|
||||
also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
|
||||
"google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
|
||||
"google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
|
||||
"google,pit-rev7", "google,pit-rev6", "google,peach".
|
||||
|
||||
- "google,snow-rev4" - for Exynos5250-based Google Snow board,
|
||||
also: "google,snow"
|
||||
- "google,snow-rev5" - for Exynos5250-based Google Snow
|
||||
Rev 5+ board.
|
||||
- "google,spring" - for Exynos5250-based Google Spring board.
|
||||
|
||||
* Hardkernel
|
||||
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
|
||||
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
|
||||
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
|
||||
- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
|
||||
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
|
||||
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
|
||||
Odroid XU3 Lite board.
|
||||
- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
|
||||
- "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1.
|
||||
|
||||
* Insignal
|
||||
- "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
|
||||
- "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
|
||||
Octa board.
|
||||
- "insignal,origen" - for Exynos4210-based Insignal Origen board.
|
||||
- "insignal,origen4412" - for Exynos4412-based Insignal Origen board.
|
||||
|
||||
|
||||
Optional nodes:
|
||||
- firmware node, specifying presence and type of secure firmware:
|
||||
- compatible: only "samsung,secure-firmware" is currently supported
|
||||
- reg: address of non-secure SYSRAM used for communication with firmware
|
||||
|
||||
firmware@203f000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203F000 0x1000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos and S5P SoC based boards
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: S5PV210 based boards
|
||||
items:
|
||||
- enum:
|
||||
- aesop,torbreck # aESOP Torbreck based on S5PV210
|
||||
- samsung,aquila # Samsung Aquila based on S5PC110
|
||||
- samsung,goni # Samsung Goni based on S5PC110
|
||||
- yic,smdkc110 # YIC System SMDKC110 based on S5PC110
|
||||
- yic,smdkv210 # YIC System SMDKV210 based on S5PV210
|
||||
- const: samsung,s5pv210
|
||||
|
||||
- description: S5PV210 based Aries boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P)
|
||||
- samsung,galaxys # Samsung Galaxy S (i9000)
|
||||
- const: samsung,aries
|
||||
- const: samsung,s5pv210
|
||||
|
||||
- description: Exynos3250 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,monk # Samsung Simband
|
||||
- samsung,rinato # Samsung Gear2
|
||||
- const: samsung,exynos3250
|
||||
- const: samsung,exynos3
|
||||
|
||||
- description: Samsung ARTIK5 boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,artik5-eval # Samsung ARTIK5 eval board
|
||||
- const: samsung,artik5 # Samsung ARTIK5 module
|
||||
- const: samsung,exynos3250
|
||||
- const: samsung,exynos3
|
||||
|
||||
- description: Exynos4210 based boards
|
||||
items:
|
||||
- enum:
|
||||
- insignal,origen # Insignal Origen
|
||||
- samsung,smdkv310 # Samsung SMDKV310 eval
|
||||
- samsung,trats # Samsung Tizen Reference
|
||||
- samsung,universal_c210 # Samsung C210
|
||||
- const: samsung,exynos4210
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Exynos4412 based boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,tiny4412 # FriendlyARM TINY4412
|
||||
- hardkernel,odroid-u3 # Hardkernel Odroid U3
|
||||
- hardkernel,odroid-x # Hardkernel Odroid X
|
||||
- hardkernel,odroid-x2 # Hardkernel Odroid X2
|
||||
- insignal,origen4412 # Insignal Origen
|
||||
- samsung,smdk4412 # Samsung SMDK4412 eval
|
||||
- topeet,itop4412-elite # TOPEET Elite base
|
||||
- const: samsung,exynos4412
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Samsung Midas family boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,i9300 # Samsung GT-I9300
|
||||
- samsung,i9305 # Samsung GT-I9305
|
||||
- samsung,n710x # Samsung GT-N7100/GT-N7105
|
||||
- samsung,trats2 # Samsung Tizen Reference
|
||||
- const: samsung,midas
|
||||
- const: samsung,exynos4412
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Exynos5250 based boards
|
||||
items:
|
||||
- enum:
|
||||
- google,snow-rev5 # Google Snow Rev 5+
|
||||
- google,spring # Google Spring
|
||||
- insignal,arndale # Insignal Arndale
|
||||
- samsung,smdk5250 # Samsung SMDK5250 eval
|
||||
- const: samsung,exynos5250
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Snow Boards (Rev 4+)
|
||||
items:
|
||||
- const: google,snow-rev4
|
||||
- const: google,snow
|
||||
- const: samsung,exynos5250
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5260 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,xyref5260 # Samsung Xyref5260 eval
|
||||
- const: samsung,exynos5260
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5410 based boards
|
||||
items:
|
||||
- enum:
|
||||
- hardkernel,odroid-xu # Hardkernel Odroid XU
|
||||
- samsung,smdk5410 # Samsung SMDK5410 eval
|
||||
- const: samsung,exynos5410
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5420 based boards
|
||||
items:
|
||||
- enum:
|
||||
- insignal,arndale-octa # Insignal Arndale Octa
|
||||
- samsung,smdk5420 # Samsung SMDK5420 eval
|
||||
- const: samsung,exynos5420
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Peach Pit Boards (Rev 6+)
|
||||
items:
|
||||
- const: google,pit-rev16
|
||||
- const: google,pit-rev15
|
||||
- const: google,pit-rev14
|
||||
- const: google,pit-rev13
|
||||
- const: google,pit-rev12
|
||||
- const: google,pit-rev11
|
||||
- const: google,pit-rev10
|
||||
- const: google,pit-rev9
|
||||
- const: google,pit-rev8
|
||||
- const: google,pit-rev7
|
||||
- const: google,pit-rev6
|
||||
- const: google,pit
|
||||
- const: google,peach
|
||||
- const: samsung,exynos5420
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5800 based boards
|
||||
items:
|
||||
- enum:
|
||||
- hardkernel,odroid-xu3 # Hardkernel Odroid XU3
|
||||
- hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
|
||||
- hardkernel,odroid-xu4 # Hardkernel Odroid XU4
|
||||
- hardkernel,odroid-hc1 # Hardkernel Odroid HC1
|
||||
- const: samsung,exynos5800
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Peach Pi Boards (Rev 10+)
|
||||
items:
|
||||
- const: google,pi-rev16
|
||||
- const: google,pi-rev15
|
||||
- const: google,pi-rev14
|
||||
- const: google,pi-rev13
|
||||
- const: google,pi-rev12
|
||||
- const: google,pi-rev11
|
||||
- const: google,pi-rev10
|
||||
- const: google,pi
|
||||
- const: google,peach
|
||||
- const: samsung,exynos5800
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5433 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,tm2 # Samsung TM2
|
||||
- samsung,tm2e # Samsung TM2E
|
||||
- const: samsung,exynos5433
|
||||
|
||||
- description: Exynos7 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
|
||||
- const: samsung,exynos7
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Secure Firmware
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,secure-firmware
|
||||
|
||||
reg:
|
||||
description:
|
||||
Address of non-secure SYSRAM used for communication with firmware.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware@203f000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203f000 0x1000>;
|
||||
};
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
|
||||
- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
Example:
|
||||
syscon@10010000 {
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
# Custom select to avoid matching all nodes with 'syscon'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
allOf:
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
examples:
|
||||
- |
|
||||
syscon@10010000 {
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
Spreadtrum SoC Platforms Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
SC9836 openphone Board
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sc9836-openphone", "sprd,sc9836";
|
||||
|
||||
SC9860 SoC
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sc9860"
|
||||
|
||||
SP9860G 3GFHD Board
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2019 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sprd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sc9836-openphone
|
||||
- const: sprd,sc9836
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sp9860g-1h10
|
||||
- const: sprd,sc9860
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sp9863a-1h10
|
||||
- const: sprd,sc9863a
|
||||
|
||||
...
|
||||
|
|
@ -13,19 +13,38 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f429i-disco
|
||||
- st,stm32429i-eval
|
||||
- const: st,stm32f429
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f469i-disco
|
||||
- const: st,stm32f469
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f746-disco
|
||||
- st,stm32746g-eval
|
||||
- const: st,stm32f746
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f769-disco
|
||||
- const: st,stm32f769
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32h743i-disco
|
||||
- st,stm32h743i-eval
|
||||
- const: st,stm32h743
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157c-dk2
|
||||
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
...
|
||||
|
|
|
|||
|
|
@ -1,44 +0,0 @@
|
|||
Allwinner SRAM for smp bringup:
|
||||
------------------------------------------------
|
||||
|
||||
Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
|
||||
primary core (cpu0). Once the core gets powered up it checks if a magic
|
||||
value is set at a specific location. If it is then the BROM will jump
|
||||
to the software entry address, instead of executing a standard boot.
|
||||
|
||||
Therefore a reserved section sub-node has to be added to the mmio-sram
|
||||
declaration.
|
||||
|
||||
Note that this is separate from the Allwinner SRAM controller found in
|
||||
../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
|
||||
any device.
|
||||
|
||||
Also there are no "secure-only" properties. The implementation should
|
||||
check if this SRAM is usable first.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : depending on the SoC this should be one of:
|
||||
"allwinner,sun9i-a80-smp-sram"
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sram_b: sram@20000 {
|
||||
/* 256 KiB secure SRAM at 0x20000 */
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00020000 0x40000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x00020000 0x40000>;
|
||||
|
||||
smp-sram@1000 {
|
||||
/*
|
||||
* This is checked by BROM to determine if
|
||||
* cpu0 should jump to SMP entry vector
|
||||
*/
|
||||
compatible = "allwinner,sun9i-a80-smp-sram";
|
||||
reg = <0x1000 0x8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
Required properties:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a774b1" for RZ/G2N
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
|
|
@ -9,8 +10,10 @@ Required properties:
|
|||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,sata-r8a77965" for R-Car M3-N
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2
|
||||
compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
|
||||
RZ/G2 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
|
|
|
|||
|
|
@ -1,46 +0,0 @@
|
|||
Renesas Bus State Controller (BSC)
|
||||
==================================
|
||||
|
||||
The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
|
||||
Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
|
||||
It provides an external bus for connecting multiple external devices to the
|
||||
SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
|
||||
|
||||
While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
|
||||
domain, and may have a gateable functional clock.
|
||||
Before a device connected to the BSC can be accessed, the PM domain
|
||||
containing the BSC must be powered on, and the functional clock
|
||||
driving the BSC must be enabled.
|
||||
|
||||
The bindings for the BSC extend the bindings for "simple-pm-bus".
|
||||
|
||||
|
||||
Required properties
|
||||
- compatible: Must contain an SoC-specific value, and "renesas,bsc" and
|
||||
"simple-pm-bus" as fallbacks.
|
||||
SoC-specific values can be:
|
||||
"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
|
||||
"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
- reg: Must contain the base address and length to access the bus controller.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: Must contain a reference to the BSC interrupt, if available.
|
||||
- clocks: Must contain a reference to the functional clock, if available.
|
||||
- power-domains: Must contain a reference to the PM domain, if available.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Bus State Controller (BSC)
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
|
||||
Bridge", or "External Bus Interface") can be found in several Renesas ARM
|
||||
SoCs. It provides an external bus for connecting multiple external
|
||||
devices to the SoC, driving several chip select lines, for e.g. NOR
|
||||
FLASH, Ethernet and USB.
|
||||
|
||||
While the BSC is a fairly simple memory-mapped bus, it may be part of a
|
||||
PM domain, and may have a gateable functional clock. Before a device
|
||||
connected to the BSC can be accessed, the PM domain containing the BSC
|
||||
must be powered on, and the functional clock driving the BSC must be
|
||||
enabled.
|
||||
|
||||
The bindings for the BSC extend the bindings for "simple-pm-bus".
|
||||
|
||||
allOf:
|
||||
- $ref: simple-pm-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4)
|
||||
- renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0)
|
||||
- const: renesas,bsc
|
||||
- {} # simple-pm-bus, but not listed here to avoid false select
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc", "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
Simple Power-Managed Bus
|
||||
========================
|
||||
|
||||
A Simple Power-Managed Bus is a transparent bus that doesn't need a real
|
||||
driver, as it's typically initialized by the boot loader.
|
||||
|
||||
However, its bus controller is part of a PM domain, or under the control of a
|
||||
functional clock. Hence, the bus controller's PM domain and/or clock must be
|
||||
enabled for child devices connected to the bus (either on-SoC or externally)
|
||||
to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
|
||||
in the Devicetree Specification, it is not an extension of "simple-bus".
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain at least "simple-pm-bus".
|
||||
Must not contain "simple-bus".
|
||||
It's recommended to let this be preceded by one or more
|
||||
vendor-specific compatible values.
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
|
||||
Optional platform-specific properties for clock or PM domain control (at least
|
||||
one of them is required):
|
||||
- clocks: Must contain a reference to the functional clock(s),
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
Please refer to the binding documentation for the clock and/or PM domain
|
||||
providers for more details.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple Power-Managed Bus
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
A Simple Power-Managed Bus is a transparent bus that doesn't need a real
|
||||
driver, as it's typically initialized by the boot loader.
|
||||
|
||||
However, its bus controller is part of a PM domain, or under the control
|
||||
of a functional clock. Hence, the bus controller's PM domain and/or
|
||||
clock must be enabled for child devices connected to the bus (either
|
||||
on-SoC or externally) to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as
|
||||
specified in the Devicetree Specification, it is not an extension of
|
||||
"simple-bus".
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^bus(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
contains:
|
||||
const: simple-pm-bus
|
||||
description:
|
||||
Shall contain "simple-pm-bus" in addition to a optional bus-specific
|
||||
compatible strings defined in individual pm-bus bindings.
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
clocks: true
|
||||
# Functional clocks
|
||||
# Required if power-domains is absent, optional otherwise
|
||||
|
||||
power-domains:
|
||||
# Required if clocks is absent, optional otherwise
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- ranges
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- clocks
|
||||
- required:
|
||||
- power-domains
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bus {
|
||||
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
};
|
||||
|
|
@ -62,7 +62,7 @@ Required Properties:
|
|||
power-managed through Module Standby should refer to the CPG device
|
||||
node in their "power-domains" property, as documented by the generic PM
|
||||
Domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
|
||||
- #reset-cells: Must be 1
|
||||
- The single reset specifier cell must be the module number, as defined
|
||||
|
|
|
|||
|
|
@ -67,5 +67,5 @@ Examples:
|
|||
|
||||
Also see:
|
||||
- Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
- Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
|
||||
|
||||
STM32 Low-Power Timer provides several counter modes. It can be used as:
|
||||
- quadrature encoder to detect angular position and direction of rotary
|
||||
elements, from IN1 and IN2 input signals.
|
||||
- simple counter from IN1 input signal.
|
||||
|
||||
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-counter".
|
||||
- pinctrl-names: Set to "default". An additional "sleep" state can be
|
||||
defined to set pins in sleep state.
|
||||
- pinctrl-n: List of phandles pointing to pin configuration nodes,
|
||||
to set IN1/IN2 pins in mode of operation for Low-Power
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
...
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lptim1_in_pins>;
|
||||
pinctrl-1 = <&lptim1_sleep_in_pins>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
STMicroelectronics STM32 Timer quadrature encoder
|
||||
|
||||
STM32 Timer provides quadrature encoder to detect
|
||||
angular position and direction of rotary elements,
|
||||
from IN1 and IN2 input signals.
|
||||
|
||||
Must be a sub-node of an STM32 Timer device tree node.
|
||||
See ../mfd/stm32-timers.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-timer-counter".
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||
to set CH1/CH2 pins in mode of operation for STM32
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 160>;
|
||||
clock-names = "int";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-timer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tim1_in_pins>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
Samsung SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entry for slimSSS version:
|
||||
- "samsung,exynos5433-slim-sss" for Exynos5433 SoC.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SlimSSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain "pclk" and
|
||||
"aclk" for slim-sss in Exynos5433.
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-slimsss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Kamil Konieczny <k.konieczny@partner.samsung.com>
|
||||
|
||||
description: |+
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,exynos5433-slim-ss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: aclk
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
Samsung SoC SSS (Security SubSystem) module
|
||||
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and
|
||||
Exynos5 (Exynos5420 and Exynos5250) SoCs
|
||||
supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SSS versions:
|
||||
- "samsung,s5pv210-secss" for S5PV210 SoC.
|
||||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain one entry
|
||||
"secss".
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SSS (Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Kamil Konieczny <k.konieczny@partner.samsung.com>
|
||||
|
||||
description: |+
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and Exynos5 (Exynos5420 and Exynos5250)
|
||||
SoCs supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,s5pv210-secss # for S5PV210
|
||||
- samsung,exynos4210-secss # for Exynos4210, Exynos4212,
|
||||
# Exynos4412, Exynos5250,
|
||||
# Exynos5260 and Exynos5420
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: secss
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
* STMicroelectronics STM32 CRC
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f7-crc".
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- clocks: The input clock of the CRC instance
|
||||
|
||||
Optional properties: none
|
||||
|
||||
Example:
|
||||
|
||||
crc: crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 12>;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRC bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32f7-crc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 12>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
* STMicroelectronics STM32 CRYP
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f756-cryp".
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- clocks: The input clock of the CRYP instance
|
||||
- interrupts: The CRYP interrupt
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the CRYP instance
|
||||
|
||||
Example:
|
||||
crypto@50060000 {
|
||||
compatible = "st,stm32f756-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
interrupts = <79>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRYP bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f756-cryp
|
||||
- st,stm32mp1-cryp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
* STMicroelectronics STM32 HASH
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain entries for this and backward compatible
|
||||
HASH versions:
|
||||
- "st,stm32f456-hash" for stm32 F456.
|
||||
- "st,stm32f756-hash" for stm32 F756.
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- interrupts: the interrupt specifier for the HASH
|
||||
- clocks: The input clock of the HASH instance
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the HASH instance
|
||||
- dmas: DMA specifiers for the HASH. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request name. Should be "in" if a dma is present.
|
||||
- dma-maxburst: Set number of maximum dma burst supported
|
||||
|
||||
Example:
|
||||
|
||||
hash1: hash@50060400 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x50060400 0x400>;
|
||||
interrupts = <80>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
|
||||
dmas = <&dma2 7 2 0x400 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 HASH bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f456-hash
|
||||
- st,stm32f756-hash
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: in
|
||||
|
||||
dma-maxburst:
|
||||
description: Set number of maximum dma burst supported
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 0
|
||||
- maximum: 2
|
||||
- default: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -79,8 +79,6 @@ properties:
|
|||
|
||||
hdmi-supply:
|
||||
description: phandle to an external 5V regulator to power the HDMI logic
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ Optional properties:
|
|||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify flags.
|
||||
See ../../gpio/gpio.txt for more information.
|
||||
- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
|
||||
- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of
|
||||
the cell formats.
|
||||
|
||||
- clock-names: should be "refclk"
|
||||
|
|
|
|||
|
|
@ -27,11 +27,11 @@ Example:
|
|||
|
||||
display: display {
|
||||
model = "320x240x4";
|
||||
native-mode = <&timing0>;
|
||||
bits-per-pixel = <4>;
|
||||
ac-prescale = <17>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: 320x240 {
|
||||
hactive = <320>;
|
||||
hback-porch = <0>;
|
||||
|
|
|
|||
|
|
@ -38,10 +38,10 @@ Example:
|
|||
|
||||
display0: display0 {
|
||||
model = "Primeview-PD050VL1";
|
||||
native-mode = <&timing_disp0>;
|
||||
bits-per-pixel = <16>;
|
||||
fsl,pcr = <0xf0c88080>; /* non-standard but required */
|
||||
display-timings {
|
||||
native-mode = <&timing_disp0>;
|
||||
timing_disp0: 640x480 {
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
|
|
|
|||
|
|
@ -1,26 +0,0 @@
|
|||
Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,ld-d5116z01b"
|
||||
- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
|
||||
|
||||
This binding is compatible with the simple-panel binding.
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in [1]. This
|
||||
node should describe panel's video bus.
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
|
||||
panel: panel {
|
||||
compatible = "sharp,ld-d5116z01b";
|
||||
power-supply = <&vlcd_3v3>;
|
||||
|
||||
port {
|
||||
panel_ep: endpoint {
|
||||
remote-endpoint = <&bridge_out_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
|
||||
|
||||
maintainers:
|
||||
- Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sharp,ld-d5116z01b
|
||||
|
||||
power-supply: true
|
||||
backlight: true
|
||||
port: true
|
||||
no-hpd: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- power-supply
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 DSI host controller
|
||||
|
||||
maintainers:
|
||||
- Philippe Cornu <philippe.cornu@st.com>
|
||||
- Yannick Fertre <yannick.fertre@st.com>
|
||||
|
||||
description:
|
||||
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-dsi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Module Clock
|
||||
- description: DSI bus clock
|
||||
- description: Pixel clock
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: ref
|
||||
- const: px_clk
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
|
||||
phy-dsi-supply:
|
||||
description:
|
||||
Phandle of the regulator that provides the supply voltage.
|
||||
|
||||
ports:
|
||||
type: object
|
||||
description:
|
||||
A node containing DSI input & output port nodes with endpoint
|
||||
definitions as documented in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
properties:
|
||||
port@0:
|
||||
type: object
|
||||
description:
|
||||
DSI input port node, connected to the ltdc rgb output port.
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
description:
|
||||
DSI output port node, connected to a panel or a bridge input port"
|
||||
|
||||
patternProperties:
|
||||
"^(panel|panel-dsi)@[0-9]$":
|
||||
type: object
|
||||
description:
|
||||
A node containing the panel or bridge description as documented in
|
||||
Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
|
||||
properties:
|
||||
port:
|
||||
type: object
|
||||
description:
|
||||
Panel or bridge port node, connected to the DSI output port (port@1)
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
dsi: dsi@5a000000 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x5a000000 0x800>;
|
||||
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
||||
clock-names = "pclk", "ref", "px_clk";
|
||||
resets = <&rcc DSI_R>;
|
||||
reset-names = "apb";
|
||||
phy-dsi-supply = <®18>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_ep1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel-dsi@0 {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&v3v3>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
* STMicroelectronics STM32 lcd-tft display controller
|
||||
|
||||
- ltdc: lcd-tft display controller host
|
||||
Required properties:
|
||||
- compatible: "st,stm32-ltdc"
|
||||
- reg: Physical base address of the IP registers and length of memory mapped region.
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For ltdc it should contain:
|
||||
- "lcd" for the clock feeding the output pixel clock & IP clock.
|
||||
- resets: reset to be used by the device (defined by use of RCC macro).
|
||||
Required nodes:
|
||||
- Video port for DPI RGB output: ltdc has one video port with up to 2
|
||||
endpoints:
|
||||
- for external dpi rgb panel or bridge, using gpios.
|
||||
- for internal dpi input of the MIPI DSI host controller.
|
||||
Note: These 2 endpoints cannot be activated simultaneously.
|
||||
|
||||
* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
|
||||
DesignWare MIPI DSI host controller
|
||||
|
||||
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
|
||||
DSI host controller. For all mandatory properties & nodes, please refer
|
||||
to the related documentation in [5].
|
||||
|
||||
Mandatory properties specific to STM32 DSI:
|
||||
- #address-cells: Should be <1>.
|
||||
- #size-cells: Should be <0>.
|
||||
- compatible: "st,stm32-dsi".
|
||||
- clock-names:
|
||||
- phy pll reference clock string name, must be "ref".
|
||||
- resets: see [5].
|
||||
- reset-names: see [5].
|
||||
|
||||
Mandatory nodes specific to STM32 DSI:
|
||||
- ports: A node containing DSI input & output port nodes with endpoint
|
||||
definitions as documented in [3] & [4].
|
||||
- port@0: DSI input port node, connected to the ltdc rgb output port.
|
||||
- port@1: DSI output port node, connected to a panel or a bridge input port.
|
||||
- panel or bridge node: A node containing the panel or bridge description as
|
||||
documented in [6].
|
||||
- port: panel or bridge port node, connected to the DSI output port (port@1).
|
||||
Optional properties:
|
||||
- phy-dsi-supply: phandle of the regulator that provides the supply voltage.
|
||||
|
||||
Note: You can find more documentation in the following references
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/reset/reset.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/graph.txt
|
||||
[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
|
||||
[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
|
||||
|
||||
Example 1: RGB panel
|
||||
/ {
|
||||
...
|
||||
soc {
|
||||
...
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
|
||||
port {
|
||||
ltdc_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2: DSI panel
|
||||
|
||||
/ {
|
||||
...
|
||||
soc {
|
||||
...
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
|
||||
port {
|
||||
ltdc_out_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
dsi: dsi@40016c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x40016c00 0x800>;
|
||||
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
|
||||
clock-names = "pclk", "ref";
|
||||
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
|
||||
reset-names = "apb";
|
||||
phy-dsi-supply = <®18>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_out_dsi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&dsi_in_panel>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
panel-dsi@0 {
|
||||
reg = <0>; /* dsi virtual channel (0..3) */
|
||||
compatible = ...;
|
||||
enable-gpios = ...;
|
||||
|
||||
port {
|
||||
dsi_in_panel: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 lcd-tft display controller
|
||||
|
||||
maintainers:
|
||||
- Philippe Cornu <philippe.cornu@st.com>
|
||||
- Yannick Fertre <yannick.fertre@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-ltdc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: events interrupt line.
|
||||
- description: errors interrupt line.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: lcd
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
port:
|
||||
type: object
|
||||
description:
|
||||
"Video port for DPI RGB output.
|
||||
ltdc has one video port with up to 2 endpoints:
|
||||
- for external dpi rgb panel or bridge, using gpios.
|
||||
- for internal dpi input of the MIPI DSI host controller.
|
||||
Note: These 2 endpoints cannot be activated simultaneously.
|
||||
Please refer to the bindings defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt."
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x5a001000 0x400>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LTDC_PX>;
|
||||
clock-names = "lcd";
|
||||
resets = <&rcc LTDC_R>;
|
||||
|
||||
port {
|
||||
ltdc_out_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
|
@ -68,9 +68,7 @@ else:
|
|||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -1,89 +1 @@
|
|||
EEPROMs (I2C)
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be a "<manufacturer>,<model>" pair. The following <model>
|
||||
values are supported (assuming "atmel" as manufacturer):
|
||||
|
||||
"atmel,24c00",
|
||||
"atmel,24c01",
|
||||
"atmel,24cs01",
|
||||
"atmel,24c02",
|
||||
"atmel,24cs02",
|
||||
"atmel,24mac402",
|
||||
"atmel,24mac602",
|
||||
"atmel,spd",
|
||||
"atmel,24c04",
|
||||
"atmel,24cs04",
|
||||
"atmel,24c08",
|
||||
"atmel,24cs08",
|
||||
"atmel,24c16",
|
||||
"atmel,24cs16",
|
||||
"atmel,24c32",
|
||||
"atmel,24cs32",
|
||||
"atmel,24c64",
|
||||
"atmel,24cs64",
|
||||
"atmel,24c128",
|
||||
"atmel,24c256",
|
||||
"atmel,24c512",
|
||||
"atmel,24c1024",
|
||||
"atmel,24c2048",
|
||||
|
||||
If <manufacturer> is not "atmel", then a fallback must be used
|
||||
with the same <model> and "atmel" as manufacturer.
|
||||
|
||||
Example:
|
||||
compatible = "microchip,24c128", "atmel,24c128";
|
||||
|
||||
Supported manufacturers are:
|
||||
|
||||
"catalyst",
|
||||
"microchip",
|
||||
"nxp",
|
||||
"ramtron",
|
||||
"renesas",
|
||||
"rohm",
|
||||
"st",
|
||||
|
||||
Some vendors use different model names for chips which are just
|
||||
variants of the above. Known such exceptions are listed below:
|
||||
|
||||
"nxp,se97b" - the fallback is "atmel,24c02",
|
||||
"renesas,r1ex24002" - the fallback is "atmel,24c02"
|
||||
"renesas,r1ex24016" - the fallback is "atmel,24c16"
|
||||
"renesas,r1ex24128" - the fallback is "atmel,24c128"
|
||||
"rohm,br24t01" - the fallback is "atmel,24c01"
|
||||
|
||||
- reg: The I2C address of the EEPROM.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- pagesize: The length of the pagesize for writing. Please consult the
|
||||
manual of your device, that value varies a lot. A wrong value
|
||||
may result in data loss! If not specified, a safety value of
|
||||
'1' is used which will be very slow.
|
||||
|
||||
- read-only: This parameterless property disables writes to the eeprom.
|
||||
|
||||
- size: Total eeprom size in bytes.
|
||||
|
||||
- no-read-rollover: This parameterless property indicates that the
|
||||
multi-address eeprom does not automatically roll over
|
||||
reads to the next slave address. Please consult the
|
||||
manual of your device.
|
||||
|
||||
- wp-gpios: GPIO to which the write-protect pin of the chip is connected.
|
||||
|
||||
- address-width: number of address bits (one of 8, 16).
|
||||
|
||||
- num-addresses: total number of i2c slave addresses this device takes
|
||||
|
||||
Example:
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x52>;
|
||||
pagesize = <32>;
|
||||
wp-gpios = <&gpio1 3 0>;
|
||||
num-addresses = <8>;
|
||||
};
|
||||
This file has been moved to at24.yaml.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,188 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# Copyright 2019 BayLibre SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/eeprom/at24.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: I2C EEPROMs compatible with Atmel's AT24
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^eeprom@[0-9a-f]{1,2}$"
|
||||
|
||||
# There are multiple known vendors who manufacture EEPROM chips compatible
|
||||
# with Atmel's AT24. The compatible string requires either a single item
|
||||
# if the memory comes from Atmel (in which case the vendor part must be
|
||||
# 'atmel') or two items with the same 'model' part where the vendor part of
|
||||
# the first one is the actual manufacturer and the second item is the
|
||||
# corresponding 'atmel,<model>' from Atmel.
|
||||
compatible:
|
||||
oneOf:
|
||||
- allOf:
|
||||
- minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|mac)[0-9]+|spd)$"
|
||||
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
|
||||
- oneOf:
|
||||
- items:
|
||||
pattern: c00$
|
||||
- items:
|
||||
pattern: c01$
|
||||
- items:
|
||||
pattern: cs01$
|
||||
- items:
|
||||
pattern: c02$
|
||||
- items:
|
||||
pattern: cs02$
|
||||
- items:
|
||||
pattern: mac402$
|
||||
- items:
|
||||
pattern: mac602$
|
||||
- items:
|
||||
pattern: c04$
|
||||
- items:
|
||||
pattern: cs04$
|
||||
- items:
|
||||
pattern: c08$
|
||||
- items:
|
||||
pattern: cs08$
|
||||
- items:
|
||||
pattern: c16$
|
||||
- items:
|
||||
pattern: cs16$
|
||||
- items:
|
||||
pattern: c32$
|
||||
- items:
|
||||
pattern: cs32$
|
||||
- items:
|
||||
pattern: c64$
|
||||
- items:
|
||||
pattern: cs64$
|
||||
- items:
|
||||
pattern: c128$
|
||||
- items:
|
||||
pattern: cs128$
|
||||
- items:
|
||||
pattern: c256$
|
||||
- items:
|
||||
pattern: cs256$
|
||||
- items:
|
||||
pattern: c512$
|
||||
- items:
|
||||
pattern: cs512$
|
||||
- items:
|
||||
pattern: c1024$
|
||||
- items:
|
||||
pattern: cs1024$
|
||||
- items:
|
||||
pattern: c2048$
|
||||
- items:
|
||||
pattern: cs2048$
|
||||
- items:
|
||||
pattern: spd$
|
||||
# These are special cases that don't conform to the above pattern.
|
||||
# Each requires a standard at24 model as fallback.
|
||||
- items:
|
||||
- const: rohm,br24t01
|
||||
- const: atmel,24c01
|
||||
- items:
|
||||
- const: nxp,se97b
|
||||
- const: atmel,24c02
|
||||
- items:
|
||||
- const: renesas,r1ex24002
|
||||
- const: atmel,24c02
|
||||
- items:
|
||||
- const: renesas,r1ex24016
|
||||
- const: atmel,24c16
|
||||
- items:
|
||||
- const: giantec,gt24c32a
|
||||
- const: atmel,24c32
|
||||
- items:
|
||||
- const: renesas,r1ex24128
|
||||
- const: atmel,24c128
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
pagesize:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The length of the pagesize for writing. Please consult the
|
||||
manual of your device, that value varies a lot. A wrong value
|
||||
may result in data loss! If not specified, a safety value of
|
||||
'1' is used which will be very slow.
|
||||
enum: [ 1, 8, 16, 32, 64, 128, 258 ]
|
||||
default: 1
|
||||
|
||||
read-only:
|
||||
$ref: /schemas/types.yaml#definitions/flag
|
||||
description:
|
||||
Disables writes to the eeprom.
|
||||
|
||||
size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Total eeprom size in bytes.
|
||||
|
||||
no-read-rollover:
|
||||
$ref: /schemas/types.yaml#definitions/flag
|
||||
description:
|
||||
Indicates that the multi-address eeprom does not automatically roll
|
||||
over reads to the next slave address. Please consult the manual of
|
||||
your device.
|
||||
|
||||
wp-gpios:
|
||||
description:
|
||||
GPIO to which the write-protect pin of the chip is connected.
|
||||
maxItems: 1
|
||||
|
||||
address-width:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of address bits.
|
||||
default: 8
|
||||
enum: [ 8, 16 ]
|
||||
|
||||
num-addresses:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Total number of i2c slave addresses this device takes.
|
||||
default: 1
|
||||
minimum: 1
|
||||
maximum: 8
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "microchip,24c32", "atmel,24c32";
|
||||
reg = <0x52>;
|
||||
pagesize = <32>;
|
||||
wp-gpios = <&gpio1 3 0>;
|
||||
num-addresses = <8>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2018 Linaro Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
|
|
@ -71,7 +71,7 @@ properties:
|
|||
# minItems/maxItems equal to 2 is implied
|
||||
|
||||
reg-names:
|
||||
# The core schema enforces this is a string array
|
||||
# The core schema enforces this (*-names) is a string array
|
||||
items:
|
||||
- const: core
|
||||
- const: aux
|
||||
|
|
@ -79,7 +79,8 @@ properties:
|
|||
clocks:
|
||||
# Cases that have only a single entry just need to express that with maxItems
|
||||
maxItems: 1
|
||||
description: bus clock
|
||||
description: bus clock. A description is only needed for a single item if
|
||||
there's something unique to add.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
|
@ -127,6 +128,14 @@ properties:
|
|||
maxItems: 1
|
||||
description: A connection of the 'foo' gpio line.
|
||||
|
||||
# *-supply is always a single phandle, so nothing more to define.
|
||||
foo-supply: true
|
||||
|
||||
# Vendor specific properties
|
||||
#
|
||||
# Vendor specific properties have slightly different schema requirements than
|
||||
# common properties. They must have at least a type definition and
|
||||
# 'description'.
|
||||
vendor,int-property:
|
||||
description: Vendor specific properties must have a description
|
||||
# 'allOf' is the json-schema way of subclassing a schema. Here the base
|
||||
|
|
@ -137,9 +146,9 @@ properties:
|
|||
- enum: [2, 4, 6, 8, 10]
|
||||
|
||||
vendor,bool-property:
|
||||
description: Vendor specific properties must have a description
|
||||
# boolean properties is one case where the json-schema 'type' keyword
|
||||
# can be used directly
|
||||
description: Vendor specific properties must have a description. Boolean
|
||||
properties are one case where the json-schema 'type' keyword can be used
|
||||
directly.
|
||||
type: boolean
|
||||
|
||||
vendor,string-array-property:
|
||||
|
|
@ -151,14 +160,72 @@ properties:
|
|||
- enum: [ foo, bar ]
|
||||
- enum: [ baz, boo ]
|
||||
|
||||
vendor,property-in-standard-units-microvolt:
|
||||
description: Vendor specific properties having a standard unit suffix
|
||||
don't need a type.
|
||||
enum: [ 100, 200, 300 ]
|
||||
|
||||
child-node:
|
||||
description: Child nodes are just another property from a json-schema
|
||||
perspective.
|
||||
type: object # DT nodes are json objects
|
||||
properties:
|
||||
vendor,a-child-node-property:
|
||||
description: Child node properties have all the same schema
|
||||
requirements.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- vendor,a-child-node-property
|
||||
|
||||
# Describe the relationship between different properties
|
||||
dependencies:
|
||||
# 'vendor,bool-property' is only allowed when 'vendor,string-array-property'
|
||||
# is present
|
||||
vendor,bool-property: [ vendor,string-array-property ]
|
||||
# Expressing 2 properties in both orders means all of the set of properties
|
||||
# must be present or none of them.
|
||||
vendor,string-array-property: [ vendor,bool-property ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
|
||||
# if/then schema can be used to handle conditions on a property affecting
|
||||
# another property. A typical case is a specific 'compatible' value changes the
|
||||
# constraints on other properties.
|
||||
#
|
||||
# For multiple 'if' schema, group them under an 'allOf'.
|
||||
#
|
||||
# If the conditionals become too unweldy, then it may be better to just split
|
||||
# the binding into separate schema documents.
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: vendor,soc2-ip
|
||||
then:
|
||||
required:
|
||||
- foo-supply
|
||||
|
||||
# Ideally, the schema should have this line otherwise any other properties
|
||||
# present are allowed. There's a few common properties such as 'status' and
|
||||
# 'pinctrl-*' which are added automatically by the tooling.
|
||||
#
|
||||
# This can't be used in cases where another schema is referenced
|
||||
# (i.e. allOf: [{$ref: ...}]).
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Examples are now compiled with dtc
|
||||
# Examples are now compiled with dtc and validated against the schemas
|
||||
#
|
||||
# Examples have a default #address-cells and #size-cells value of 1. This can
|
||||
# be overridden or an appropriate parent bus node should be shown (such as on
|
||||
# i2c buses).
|
||||
#
|
||||
# Any includes used have to be explicitly included.
|
||||
- |
|
||||
node@1000 {
|
||||
compatible = "vendor,soc4-ip", "vendor,soc1-ip";
|
||||
|
|
|
|||
|
|
@ -25,8 +25,6 @@ properties:
|
|||
- const: intel,ixp4xx-network-processing-engine
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: NPE0 register range
|
||||
- description: NPE1 register range
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ implemented by this node:
|
|||
|
||||
- .../clock/clock-bindings.txt
|
||||
- <dt-bindings/clock/tegra186-clock.h>
|
||||
- ../power/power_domain.txt
|
||||
- ../power/power-domain.yaml
|
||||
- <dt-bindings/power/tegra186-powergate.h>
|
||||
- .../reset/reset.txt
|
||||
- <dt-bindings/reset/tegra186-reset.h>
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- amlogic,meson-g12a-mali
|
||||
- realtek,rtd1619-mali
|
||||
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
|
||||
|
||||
reg:
|
||||
|
|
@ -37,8 +38,7 @@ properties:
|
|||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
mali-supply:
|
||||
maxItems: 1
|
||||
mali-supply: true
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,14 @@ properties:
|
|||
pattern: '^gpu@[a-f0-9]+$'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5250-mali
|
||||
- const: arm,mali-t604
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5420-mali
|
||||
- const: arm,mali-t628
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,sun50i-h6-mali
|
||||
|
|
@ -21,26 +29,19 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- amlogic,meson-gxm-mali
|
||||
- realtek,rtd1295-mali
|
||||
- const: arm,mali-t820
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3288-mali
|
||||
- samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3399-mali
|
||||
- const: arm,mali-t860
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5250-mali
|
||||
- const: arm,mali-t604
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
|
||||
# "arm,mali-t624"
|
||||
# "arm,mali-t628"
|
||||
# "arm,mali-t830"
|
||||
# "arm,mali-t880"
|
||||
|
||||
|
|
@ -69,8 +70,7 @@ properties:
|
|||
- const: core
|
||||
- const: bus
|
||||
|
||||
mali-supply:
|
||||
maxItems: 1
|
||||
mali-supply: true
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
|
|
|
|||
|
|
@ -97,8 +97,7 @@ properties:
|
|||
|
||||
memory-region: true
|
||||
|
||||
mali-supply:
|
||||
maxItems: 1
|
||||
mali-supply: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -1,27 +0,0 @@
|
|||
* Samsung 2D Graphics Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one among the following:
|
||||
(a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
|
||||
(b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
|
||||
(c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : G2D interrupt number to the CPU.
|
||||
- clocks : from common clock binding: handle to G2D clocks.
|
||||
- clock-names : names of clocks listed in clocks property, in the same
|
||||
order, depending on SoC type:
|
||||
- for S5PV210 and Exynos4 based SoCs: "fimg2d" and
|
||||
"sclk_fimg2d"
|
||||
- for Exynos5250 SoC: "fimg2d".
|
||||
|
||||
Example:
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC 2D Graphics Accelerator
|
||||
|
||||
maintainers:
|
||||
- Inki Dae <inki.dae@samsung.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s5pv210-g2d # in S5PV210 & Exynos4210 SoC
|
||||
- samsung,exynos4212-g2d # in Exynos4x12 SoCs
|
||||
- samsung,exynos5250-g2d
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks: {}
|
||||
clock-names: {}
|
||||
iommus: {}
|
||||
power-domains: {}
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5250-g2d
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: fimg2d clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: fimg2d
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: sclk_fimg2d clock
|
||||
- description: fimg2d clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: sclk_fimg2d
|
||||
- const: fimg2d
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
interrupts = <0 89 0>;
|
||||
clocks = <&clock 177>, <&clock 277>;
|
||||
clock-names = "sclk_fimg2d", "fimg2d";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
* Samsung Image Rotator
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one of the following:
|
||||
* "samsung,s5pv210-rotator" for Rotator IP in S5PV210
|
||||
* "samsung,exynos4210-rotator" for Rotator IP in Exynos4210
|
||||
* "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412
|
||||
* "samsung,exynos5250-rotator" for Rotator IP in Exynos5250
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : Interrupt specifier for rotator interrupt, according to format
|
||||
specific to interrupt parent.
|
||||
|
||||
- clocks : Clock specifier for rotator clock, according to generic clock
|
||||
bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
|
||||
|
||||
- clock-names : Names of clocks. For exynos rotator, it should be "rotator".
|
||||
|
||||
Example:
|
||||
rotator@12810000 {
|
||||
compatible = "samsung,exynos4210-rotator";
|
||||
reg = <0x12810000 0x1000>;
|
||||
interrupts = <0 83 0>;
|
||||
clocks = <&clock 278>;
|
||||
clock-names = "rotator";
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/samsung-rotator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC Image Rotator
|
||||
|
||||
maintainers:
|
||||
- Inki Dae <inki.dae@samsung.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- "samsung,s5pv210-rotator"
|
||||
- "samsung,exynos4210-rotator"
|
||||
- "samsung,exynos4212-rotator"
|
||||
- "samsung,exynos5250-rotator"
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: rotator
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
rotator@12810000 {
|
||||
compatible = "samsung,exynos4210-rotator";
|
||||
reg = <0x12810000 0x1000>;
|
||||
interrupts = <0 83 0>;
|
||||
clocks = <&clock 278>;
|
||||
clock-names = "rotator";
|
||||
};
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
* Samsung Exynos Image Scaler
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be one of the following:
|
||||
(a) "samsung,exynos5420-scaler" for Scaler IP in Exynos5420
|
||||
(b) "samsung,exynos5433-scaler" for Scaler IP in Exynos5433
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : Interrupt specifier for scaler interrupt, according to format
|
||||
specific to interrupt parent.
|
||||
|
||||
- clocks : Clock specifier for scaler clock, according to generic clock
|
||||
bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
|
||||
|
||||
- clock-names : Names of clocks. For exynos scaler, it should be "mscl"
|
||||
on 5420 and "pclk", "aclk" and "aclk_xiu" on 5433.
|
||||
|
||||
Example:
|
||||
scaler@12800000 {
|
||||
compatible = "samsung,exynos5420-scaler";
|
||||
reg = <0x12800000 0x1294>;
|
||||
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_MSCL0>;
|
||||
clock-names = "mscl";
|
||||
};
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC Image Scaler
|
||||
|
||||
maintainers:
|
||||
- Inki Dae <inki.dae@samsung.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos5420-scaler
|
||||
- samsung,exynos5433-scaler
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks: {}
|
||||
clock-names: {}
|
||||
iommus: {}
|
||||
power-domains: {}
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos5420-scaler
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: mscl clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: mscl
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: pclk clock
|
||||
- description: aclk clock
|
||||
- description: aclk_xiu clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: aclk
|
||||
- const: aclk_xiu
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
scaler@12800000 {
|
||||
compatible = "samsung,exynos5420-scaler";
|
||||
reg = <0x12800000 0x1294>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_MSCL0>;
|
||||
clock-names = "mscl";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
STM32 Hardware Spinlock Device Binding
|
||||
-------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : should be "st,stm32-hwspinlock".
|
||||
- reg : the register address of hwspinlock.
|
||||
- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
|
||||
hwlock, so the number of cells should be <1> here.
|
||||
- clock-names : Must contain "hsem".
|
||||
- clocks : Must contain a phandle entry for the clock in clock-names, see the
|
||||
common clock bindings.
|
||||
|
||||
Please look at the generic hwlock binding for usage information for consumers,
|
||||
"Documentation/devicetree/bindings/hwlock/hwlock.txt"
|
||||
|
||||
Example of hwlock provider:
|
||||
hwspinlock@4c000000 {
|
||||
compatible = "st,stm32-hwspinlock";
|
||||
#hwlock-cells = <1>;
|
||||
reg = <0x4c000000 0x400>;
|
||||
clocks = <&rcc HSEM>;
|
||||
clock-names = "hsem";
|
||||
};
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 Hardware Spinlock bindings
|
||||
|
||||
maintainers:
|
||||
- Benjamin Gaignard <benjamin.gaignard@st.com>
|
||||
- Fabien Dessenne <fabien.dessenne@st.com>
|
||||
|
||||
properties:
|
||||
"#hwlock-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: st,stm32-hwspinlock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: hsem
|
||||
|
||||
required:
|
||||
- "#hwlock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
hwspinlock@4c000000 {
|
||||
compatible = "st,stm32-hwspinlock";
|
||||
#hwlock-cells = <1>;
|
||||
reg = <0x4c000000 0x400>;
|
||||
clocks = <&rcc HSEM>;
|
||||
clock-names = "hsem";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -40,9 +40,7 @@ required:
|
|||
- clocks
|
||||
- resets
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -1,65 +0,0 @@
|
|||
* I2C controller embedded in STMicroelectronics STM32 I2C platform
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of the following
|
||||
- "st,stm32f4-i2c"
|
||||
- "st,stm32f7-i2c"
|
||||
- reg: Offset and length of the register set for the device
|
||||
- interrupts: Must contain the interrupt id for I2C event and then the
|
||||
interrupt id for I2C error.
|
||||
- resets: Must contain the phandle to the reset controller.
|
||||
- clocks: Must contain the input clock of the I2C instance.
|
||||
- A pinctrl state named "default" must be defined to set pins in mode of
|
||||
operation for I2C transfer
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used.
|
||||
For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
|
||||
100000 and 400000.
|
||||
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
|
||||
Plus are supported, possible values are 100000, 400000 and 1000000.
|
||||
- dmas: List of phandles to rx and tx DMA channels. Refer to stm32-dma.txt.
|
||||
- dma-names: List of dma names. Valid names are: "rx" and "tx".
|
||||
- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
I2C Timings are derived from these 2 values
|
||||
- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
|
||||
Plus speed is selected by slave.
|
||||
1st cell: phandle to syscfg
|
||||
2nd cell: register offset within SYSCFG
|
||||
3rd cell: register bitmask for FMP bit
|
||||
For STM32F7, STM32H7 and STM32MP1 only.
|
||||
|
||||
Example:
|
||||
|
||||
i2c@40005400 {
|
||||
compatible = "st,stm32f4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc 277>;
|
||||
clocks = <&rcc 0 149>;
|
||||
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
i2c@40005400 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
|
||||
clocks = <&rcc 1 CLK_I2C1>;
|
||||
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
|
||||
pinctrl-names = "default";
|
||||
st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
||||
};
|
||||
|
|
@ -93,9 +93,7 @@ allOf:
|
|||
required:
|
||||
- resets
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,141 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: I2C controller embedded in STMicroelectronics STM32 I2C platform
|
||||
|
||||
maintainers:
|
||||
- Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32f7-i2c
|
||||
then:
|
||||
properties:
|
||||
i2c-scl-rising-time-ns:
|
||||
default: 25
|
||||
|
||||
i2c-scl-falling-time-ns:
|
||||
default: 10
|
||||
|
||||
st,syscfg-fmp:
|
||||
description: Use to set Fast Mode Plus bit within SYSCFG when
|
||||
Fast Mode Plus speed is selected by slave.
|
||||
Format is phandle to syscfg / register offset within
|
||||
syscfg / register bitmask for FMP bit.
|
||||
allOf:
|
||||
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
|
||||
- items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32f4-i2c
|
||||
then:
|
||||
properties:
|
||||
clock-frequency:
|
||||
enum: [100000, 400000]
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f4-i2c
|
||||
- st,stm32f7-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: interrupt ID for I2C event
|
||||
- description: interrupt ID for I2C error
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: RX DMA Channel phandle
|
||||
- description: TX DMA Channel phandle
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
clock-frequency:
|
||||
description: Desired I2C bus clock frequency in Hz. If not specified,
|
||||
the default 100 kHz frequency will be used.
|
||||
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode,
|
||||
Fast-mode and Fast-mode Plus are supported, possible
|
||||
values are 100000, 400000 and 1000000.
|
||||
default: 100000
|
||||
enum: [100000, 400000, 1000000]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- resets
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/mfd/stm32f7-rcc.h>
|
||||
#include <dt-bindings/clock/stm32fx-clock.h>
|
||||
//Example 1 (with st,stm32f4-i2c compatible)
|
||||
i2c@40005400 {
|
||||
compatible = "st,stm32f4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc 277>;
|
||||
clocks = <&rcc 0 149>;
|
||||
};
|
||||
|
||||
//Example 2 (with st,stm32f7-i2c compatible)
|
||||
i2c@40005800 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
|
||||
clocks = <&rcc 1 CLK_I2C1>;
|
||||
};
|
||||
|
||||
//Example 3 (with st,stm32f7-i2c compatible on stm32mp)
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
i2c@40013000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C2_K>;
|
||||
resets = <&rcc I2C2_R>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
||||
};
|
||||
...
|
||||
|
|
@ -45,15 +45,12 @@ properties:
|
|||
|
||||
refin1-supply:
|
||||
description: refin1 supply can be used as reference for conversion.
|
||||
maxItems: 1
|
||||
|
||||
refin2-supply:
|
||||
description: refin2 supply can be used as reference for conversion.
|
||||
maxItems: 1
|
||||
|
||||
avdd-supply:
|
||||
description: avdd supply can be used as reference for conversion.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -31,10 +31,7 @@ properties:
|
|||
|
||||
spi-cpha: true
|
||||
|
||||
avcc-supply:
|
||||
description:
|
||||
Phandle to the Avcc power supply
|
||||
maxItems: 1
|
||||
avcc-supply: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ properties:
|
|||
avdd-supply:
|
||||
description:
|
||||
The regulator supply for the ADC reference voltage.
|
||||
maxItems: 1
|
||||
|
||||
powerdown-gpios:
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@ properties:
|
|||
avdd-supply:
|
||||
description:
|
||||
Definition of the regulator used as analog supply
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
minimum: 20000
|
||||
|
|
|
|||
|
|
@ -1,107 +0,0 @@
|
|||
Samsung Exynos Analog to Digital Converter bindings
|
||||
|
||||
The devicetree bindings are for the new ADC driver written for
|
||||
Exynos4 and upward SoCs from Samsung.
|
||||
|
||||
New driver handles the following
|
||||
1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
|
||||
and future SoCs from Samsung
|
||||
2. Add ADC driver under iio/adc framework
|
||||
3. Also adds the Documentation for device tree bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "samsung,exynos-adc-v1"
|
||||
for Exynos5250 controllers.
|
||||
Must be "samsung,exynos-adc-v2" for
|
||||
future controllers.
|
||||
Must be "samsung,exynos3250-adc" for
|
||||
controllers compatible with ADC of Exynos3250.
|
||||
Must be "samsung,exynos4212-adc" for
|
||||
controllers compatible with ADC of Exynos4212 and Exynos4412.
|
||||
Must be "samsung,exynos7-adc" for
|
||||
the ADC in Exynos7 and compatibles
|
||||
Must be "samsung,s3c2410-adc" for
|
||||
the ADC in s3c2410 and compatibles
|
||||
Must be "samsung,s3c2416-adc" for
|
||||
the ADC in s3c2416 and compatibles
|
||||
Must be "samsung,s3c2440-adc" for
|
||||
the ADC in s3c2440 and compatibles
|
||||
Must be "samsung,s3c2443-adc" for
|
||||
the ADC in s3c2443 and compatibles
|
||||
Must be "samsung,s3c6410-adc" for
|
||||
the ADC in s3c6410 and compatibles
|
||||
Must be "samsung,s5pv210-adc" for
|
||||
the ADC in s5pv210 and compatibles
|
||||
- reg: List of ADC register address range
|
||||
- The base address and range of ADC register
|
||||
- The base address and range of ADC_PHY register (every
|
||||
SoC except for s3c24xx/s3c64xx ADC)
|
||||
- interrupts: Contains the interrupt information for the timer. The
|
||||
format is being dependent on which interrupt controller
|
||||
the Samsung device uses.
|
||||
- #io-channel-cells = <1>; As ADC has multiple outputs
|
||||
- clocks From common clock bindings: handles to clocks specified
|
||||
in "clock-names" property, in the same order.
|
||||
- clock-names From common clock bindings: list of clock input names
|
||||
used by ADC block:
|
||||
- "adc" : ADC bus clock
|
||||
- "sclk" : ADC special clock (only for Exynos3250 and
|
||||
compatible ADC block)
|
||||
- vdd-supply VDD input supply.
|
||||
|
||||
- samsung,syscon-phandle Contains the PMU system controller node
|
||||
(To access the ADC_PHY register on Exynos5250/5420/5800/3250)
|
||||
Optional properties:
|
||||
- has-touchscreen: If present, indicates that a touchscreen is
|
||||
connected an usable.
|
||||
|
||||
Note: child nodes can be added for auto probing from device tree.
|
||||
|
||||
Example: adding device info in dtsi file
|
||||
|
||||
adc: adc@12d10000 {
|
||||
compatible = "samsung,exynos-adc-v1";
|
||||
reg = <0x12D10000 0x100>;
|
||||
interrupts = <0 106 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&clock 303>;
|
||||
clock-names = "adc";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
||||
Example: adding device info in dtsi file for Exynos3250 with additional sclk
|
||||
|
||||
adc: adc@126c0000 {
|
||||
compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
|
||||
reg = <0x126C0000 0x100>;
|
||||
interrupts = <0 137 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
|
||||
clock-names = "adc", "sclk";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
||||
Example: Adding child nodes in dts file
|
||||
|
||||
adc@12d10000 {
|
||||
|
||||
/* NTC thermistor is a hwmon device */
|
||||
ncp15wb473@0 {
|
||||
compatible = "murata,ncp15wb473";
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <47000>;
|
||||
pulldown-ohm = <0>;
|
||||
io-channels = <&adc 4>;
|
||||
};
|
||||
};
|
||||
|
||||
Note: Does not apply to ADC driver under arch/arm/plat-samsung/
|
||||
Note: The child node can be added under the adc node or separately.
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Analog to Digital Converter (ADC)
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos-adc-v1 # Exynos5250
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
|
||||
- samsung,exynos7-adc
|
||||
- samsung,s3c2410-adc
|
||||
- samsung,s3c2416-adc
|
||||
- samsung,s3c2440-adc
|
||||
- samsung,s3c2443-adc
|
||||
- samsung,s3c6410-adc
|
||||
- samsung,s5pv210-adc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Phandle to ADC bus clock. For Exynos3250 additional clock is needed.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
Must contain clock names (adc, sclk) matching phandles in clocks
|
||||
property.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
vdd-supply: true
|
||||
|
||||
samsung,syscon-phandle:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description:
|
||||
Phandle to the PMU system controller node (to access the ADC_PHY
|
||||
register on Exynos3250/4x12/5250/5420/5800).
|
||||
|
||||
has-touchscreen:
|
||||
description:
|
||||
If present, indicates that a touchscreen is connected and usable.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- "#io-channel-cells"
|
||||
- vdd-supply
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos-adc-v1
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc
|
||||
- samsung,s5pv210-adc
|
||||
then:
|
||||
required:
|
||||
- samsung,syscon-phandle
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos3250-adc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: adc
|
||||
- const: sclk
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: adc
|
||||
|
||||
examples:
|
||||
- |
|
||||
adc: adc@12d10000 {
|
||||
compatible = "samsung,exynos-adc-v1";
|
||||
reg = <0x12d10000 0x100>;
|
||||
interrupts = <0 106 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&clock 303>;
|
||||
clock-names = "adc";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
|
||||
/* NTC thermistor is a hwmon device */
|
||||
ncp15wb473@0 {
|
||||
compatible = "murata,ncp15wb473";
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <47000>;
|
||||
pulldown-ohm = <0>;
|
||||
io-channels = <&adc 4>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
adc@126c0000 {
|
||||
compatible = "samsung,exynos3250-adc";
|
||||
reg = <0x126C0000 0x100>;
|
||||
interrupts = <0 137 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&cmu CLK_TSADC>,
|
||||
<&cmu CLK_SCLK_TSADC>;
|
||||
clock-names = "adc", "sclk";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
};
|
||||
|
|
@ -25,7 +25,6 @@ properties:
|
|||
|
||||
vcc-supply:
|
||||
description: regulator that provides power to the sensor
|
||||
maxItems: 1
|
||||
|
||||
plantower,set-gpios:
|
||||
description: GPIO connected to the SET line
|
||||
|
|
|
|||
|
|
@ -28,12 +28,10 @@ properties:
|
|||
vddd-supply:
|
||||
description:
|
||||
digital voltage regulator (see regulator/regulator.txt)
|
||||
maxItems: 1
|
||||
|
||||
vdda-supply:
|
||||
description:
|
||||
analog voltage regulator (see regulator/regulator.txt)
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
STMicroelectronics STM32 Low-Power Timer Trigger
|
||||
|
||||
STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
|
||||
by STM32 internal ADC and/or DAC.
|
||||
|
||||
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-trigger".
|
||||
- reg: Identify trigger hardware block. Must be 0, 1 or 2
|
||||
respectively for lptimer1, lptimer2 or lptimer3
|
||||
trigger output.
|
||||
|
||||
Example:
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
...
|
||||
trigger@0 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
STMicroelectronics STM32 Timers IIO timer bindings
|
||||
|
||||
Must be a sub-node of an STM32 Timers device tree node.
|
||||
See ../mfd/stm32-timers.txt for details about the parent node.
|
||||
|
||||
Required parameters:
|
||||
- compatible: Must be one of:
|
||||
"st,stm32-timer-trigger"
|
||||
"st,stm32h7-timer-trigger"
|
||||
- reg: Identify trigger hardware block.
|
||||
|
||||
Example:
|
||||
timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 160>;
|
||||
clock-names = "int";
|
||||
|
||||
timer@0 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
Onkey driver for MAX77650 PMIC from Maxim Integrated.
|
||||
|
||||
This module is part of the MAX77650 MFD device. For more details
|
||||
see Documentation/devicetree/bindings/mfd/max77650.txt.
|
||||
|
||||
The onkey controller is represented as a sub-node of the PMIC node on
|
||||
the device tree.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must be "maxim,max77650-onkey".
|
||||
|
||||
Optional properties:
|
||||
- linux,code: The key-code to be reported when the key is pressed.
|
||||
Defaults to KEY_POWER.
|
||||
- maxim,onkey-slide: The system's button is a slide switch, not the default
|
||||
push button.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
onkey {
|
||||
compatible = "maxim,max77650-onkey";
|
||||
linux,code = <KEY_END>;
|
||||
maxim,onkey-slide;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/max77650-onkey.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Onkey driver for MAX77650 PMIC from Maxim Integrated.
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
|
||||
description: |
|
||||
This module is part of the MAX77650 MFD device. For more details
|
||||
see Documentation/devicetree/bindings/mfd/max77650.yaml.
|
||||
|
||||
The onkey controller is represented as a sub-node of the PMIC node on
|
||||
the device tree.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: maxim,max77650-onkey
|
||||
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The key-code to be reported when the key is pressed. Defaults
|
||||
to KEY_POWER.
|
||||
|
||||
maxim,onkey-slide:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The system's button is a slide switch, not the default push button.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
Qualcomm QCS404 Network-On-Chip interconnect driver binding
|
||||
-----------------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
"qcom,qcs404-bimc"
|
||||
"qcom,qcs404-pcnoc"
|
||||
"qcom,qcs404-snoc"
|
||||
- #interconnect-cells : should contain 1
|
||||
|
||||
reg : specifies the physical base address and size of registers
|
||||
clocks : list of phandles and specifiers to all interconnect bus clocks
|
||||
clock-names : clock names should include both "bus" and "bus_a"
|
||||
|
||||
Example:
|
||||
|
||||
soc {
|
||||
...
|
||||
bimc: interconnect@400000 {
|
||||
reg = <0x00400000 0x80000>;
|
||||
compatible = "qcom,qcs404-bimc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
||||
};
|
||||
|
||||
pnoc: interconnect@500000 {
|
||||
reg = <0x00500000 0x15080>;
|
||||
compatible = "qcom,qcs404-pcnoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_PNOC_A_CLK>;
|
||||
};
|
||||
|
||||
snoc: interconnect@580000 {
|
||||
reg = <0x00580000 0x23080>;
|
||||
compatible = "qcom,qcs404-snoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interconnect/qcom,qcs404.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm QCS404 Network-On-Chip interconnect
|
||||
|
||||
maintainers:
|
||||
- Georgi Djakov <georgi.djakov@linaro.org>
|
||||
|
||||
description: |
|
||||
The Qualcomm QCS404 interconnect providers support adjusting the
|
||||
bandwidth requirements between the various NoC fabrics.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs404-bimc
|
||||
- qcom,qcs404-pcnoc
|
||||
- qcom,qcs404-snoc
|
||||
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: bus_a
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Bus A Clock
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#interconnect-cells'
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
bimc: interconnect@400000 {
|
||||
reg = <0x00400000 0x80000>;
|
||||
compatible = "qcom,qcs404-bimc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
||||
};
|
||||
|
||||
pnoc: interconnect@500000 {
|
||||
reg = <0x00500000 0x15080>;
|
||||
compatible = "qcom,qcs404-pcnoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_PNOC_A_CLK>;
|
||||
};
|
||||
|
||||
snoc: interconnect@580000 {
|
||||
reg = <0x00580000 0x23080>;
|
||||
compatible = "qcom,qcs404-snoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
||||
};
|
||||
|
|
@ -52,9 +52,7 @@ required:
|
|||
- interrupts
|
||||
- interrupt-controller
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -138,6 +138,7 @@ properties:
|
|||
containing a set of sub-nodes.
|
||||
patternProperties:
|
||||
"^interrupt-partition-[0-9]+$":
|
||||
type: object
|
||||
properties:
|
||||
affinity:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
|
|
|||
|
|
@ -1,48 +0,0 @@
|
|||
DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be "renesas,irqc-<soctype>" or "renesas,intc-ex-<soctype>",
|
||||
and "renesas,irqc" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,irqc-r8a73a4" (R-Mobile APE6)
|
||||
- "renesas,irqc-r8a7743" (RZ/G1M)
|
||||
- "renesas,irqc-r8a7744" (RZ/G1N)
|
||||
- "renesas,irqc-r8a7745" (RZ/G1E)
|
||||
- "renesas,irqc-r8a77470" (RZ/G1C)
|
||||
- "renesas,irqc-r8a7790" (R-Car H2)
|
||||
- "renesas,irqc-r8a7791" (R-Car M2-W)
|
||||
- "renesas,irqc-r8a7792" (R-Car V2H)
|
||||
- "renesas,irqc-r8a7793" (R-Car M2-N)
|
||||
- "renesas,irqc-r8a7794" (R-Car E2)
|
||||
- "renesas,intc-ex-r8a774a1" (RZ/G2M)
|
||||
- "renesas,intc-ex-r8a774c0" (RZ/G2E)
|
||||
- "renesas,intc-ex-r8a7795" (R-Car H3)
|
||||
- "renesas,intc-ex-r8a7796" (R-Car M3-W)
|
||||
- "renesas,intc-ex-r8a77965" (R-Car M3-N)
|
||||
- "renesas,intc-ex-r8a77970" (R-Car V3M)
|
||||
- "renesas,intc-ex-r8a77980" (R-Car V3H)
|
||||
- "renesas,intc-ex-r8a77990" (R-Car E3)
|
||||
- "renesas,intc-ex-r8a77995" (R-Car D3)
|
||||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
|
||||
interrupts.txt in this directory
|
||||
- clocks: Must contain a reference to the functional clock.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- any properties, listed in interrupts.txt, and any standard resource allocation
|
||||
properties
|
||||
|
||||
Example:
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7790", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,irqc-r8a73a4 # R-Mobile APE6
|
||||
- renesas,irqc-r8a7743 # RZ/G1M
|
||||
- renesas,irqc-r8a7744 # RZ/G1N
|
||||
- renesas,irqc-r8a7745 # RZ/G1E
|
||||
- renesas,irqc-r8a77470 # RZ/G1C
|
||||
- renesas,irqc-r8a7790 # R-Car H2
|
||||
- renesas,irqc-r8a7791 # R-Car M2-W
|
||||
- renesas,irqc-r8a7792 # R-Car V2H
|
||||
- renesas,irqc-r8a7793 # R-Car M2-N
|
||||
- renesas,irqc-r8a7794 # R-Car E2
|
||||
- renesas,intc-ex-r8a774a1 # RZ/G2M
|
||||
- renesas,intc-ex-r8a774b1 # RZ/G2N
|
||||
- renesas,intc-ex-r8a774c0 # RZ/G2E
|
||||
- renesas,intc-ex-r8a7795 # R-Car H3
|
||||
- renesas,intc-ex-r8a7796 # R-Car M3-W
|
||||
- renesas,intc-ex-r8a77965 # R-Car M3-N
|
||||
- renesas,intc-ex-r8a77970 # R-Car V3M
|
||||
- renesas,intc-ex-r8a77980 # R-Car V3H
|
||||
- renesas,intc-ex-r8a77990 # R-Car E3
|
||||
- renesas,intc-ex-r8a77995 # R-Car D3
|
||||
- const: renesas,irqc
|
||||
|
||||
'#interrupt-cells':
|
||||
# an interrupt index and flags, as defined in interrupts.txt in
|
||||
# this directory
|
||||
const: 2
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#interrupt-cells'
|
||||
- interrupt-controller
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc-r8a7790", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
};
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
STM32 External Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be:
|
||||
"st,stm32-exti"
|
||||
"st,stm32h7-exti"
|
||||
"st,stm32mp1-exti"
|
||||
- reg: Specifies base physical address and size of the registers
|
||||
- interrupt-controller: Indentifies the node as an interrupt controller
|
||||
- #interrupt-cells: Specifies the number of cells to encode an interrupt
|
||||
specifier, shall be 2
|
||||
- interrupts: interrupts references to primary interrupt controller
|
||||
(only needed for exti controller with multiple exti under
|
||||
same parent interrupt: st,stm32-exti and st,stm32h7-exti)
|
||||
|
||||
Optional properties:
|
||||
|
||||
- hwlocks: reference to a phandle of a hardware spinlock provider node.
|
||||
|
||||
Example:
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40013C00 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
||||
};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/st,stm32-exti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STM32 External Interrupt Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Alexandre Torgue <alexandre.torgue@st.com>
|
||||
- Ludovic Barre <ludovic.barre@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32-exti
|
||||
- st,stm32h7-exti
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32mp1-exti
|
||||
- const: syscon
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
hwlocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Reference to a phandle of a hardware spinlock provider node.
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Interrupts references to primary interrupt controller
|
||||
|
||||
required:
|
||||
- "#interrupt-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32-exti
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
required:
|
||||
- interrupts
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32h7-exti
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 96
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
//Example 1
|
||||
exti1: interrupt-controller@5000d000 {
|
||||
compatible = "st,stm32mp1-exti", "syscon";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000d000 0x400>;
|
||||
};
|
||||
|
||||
//Example 2
|
||||
exti2: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40013C00 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
* ARM SMMUv3 Architecture Implementation
|
||||
|
||||
The SMMUv3 architecture is a significant departure from previous
|
||||
revisions, replacing the MMIO register interface with in-memory command
|
||||
and event queues and adding support for the ATS and PRI components of
|
||||
the PCIe specification.
|
||||
|
||||
** SMMUv3 required properties:
|
||||
|
||||
- compatible : Should include:
|
||||
|
||||
* "arm,smmu-v3" for any SMMUv3 compliant
|
||||
implementation. This entry should be last in the
|
||||
compatible list.
|
||||
|
||||
- reg : Base address and size of the SMMU.
|
||||
|
||||
- interrupts : Non-secure interrupt list describing the wired
|
||||
interrupt sources corresponding to entries in
|
||||
interrupt-names. If no wired interrupts are
|
||||
present then this property may be omitted.
|
||||
|
||||
- interrupt-names : When the interrupts property is present, should
|
||||
include the following:
|
||||
* "eventq" - Event Queue not empty
|
||||
* "priq" - PRI Queue not empty
|
||||
* "cmdq-sync" - CMD_SYNC complete
|
||||
* "gerror" - Global Error activated
|
||||
* "combined" - The combined interrupt is optional,
|
||||
and should only be provided if the
|
||||
hardware supports just a single,
|
||||
combined interrupt line.
|
||||
If provided, then the combined interrupt
|
||||
will be used in preference to any others.
|
||||
|
||||
- #iommu-cells : See the generic IOMMU binding described in
|
||||
devicetree/bindings/pci/pci-iommu.txt
|
||||
for details. For SMMUv3, must be 1, with each cell
|
||||
describing a single stream ID. All possible stream
|
||||
IDs which a device may emit must be described.
|
||||
|
||||
** SMMUv3 optional properties:
|
||||
|
||||
- dma-coherent : Present if DMA operations made by the SMMU (page
|
||||
table walks, stream table accesses etc) are cache
|
||||
coherent with the CPU.
|
||||
|
||||
NOTE: this only applies to the SMMU itself, not
|
||||
masters connected upstream of the SMMU.
|
||||
|
||||
- msi-parent : See the generic MSI binding described in
|
||||
devicetree/bindings/interrupt-controller/msi.txt
|
||||
for a description of the msi-parent property.
|
||||
|
||||
- hisilicon,broken-prefetch-cmd
|
||||
: Avoid sending CMD_PREFETCH_* commands to the SMMU.
|
||||
|
||||
- cavium,cn9900-broken-page1-regspace
|
||||
: Replaces all page 1 offsets used for EVTQ_PROD/CONS,
|
||||
PRIQ_PROD/CONS register access with page 0 offsets.
|
||||
Set for Cavium ThunderX2 silicon that doesn't support
|
||||
SMMU page1 register space.
|
||||
|
||||
** Example
|
||||
|
||||
smmu@2b400000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x2b400000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
|
||||
dma-coherent;
|
||||
#iommu-cells = <1>;
|
||||
msi-parent = <&its 0xff0000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM SMMUv3 Architecture Implementation
|
||||
|
||||
maintainers:
|
||||
- Will Deacon <will@kernel.org>
|
||||
- Robin Murphy <Robin.Murphy@arm.com>
|
||||
|
||||
description: |+
|
||||
The SMMUv3 architecture is a significant departure from previous
|
||||
revisions, replacing the MMIO register interface with in-memory command
|
||||
and event queues and adding support for the ATS and PRI components of
|
||||
the PCIe specification.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^iommu@[0-9a-f]*"
|
||||
compatible:
|
||||
const: arm,smmu-v3
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
interrupt-names:
|
||||
oneOf:
|
||||
- const: combined
|
||||
description:
|
||||
The combined interrupt is optional, and should only be provided if the
|
||||
hardware supports just a single, combined interrupt line.
|
||||
If provided, then the combined interrupt will be used in preference to
|
||||
any others.
|
||||
- minItems: 2
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: eventq # Event Queue not empty
|
||||
- const: gerror # Global Error activated
|
||||
- const: priq # PRI Queue not empty
|
||||
- const: cmdq-sync # CMD_SYNC complete
|
||||
|
||||
'#iommu-cells':
|
||||
const: 1
|
||||
|
||||
dma-coherent:
|
||||
description: |
|
||||
Present if page table walks made by the SMMU are cache coherent with the
|
||||
CPU.
|
||||
|
||||
NOTE: this only applies to the SMMU itself, not masters connected
|
||||
upstream of the SMMU.
|
||||
|
||||
msi-parent: true
|
||||
|
||||
hisilicon,broken-prefetch-cmd:
|
||||
type: boolean
|
||||
description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
|
||||
|
||||
cavium,cn9900-broken-page1-regspace:
|
||||
type: boolean
|
||||
description:
|
||||
Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
|
||||
register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
|
||||
doesn't support SMMU page1 register space.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#iommu-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |+
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
iommu@2b400000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x2b400000 0x20000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
||||
dma-coherent;
|
||||
#iommu-cells = <1>;
|
||||
msi-parent = <&its 0xff0000>;
|
||||
};
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
* ARM System MMU Architecture Implementation
|
||||
|
||||
ARM SoCs may contain an implementation of the ARM System Memory
|
||||
Management Unit Architecture, which can be used to provide 1 or 2 stages
|
||||
of address translation to bus masters external to the CPU.
|
||||
|
||||
The SMMU may also raise interrupts in response to various fault
|
||||
conditions.
|
||||
|
||||
** System MMU required properties:
|
||||
|
||||
- compatible : Should be one of:
|
||||
|
||||
"arm,smmu-v1"
|
||||
"arm,smmu-v2"
|
||||
"arm,mmu-400"
|
||||
"arm,mmu-401"
|
||||
"arm,mmu-500"
|
||||
"cavium,smmu-v2"
|
||||
"qcom,smmu-v2"
|
||||
|
||||
depending on the particular implementation and/or the
|
||||
version of the architecture implemented.
|
||||
|
||||
Qcom SoCs must contain, as below, SoC-specific compatibles
|
||||
along with "qcom,smmu-v2":
|
||||
"qcom,msm8996-smmu-v2", "qcom,smmu-v2",
|
||||
"qcom,sdm845-smmu-v2", "qcom,smmu-v2".
|
||||
|
||||
Qcom SoCs implementing "arm,mmu-500" must also include,
|
||||
as below, SoC-specific compatibles:
|
||||
"qcom,sdm845-smmu-500", "arm,mmu-500"
|
||||
|
||||
- reg : Base address and size of the SMMU.
|
||||
|
||||
- #global-interrupts : The number of global interrupts exposed by the
|
||||
device.
|
||||
|
||||
- interrupts : Interrupt list, with the first #global-irqs entries
|
||||
corresponding to the global interrupts and any
|
||||
following entries corresponding to context interrupts,
|
||||
specified in order of their indexing by the SMMU.
|
||||
|
||||
For SMMUv2 implementations, there must be exactly one
|
||||
interrupt per context bank. In the case of a single,
|
||||
combined interrupt, it must be listed multiple times.
|
||||
|
||||
- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
|
||||
for details. With a value of 1, each IOMMU specifier
|
||||
represents a distinct stream ID emitted by that device
|
||||
into the relevant SMMU.
|
||||
|
||||
SMMUs with stream matching support and complex masters
|
||||
may use a value of 2, where the second cell of the
|
||||
IOMMU specifier represents an SMR mask to combine with
|
||||
the ID in the first cell. Care must be taken to ensure
|
||||
the set of matched IDs does not result in conflicts.
|
||||
|
||||
** System MMU optional properties:
|
||||
|
||||
- dma-coherent : Present if page table walks made by the SMMU are
|
||||
cache coherent with the CPU.
|
||||
|
||||
NOTE: this only applies to the SMMU itself, not
|
||||
masters connected upstream of the SMMU.
|
||||
|
||||
- calxeda,smmu-secure-config-access : Enable proper handling of buggy
|
||||
implementations that always use secure access to
|
||||
SMMU configuration registers. In this case non-secure
|
||||
aliases of secure registers have to be used during
|
||||
SMMU configuration.
|
||||
|
||||
- stream-match-mask : For SMMUs supporting stream matching and using
|
||||
#iommu-cells = <1>, specifies a mask of bits to ignore
|
||||
when matching stream IDs (e.g. this may be programmed
|
||||
into the SMRn.MASK field of every stream match register
|
||||
used). For cases where it is desirable to ignore some
|
||||
portion of every Stream ID (e.g. for certain MMU-500
|
||||
configurations given globally unique input IDs). This
|
||||
property is not valid for SMMUs using stream indexing,
|
||||
or using stream matching with #iommu-cells = <2>, and
|
||||
may be ignored if present in such cases.
|
||||
|
||||
- clock-names: List of the names of clocks input to the device. The
|
||||
required list depends on particular implementation and
|
||||
is as follows:
|
||||
- for "qcom,smmu-v2":
|
||||
- "bus": clock required for downstream bus access and
|
||||
for the smmu ptw,
|
||||
- "iface": clock required to access smmu's registers
|
||||
through the TCU's programming interface.
|
||||
- unspecified for other implementations.
|
||||
|
||||
- clocks: Specifiers for all clocks listed in the clock-names property,
|
||||
as per generic clock bindings.
|
||||
|
||||
- power-domains: Specifiers for power domains required to be powered on for
|
||||
the SMMU to operate, as per generic power domain bindings.
|
||||
|
||||
** Deprecated properties:
|
||||
|
||||
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
|
||||
A list of phandles to device nodes representing bus
|
||||
masters for which the SMMU can provide a translation
|
||||
and their corresponding Stream IDs. Each device node
|
||||
linked from this list must have a "#stream-id-cells"
|
||||
property, indicating the number of Stream ID
|
||||
arguments associated with its phandle.
|
||||
|
||||
** Examples:
|
||||
|
||||
/* SMMU with stream matching or stream indexing */
|
||||
smmu1: iommu {
|
||||
compatible = "arm,smmu-v1";
|
||||
reg = <0xba5e0000 0x10000>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <0 32 4>,
|
||||
<0 33 4>,
|
||||
<0 34 4>, /* This is the first context interrupt */
|
||||
<0 35 4>,
|
||||
<0 36 4>,
|
||||
<0 37 4>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
/* device with two stream IDs, 0 and 7 */
|
||||
master1 {
|
||||
iommus = <&smmu1 0>,
|
||||
<&smmu1 7>;
|
||||
};
|
||||
|
||||
|
||||
/* SMMU with stream matching */
|
||||
smmu2: iommu {
|
||||
...
|
||||
#iommu-cells = <2>;
|
||||
};
|
||||
|
||||
/* device with stream IDs 0 and 7 */
|
||||
master2 {
|
||||
iommus = <&smmu2 0 0>,
|
||||
<&smmu2 7 0>;
|
||||
};
|
||||
|
||||
/* device with stream IDs 1, 17, 33 and 49 */
|
||||
master3 {
|
||||
iommus = <&smmu2 1 0x30>;
|
||||
};
|
||||
|
||||
|
||||
/* ARM MMU-500 with 10-bit stream ID input configuration */
|
||||
smmu3: iommu {
|
||||
compatible = "arm,mmu-500", "arm,smmu-v2";
|
||||
...
|
||||
#iommu-cells = <1>;
|
||||
/* always ignore appended 5-bit TBU number */
|
||||
stream-match-mask = 0x7c00;
|
||||
};
|
||||
|
||||
bus {
|
||||
/* bus whose child devices emit one unique 10-bit stream
|
||||
ID each, but may master through multiple SMMU TBUs */
|
||||
iommu-map = <0 &smmu3 0 0x400>;
|
||||
...
|
||||
};
|
||||
|
||||
/* Qcom's arm,smmu-v2 implementation */
|
||||
smmu4: iommu@d00000 {
|
||||
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0xd00000 0x10000>;
|
||||
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&mmcc SMMU_MDP_AXI_CLK>,
|
||||
<&mmcc SMMU_MDP_AHB_CLK>;
|
||||
clock-names = "bus", "iface";
|
||||
};
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM System MMU Architecture Implementation
|
||||
|
||||
maintainers:
|
||||
- Will Deacon <will@kernel.org>
|
||||
- Robin Murphy <Robin.Murphy@arm.com>
|
||||
|
||||
description: |+
|
||||
ARM SoCs may contain an implementation of the ARM System Memory
|
||||
Management Unit Architecture, which can be used to provide 1 or 2 stages
|
||||
of address translation to bus masters external to the CPU.
|
||||
|
||||
The SMMU may also raise interrupts in response to various fault
|
||||
conditions.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^iommu@[0-9a-f]*"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Qcom SoCs implementing "arm,smmu-v2"
|
||||
items:
|
||||
- enum:
|
||||
- qcom,msm8996-smmu-v2
|
||||
- qcom,msm8998-smmu-v2
|
||||
- qcom,sdm845-smmu-v2
|
||||
- const: qcom,smmu-v2
|
||||
|
||||
- description: Qcom SoCs implementing "arm,mmu-500"
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sc7180-smmu-500
|
||||
- qcom,sdm845-smmu-500
|
||||
- const: arm,mmu-500
|
||||
- items:
|
||||
- const: arm,mmu-500
|
||||
- const: arm,smmu-v2
|
||||
- items:
|
||||
- const: arm,mmu-401
|
||||
- const: arm,smmu-v1
|
||||
- enum:
|
||||
- arm,smmu-v1
|
||||
- arm,smmu-v2
|
||||
- arm,mmu-400
|
||||
- arm,mmu-401
|
||||
- arm,mmu-500
|
||||
- cavium,smmu-v2
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#global-interrupts':
|
||||
description: The number of global interrupts exposed by the device.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
|
||||
|
||||
'#iommu-cells':
|
||||
enum: [ 1, 2 ]
|
||||
description: |
|
||||
See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
|
||||
value of 1, each IOMMU specifier represents a distinct stream ID emitted
|
||||
by that device into the relevant SMMU.
|
||||
|
||||
SMMUs with stream matching support and complex masters may use a value of
|
||||
2, where the second cell of the IOMMU specifier represents an SMR mask to
|
||||
combine with the ID in the first cell. Care must be taken to ensure the
|
||||
set of matched IDs does not result in conflicts.
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 388 # 260 plus 128 contexts
|
||||
description: |
|
||||
Interrupt list, with the first #global-interrupts entries corresponding to
|
||||
the global interrupts and any following entries corresponding to context
|
||||
interrupts, specified in order of their indexing by the SMMU.
|
||||
|
||||
For SMMUv2 implementations, there must be exactly one interrupt per
|
||||
context bank. In the case of a single, combined interrupt, it must be
|
||||
listed multiple times.
|
||||
|
||||
dma-coherent:
|
||||
description: |
|
||||
Present if page table walks made by the SMMU are cache coherent with the
|
||||
CPU.
|
||||
|
||||
NOTE: this only applies to the SMMU itself, not masters connected
|
||||
upstream of the SMMU.
|
||||
|
||||
calxeda,smmu-secure-config-access:
|
||||
type: boolean
|
||||
description:
|
||||
Enable proper handling of buggy implementations that always use secure
|
||||
access to SMMU configuration registers. In this case non-secure aliases of
|
||||
secure registers have to be used during SMMU configuration.
|
||||
|
||||
stream-match-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
For SMMUs supporting stream matching and using #iommu-cells = <1>,
|
||||
specifies a mask of bits to ignore when matching stream IDs (e.g. this may
|
||||
be programmed into the SMRn.MASK field of every stream match register
|
||||
used). For cases where it is desirable to ignore some portion of every
|
||||
Stream ID (e.g. for certain MMU-500 configurations given globally unique
|
||||
input IDs). This property is not valid for SMMUs using stream indexing, or
|
||||
using stream matching with #iommu-cells = <2>, and may be ignored if
|
||||
present in such cases.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: bus clock required for downstream bus access and for the
|
||||
smmu ptw
|
||||
- description: interface clock required to access smmu's registers
|
||||
through the TCU's programming interface.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#global-interrupts'
|
||||
- '#iommu-cells'
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |+
|
||||
/* SMMU with stream matching or stream indexing */
|
||||
smmu1: iommu@ba5e0000 {
|
||||
compatible = "arm,smmu-v1";
|
||||
reg = <0xba5e0000 0x10000>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <0 32 4>,
|
||||
<0 33 4>,
|
||||
<0 34 4>, /* This is the first context interrupt */
|
||||
<0 35 4>,
|
||||
<0 36 4>,
|
||||
<0 37 4>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
/* device with two stream IDs, 0 and 7 */
|
||||
master1 {
|
||||
iommus = <&smmu1 0>,
|
||||
<&smmu1 7>;
|
||||
};
|
||||
|
||||
|
||||
/* SMMU with stream matching */
|
||||
smmu2: iommu@ba5f0000 {
|
||||
compatible = "arm,smmu-v1";
|
||||
reg = <0xba5f0000 0x10000>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <0 38 4>,
|
||||
<0 39 4>,
|
||||
<0 40 4>, /* This is the first context interrupt */
|
||||
<0 41 4>,
|
||||
<0 42 4>,
|
||||
<0 43 4>;
|
||||
#iommu-cells = <2>;
|
||||
};
|
||||
|
||||
/* device with stream IDs 0 and 7 */
|
||||
master2 {
|
||||
iommus = <&smmu2 0 0>,
|
||||
<&smmu2 7 0>;
|
||||
};
|
||||
|
||||
/* device with stream IDs 1, 17, 33 and 49 */
|
||||
master3 {
|
||||
iommus = <&smmu2 1 0x30>;
|
||||
};
|
||||
|
||||
|
||||
/* ARM MMU-500 with 10-bit stream ID input configuration */
|
||||
smmu3: iommu@ba600000 {
|
||||
compatible = "arm,mmu-500", "arm,smmu-v2";
|
||||
reg = <0xba600000 0x10000>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <0 44 4>,
|
||||
<0 45 4>,
|
||||
<0 46 4>, /* This is the first context interrupt */
|
||||
<0 47 4>,
|
||||
<0 48 4>,
|
||||
<0 49 4>;
|
||||
#iommu-cells = <1>;
|
||||
/* always ignore appended 5-bit TBU number */
|
||||
stream-match-mask = <0x7c00>;
|
||||
};
|
||||
|
||||
bus {
|
||||
/* bus whose child devices emit one unique 10-bit stream
|
||||
ID each, but may master through multiple SMMU TBUs */
|
||||
iommu-map = <0 &smmu3 0 0x400>;
|
||||
|
||||
|
||||
};
|
||||
|
||||
- |+
|
||||
/* Qcom's arm,smmu-v2 implementation */
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
smmu4: iommu@d00000 {
|
||||
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0xd00000 0x10000>;
|
||||
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
power-domains = <&mmcc 0>;
|
||||
|
||||
clocks = <&mmcc 123>,
|
||||
<&mmcc 124>;
|
||||
clock-names = "bus", "iface";
|
||||
};
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
|
||||
|
||||
Samsung's Exynos architecture contains System MMUs that enables scattered
|
||||
physical memory chunks visible as a contiguous region to DMA-capable peripheral
|
||||
devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
|
||||
|
||||
System MMU is an IOMMU and supports identical translation table format to
|
||||
ARMv7 translation tables with minimum set of page properties including access
|
||||
permissions, shareability and security protection. In addition, System MMU has
|
||||
another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
||||
latency.
|
||||
|
||||
System MMUs are in many to one relation with peripheral devices, i.e. single
|
||||
peripheral device might have multiple System MMUs (usually one for each bus
|
||||
master), but one System MMU can handle transactions from only one peripheral
|
||||
device. The relation between a System MMU and the peripheral device needs to be
|
||||
defined in device node of the peripheral device.
|
||||
|
||||
MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
|
||||
MMUs.
|
||||
* MFC has one System MMU on its left and right bus.
|
||||
* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
|
||||
for window 1, 2 and 3.
|
||||
* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
|
||||
the other System MMU on the write channel.
|
||||
|
||||
For information on assigning System MMU controller to its peripheral devices,
|
||||
see generic IOMMU bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,exynos-sysmmu"
|
||||
- reg: A tuple of base address and size of System MMU registers.
|
||||
- #iommu-cells: Should be <0>.
|
||||
- interrupts: An interrupt specifier for interrupt signal of System MMU,
|
||||
according to the format defined by a particular interrupt
|
||||
controller.
|
||||
- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
|
||||
SYSMMU core clocks.
|
||||
Optional "master" if the clock to the System MMU is gated by
|
||||
another gate clock other core (usually main gate clock
|
||||
of peripheral device this SYSMMU belongs to).
|
||||
- clocks: Phandles for respective clocks described by clock-names.
|
||||
- power-domains: Required if the System MMU is needed to gate its power.
|
||||
Please refer to the following document:
|
||||
Documentation/devicetree/bindings/power/pd-samsung.txt
|
||||
|
||||
Examples:
|
||||
gsc_0: gsc@13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
power-domains = <&pd_gsc>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
iommus = <&sysmmu_gsc0>;
|
||||
};
|
||||
|
||||
sysmmu_gsc0: sysmmu@13e80000 {
|
||||
compatible = "samsung,exynos-sysmmu";
|
||||
reg = <0x13E80000 0x1000>;
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <2 0>;
|
||||
clock-names = "sysmmu", "master";
|
||||
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
|
||||
power-domains = <&pd_gsc>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
|
||||
|
||||
maintainers:
|
||||
- Marek Szyprowski <m.szyprowski@samsung.com>
|
||||
|
||||
description: |+
|
||||
Samsung's Exynos architecture contains System MMUs that enables scattered
|
||||
physical memory chunks visible as a contiguous region to DMA-capable peripheral
|
||||
devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
|
||||
|
||||
System MMU is an IOMMU and supports identical translation table format to
|
||||
ARMv7 translation tables with minimum set of page properties including access
|
||||
permissions, shareability and security protection. In addition, System MMU has
|
||||
another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
||||
latency.
|
||||
|
||||
System MMUs are in many to one relation with peripheral devices, i.e. single
|
||||
peripheral device might have multiple System MMUs (usually one for each bus
|
||||
master), but one System MMU can handle transactions from only one peripheral
|
||||
device. The relation between a System MMU and the peripheral device needs to be
|
||||
defined in device node of the peripheral device.
|
||||
|
||||
MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
|
||||
MMUs.
|
||||
* MFC has one System MMU on its left and right bus.
|
||||
* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
|
||||
for window 1, 2 and 3.
|
||||
* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
|
||||
the other System MMU on the write channel.
|
||||
|
||||
For information on assigning System MMU controller to its peripheral devices,
|
||||
see generic IOMMU bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: samsung,exynos-sysmmu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: sysmmu
|
||||
- items:
|
||||
- const: sysmmu
|
||||
- const: master
|
||||
- items:
|
||||
- const: aclk
|
||||
- const: pclk
|
||||
|
||||
"#iommu-cells":
|
||||
const: 0
|
||||
|
||||
power-domains:
|
||||
description: |
|
||||
Required if the System MMU is needed to gate its power.
|
||||
Please refer to the following document:
|
||||
Documentation/devicetree/bindings/power/pd-samsung.yaml
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#iommu-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
|
||||
gsc_0: scaler@13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
power-domains = <&pd_gsc>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
iommus = <&sysmmu_gsc0>;
|
||||
};
|
||||
|
||||
sysmmu_gsc0: iommu@13e80000 {
|
||||
compatible = "samsung,exynos-sysmmu";
|
||||
reg = <0x13E80000 0x1000>;
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <2 0>;
|
||||
clock-names = "sysmmu", "master";
|
||||
clocks = <&clock CLK_SMMU_GSCL0>,
|
||||
<&clock CLK_GSCL0>;
|
||||
power-domains = <&pd_gsc>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
LED driver for MAX77650 PMIC from Maxim Integrated.
|
||||
|
||||
This module is part of the MAX77650 MFD device. For more details
|
||||
see Documentation/devicetree/bindings/mfd/max77650.txt.
|
||||
|
||||
The LED controller is represented as a sub-node of the PMIC node on
|
||||
the device tree.
|
||||
|
||||
This device has three current sinks.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must be "maxim,max77650-led"
|
||||
- #address-cells: Must be <1>.
|
||||
- #size-cells: Must be <0>.
|
||||
|
||||
Each LED is represented as a sub-node of the LED-controller node. Up to
|
||||
three sub-nodes can be defined.
|
||||
|
||||
Required properties of the sub-node:
|
||||
------------------------------------
|
||||
|
||||
- reg: Must be <0>, <1> or <2>.
|
||||
|
||||
Optional properties of the sub-node:
|
||||
------------------------------------
|
||||
|
||||
- label: See Documentation/devicetree/bindings/leds/common.txt
|
||||
- linux,default-trigger: See Documentation/devicetree/bindings/leds/common.txt
|
||||
|
||||
For more details, please refer to the generic GPIO DT binding document
|
||||
<devicetree/bindings/gpio/gpio.txt>.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
leds {
|
||||
compatible = "maxim,max77650-led";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
label = "blue:usr0";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
label = "red:usr1";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
label = "green:usr2";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/leds/leds-max77650.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LED driver for MAX77650 PMIC from Maxim Integrated.
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
|
||||
description: |
|
||||
This module is part of the MAX77650 MFD device. For more details
|
||||
see Documentation/devicetree/bindings/mfd/max77650.yaml.
|
||||
|
||||
The LED controller is represented as a sub-node of the PMIC node on
|
||||
the device tree.
|
||||
|
||||
This device has three current sinks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: maxim,max77650-led
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^led@[0-2]$":
|
||||
type: object
|
||||
description: |
|
||||
Properties for a single LED.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description:
|
||||
Index of the LED.
|
||||
minimum: 0
|
||||
maximum: 2
|
||||
|
||||
label: true
|
||||
|
||||
linux,default-trigger: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: STMicroelectronics STM32 IPC controller bindings
|
||||
|
||||
description:
|
||||
The IPCC block provides a non blocking signaling mechanism to post and
|
||||
retrieve messages in an atomic way between two processors.
|
||||
It provides the signaling for N bidirectionnal channels. The number of
|
||||
channels (N) can be read from a dedicated register.
|
||||
|
||||
maintainers:
|
||||
- Fabien Dessenne <fabien.dessenne@st.com>
|
||||
- Arnaud Pouliquen <arnaud.pouliquen@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp1-ipcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: rx channel occupied
|
||||
- description: tx channel free
|
||||
- description: wakeup source
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
- const: wakeup
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
"#mbox-cells":
|
||||
const: 1
|
||||
|
||||
st,proc-id:
|
||||
description: Processor id using the mailbox (0 or 1)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- st,proc-id
|
||||
- clocks
|
||||
- interrupt-names
|
||||
- "#mbox-cells"
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
ipcc: mailbox@4c001000 {
|
||||
compatible = "st,stm32mp1-ipcc";
|
||||
#mbox-cells = <1>;
|
||||
reg = <0x4c001000 0x400>;
|
||||
st,proc-id = <0>;
|
||||
interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
|
||||
<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
|
||||
<&aiec 62 1>;
|
||||
interrupt-names = "rx", "tx", "wakeup";
|
||||
clocks = <&rcc_clk IPCC>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
|
||||
|
||||
The IPCC block provides a non blocking signaling mechanism to post and
|
||||
retrieve messages in an atomic way between two processors.
|
||||
It provides the signaling for N bidirectionnal channels. The number of channels
|
||||
(N) can be read from a dedicated register.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32mp1-ipcc"
|
||||
- reg: Register address range (base address and length)
|
||||
- st,proc-id: Processor id using the mailbox (0 or 1)
|
||||
- clocks: Input clock
|
||||
- interrupt-names: List of names for the interrupts described by the interrupt
|
||||
property. Must contain the following entries:
|
||||
- "rx"
|
||||
- "tx"
|
||||
- "wakeup"
|
||||
- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
|
||||
free" and "system wakeup".
|
||||
- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
|
||||
The data contained in the mbox specifier of the "mboxes"
|
||||
property in the client node is the mailbox channel index.
|
||||
|
||||
Optional properties:
|
||||
- wakeup-source: Flag to indicate whether this device can wake up the system
|
||||
|
||||
|
||||
|
||||
Example:
|
||||
ipcc: mailbox@4c001000 {
|
||||
compatible = "st,stm32mp1-ipcc";
|
||||
#mbox-cells = <1>;
|
||||
reg = <0x4c001000 0x400>;
|
||||
st,proc-id = <0>;
|
||||
interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
|
||||
<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
|
||||
<&aiec 62 1>;
|
||||
interrupt-names = "rx", "tx", "wakeup";
|
||||
clocks = <&rcc_clk IPCC>;
|
||||
wakeup-source;
|
||||
}
|
||||
|
||||
Client:
|
||||
mbox_test {
|
||||
...
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>;
|
||||
};
|
||||
|
|
@ -60,9 +60,7 @@ required:
|
|||
- clocks
|
||||
- clock-names
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,91 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/media/amlogic,meson-gx-ao-cec.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Amlogic Meson AO-CEC Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
description: |
|
||||
The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
|
||||
to handle communication between HDMI connected devices over the CEC bus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gx-ao-cec # GXBB, GXL, GXM, G12A and SM1 AO_CEC_A module
|
||||
- amlogic,meson-g12a-ao-cec # G12A AO_CEC_B module
|
||||
- amlogic,meson-sm1-ao-cec # SM1 AO_CEC_B module
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
hdmi-phandle:
|
||||
description: phandle to the HDMI controller
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- amlogic,meson-gx-ao-cec
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: AO-CEC clock
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
items:
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- amlogic,meson-g12a-ao-cec
|
||||
- amlogic,meson-sm1-ao-cec
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: AO-CEC clock generator source
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
items:
|
||||
- const: oscin
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- hdmi-phandle
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
cec_AO: cec@100 {
|
||||
compatible = "amlogic,meson-gx-ao-cec";
|
||||
reg = <0x0 0x00100 0x0 0x14>;
|
||||
interrupts = <199>;
|
||||
clocks = <&clkc_cec>;
|
||||
clock-names = "core";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue