ARM: dts: aspeed: Add AST2600 and EVB
The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7 CPU and shares many periperhals with the existing AST2400 and AST2500. Link: https://lore.kernel.org/r/20190911165614.31641-1-joel@jms.id.au Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>alistair/sunxi64-5.4-dsi
Joel Stanley
Arnd Bergmann
parent
4e53a92cdd
commit
2ca5646b5c
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@ -1268,6 +1268,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-ast2500-evb.dtb \
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aspeed-ast2600-evb.dtb \
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aspeed-bmc-arm-centriq2400-rep.dtb \
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aspeed-bmc-arm-stardragon4800-rep2.dtb \
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aspeed-bmc-facebook-cmm.dtb \
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@ -0,0 +1,80 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright 2019 IBM Corp.
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/dts-v1/;
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#include "aspeed-g6.dtsi"
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/ {
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model = "AST2600 EVB";
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compatible = "aspeed,ast2600";
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aliases {
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serial4 = &uart5;
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};
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chosen {
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bootargs = "console=ttyS4,115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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};
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&mdio1 {
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status = "okay";
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ethphy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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&mdio2 {
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status = "okay";
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ethphy2: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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&mdio3 {
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status = "okay";
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ethphy3: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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};
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&mac1 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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};
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&mac2 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <ðphy2>;
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};
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&mac3 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <ðphy3>;
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};
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&emmc {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright 2019 IBM Corp.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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/ {
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model = "Aspeed BMC";
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compatible = "aspeed,ast2600";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial4 = &uart5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "aspeed,ast2600-smp";
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cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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};
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cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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clocks = <&syscon ASPEED_CLK_HPLL>;
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arm,cpu-registers-not-fw-configured;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges;
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gic: interrupt-controller@40461000 {
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compatible = "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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reg = <0x40461000 0x1000>,
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<0x40462000 0x1000>,
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<0x40464000 0x2000>,
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<0x40466000 0x2000>;
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};
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mdio0: mdio@1e650000 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650000 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mdio1: mdio@1e650008 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650008 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mdio2: mdio@1e650010 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650010 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mdio3: mdio@1e650018 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650018 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mac0: ftgmac@1e660000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e660000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
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status = "disabled";
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};
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mac1: ftgmac@1e680000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e680000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
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status = "disabled";
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};
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mac2: ftgmac@1e670000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e670000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
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status = "disabled";
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};
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mac3: ftgmac@1e690000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e690000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@1e6e2000 {
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compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1000>;
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ranges = <0 0x1e6e2000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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pinctrl: pinctrl {
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compatible = "aspeed,ast2600-pinctrl";
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};
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smp-memram@180 {
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compatible = "aspeed,ast2600-smpmem";
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reg = <0x180 0x40>;
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};
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};
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rng: hwrng@1e6e2524 {
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compatible = "timeriomem_rng";
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reg = <0x1e6e2524 0x4>;
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period = <1>;
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quality = <100>;
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};
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rtc: rtc@1e781000 {
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compatible = "aspeed,ast2600-rtc";
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reg = <0x1e781000 0x18>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart5: serial@1e784000 {
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compatible = "ns16550a";
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reg = <0x1e784000 0x1000>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
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no-loopback-test;
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};
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wdt1: watchdog@1e785000 {
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compatible = "aspeed,ast2600-wdt";
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reg = <0x1e785000 0x40>;
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};
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wdt2: watchdog@1e785040 {
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compatible = "aspeed,ast2600-wdt";
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reg = <0x1e785040 0x40>;
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status = "disabled";
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};
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wdt3: watchdog@1e785080 {
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compatible = "aspeed,ast2600-wdt";
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reg = <0x1e785080 0x40>;
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status = "disabled";
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};
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wdt4: watchdog@1e7850C0 {
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compatible = "aspeed,ast2600-wdt";
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reg = <0x1e7850C0 0x40>;
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status = "disabled";
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};
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sdc: sdc@1e740000 {
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compatible = "aspeed,ast2600-sd-controller";
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reg = <0x1e740000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1e740000 0x10000>;
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clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
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status = "disabled";
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sdhci0: sdhci@1e740100 {
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compatible = "aspeed,ast2600-sdhci", "sdhci";
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reg = <0x100 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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sdhci,auto-cmd12;
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clocks = <&syscon ASPEED_CLK_SDIO>;
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status = "disabled";
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};
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sdhci1: sdhci@1e740200 {
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compatible = "aspeed,ast2600-sdhci", "sdhci";
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reg = <0x200 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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sdhci,auto-cmd12;
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clocks = <&syscon ASPEED_CLK_SDIO>;
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status = "disabled";
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};
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};
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emmc: sdc@1e750000 {
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compatible = "aspeed,ast2600-sd-controller";
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reg = <0x1e750000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1e750000 0x10000>;
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clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
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status = "disabled";
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sdhci@1e750100 {
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compatible = "aspeed,ast2600-sdhci";
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reg = <0x100 0x100>;
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sdhci,auto-cmd12;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_EMMC>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc_default>;
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};
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};
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};
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};
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};
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&pinctrl {
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pinctrl_emmc_default: emmc_default {
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function = "SD3";
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groups = "SD3";
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};
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};
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