drm/nouveau/kms/nv50: handle SetControlOutputResource from head
Removes duplicated code from OR-specific functions. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>hifive-unleashed-5.1
Ben Skeggs
parent
10ffe0fad5
commit
2ca7fb5c1c
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@ -194,6 +194,12 @@ struct nv50_head_atom {
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} sat;
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} procamp;
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struct {
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u8 nhsync:1;
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u8 nvsync:1;
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u8 depth:4;
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} or;
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union {
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struct {
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bool ilut:1;
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@ -214,6 +220,7 @@ struct nv50_head_atom {
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bool ovly:1;
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bool dither:1;
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bool procamp:1;
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bool or:1;
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};
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u16 mask;
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} set;
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@ -457,6 +464,7 @@ struct nv50_head_func {
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void (*ovly)(struct nv50_head *, struct nv50_head_atom *);
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void (*dither)(struct nv50_head *, struct nv50_head_atom *);
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void (*procamp)(struct nv50_head *, struct nv50_head_atom *);
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void (*or)(struct nv50_head *, struct nv50_head_atom *);
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};
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#define nv50_head(c) container_of((c), struct nv50_head, base.base)
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@ -1627,6 +1635,23 @@ nv50_base_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)
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/******************************************************************************
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* Head
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*****************************************************************************/
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static void
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head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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u32 *push;
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if (core->base.user.oclass >= GF110_DISP_CORE_CHANNEL_DMA &&
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(push = evo_wait(core, 2))) {
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evo_mthd(push, 0x0404 + (head->base.index * 0x300), 2);
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evo_data(push, 0x00000001 | (asyh->or.depth << 6) |
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(asyh->or.nvsync << 4) |
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(asyh->or.nhsync << 3));
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evo_data(push, 0x31ec6000 | (head->base.index << 25) |
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asyh->mode.interlace);
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evo_kick(push, core);
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}
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}
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static void
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nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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@ -2033,6 +2058,7 @@ head507d = {
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.ovly = nv50_head_ovly,
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.dither = nv50_head_dither,
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.procamp = nv50_head_procamp,
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.or = head907d_or,
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};
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static void
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@ -2066,6 +2092,7 @@ nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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if (asyh->set.ovly ) head->func->ovly (head, asyh);
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if (asyh->set.dither ) head->func->dither (head, asyh);
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if (asyh->set.procamp) head->func->procamp (head, asyh);
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if (asyh->set.or ) head->func->or (head, asyh);
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}
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static void
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@ -2268,6 +2295,9 @@ nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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}
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m->clock = mode->crtc_clock;
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asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
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asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
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asyh->set.or = head->func->or != NULL;
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asyh->set.mode = true;
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}
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@ -2304,6 +2334,7 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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if (asyc)
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asyc->set.mask = ~0;
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asyh->set.mask = ~0;
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asyh->set.or = head->func->or != NULL;
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}
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if (asyh->state.mode_changed)
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@ -2707,7 +2738,7 @@ nv50_dac_enable(struct drm_encoder *encoder)
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struct nv50_dmac *core = &nv50_disp(encoder->dev)->core->chan;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
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struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
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u32 *push;
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nv50_outp_acquire(nv_encoder);
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@ -2715,37 +2746,17 @@ nv50_dac_enable(struct drm_encoder *encoder)
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push = evo_wait(core, 8);
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if (push) {
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
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u32 syncs = 0x00000000;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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syncs |= 0x00000001;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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syncs |= 0x00000002;
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evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
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evo_data(push, 1 << nv_crtc->index);
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evo_data(push, syncs);
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evo_data(push, (asyh->or.nvsync << 1) | asyh->or.nhsync);
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} else {
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u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
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u32 syncs = 0x00000001;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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syncs |= 0x00000008;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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syncs |= 0x00000010;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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magic |= 0x00000001;
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evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
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evo_data(push, syncs);
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evo_data(push, magic);
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evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
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evo_data(push, 1 << nv_crtc->index);
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}
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evo_kick(push, core);
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}
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asyh->or.depth = 0;
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nv_encoder->crtc = encoder->crtc;
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}
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@ -3144,7 +3155,7 @@ nv50_msto_enable(struct drm_encoder *encoder)
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}
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mstm->outp->update(mstm->outp, head->base.index,
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&head->base.base.state->adjusted_mode, proto, depth);
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nv50_head_atom(head->base.base.state), proto, depth);
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msto->head = head;
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msto->mstc = mstc;
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@ -3612,46 +3623,31 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
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*****************************************************************************/
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static void
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nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
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struct drm_display_mode *mode, u8 proto, u8 depth)
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struct nv50_head_atom *asyh, u8 proto, u8 depth)
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{
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struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
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struct nv50_dmac *core = &disp->core->chan;
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u32 *push;
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if (!mode) {
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if (!asyh) {
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nv_encoder->ctrl &= ~BIT(head);
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if (!(nv_encoder->ctrl & 0x0000000f))
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nv_encoder->ctrl = 0;
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} else {
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nv_encoder->ctrl |= proto << 8;
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nv_encoder->ctrl |= BIT(head);
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asyh->or.depth = depth;
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}
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if ((push = evo_wait(core, 6))) {
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
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if (mode) {
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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nv_encoder->ctrl |= 0x00001000;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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nv_encoder->ctrl |= 0x00002000;
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nv_encoder->ctrl |= depth << 16;
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if (asyh) {
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nv_encoder->ctrl |= asyh->or.depth << 16 |
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asyh->or.nvsync << 13 |
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asyh->or.nhsync << 12;
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}
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evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
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} else {
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if (mode) {
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u32 magic = 0x31ec6000 | (head << 25);
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u32 syncs = 0x00000001;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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syncs |= 0x00000008;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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syncs |= 0x00000010;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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magic |= 0x00000001;
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evo_mthd(push, 0x0404 + (head * 0x300), 2);
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evo_data(push, syncs | (depth << 6));
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evo_data(push, magic);
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}
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evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
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}
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evo_data(push, nv_encoder->ctrl);
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@ -3692,7 +3688,8 @@ nv50_sor_enable(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
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struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
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struct drm_display_mode *mode = &asyh->state.adjusted_mode;
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struct {
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struct nv50_disp_mthd_v1 base;
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struct nv50_disp_sor_lvds_script_v0 lvds;
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@ -3786,7 +3783,7 @@ nv50_sor_enable(struct drm_encoder *encoder)
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break;
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}
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nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
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nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
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}
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static const struct drm_encoder_helper_funcs
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@ -3924,19 +3921,19 @@ nv50_pior_enable(struct drm_encoder *encoder)
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct nouveau_connector *nv_connector;
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struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
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struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
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u8 owner = 1 << nv_crtc->index;
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u8 proto, depth;
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u8 proto;
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u32 *push;
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nv50_outp_acquire(nv_encoder);
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nv_connector = nouveau_encoder_connector_get(nv_encoder);
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switch (nv_connector->base.display_info.bpc) {
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case 10: depth = 0x6; break;
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case 8: depth = 0x5; break;
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case 6: depth = 0x2; break;
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default: depth = 0x0; break;
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case 10: asyh->or.depth = 0x6; break;
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case 8: asyh->or.depth = 0x5; break;
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case 6: asyh->or.depth = 0x2; break;
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default: asyh->or.depth = 0x0; break;
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}
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switch (nv_encoder->dcb->type) {
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@ -3952,13 +3949,11 @@ nv50_pior_enable(struct drm_encoder *encoder)
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push = evo_wait(core, 8);
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if (push) {
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
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u32 ctrl = (depth << 16) | (proto << 8) | owner;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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ctrl |= 0x00001000;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ctrl |= 0x00002000;
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evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
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evo_data(push, ctrl);
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evo_data(push, (asyh->or.depth << 16) |
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(asyh->or.nvsync << 13) |
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(asyh->or.nhsync << 12) |
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(proto << 8) | owner);
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}
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evo_kick(push, core);
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@ -32,6 +32,7 @@
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#include <drm/drm_encoder_slave.h>
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#include <drm/drm_dp_mst_helper.h>
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#include "dispnv04/disp.h"
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struct nv50_head_atom;
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#define NV_DPMS_CLEARED 0x80
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@ -68,7 +69,7 @@ struct nouveau_encoder {
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void (*enc_save)(struct drm_encoder *encoder);
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void (*enc_restore)(struct drm_encoder *encoder);
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void (*update)(struct nouveau_encoder *, u8 head,
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struct drm_display_mode *, u8 proto, u8 depth);
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struct nv50_head_atom *, u8 proto, u8 depth);
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};
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struct nouveau_encoder *
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