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drm/i915: Zero unused WM1 watermarks on VLV/CHV 

The hardware supposedly ignores the WM1 watermarks while the PND
deadline mode is enabled, but clear out the register just in case.
This is what the other OS does, and it does make register dumps look
more consistent when we don't have partial WM1 values lingering in
the registers (some WM1 watermarks already get zeroed when the actually
used DSPFW registers get written).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
hifive-unleashed-5.1
Ville Syrjälä 2015-06-24 22:00:10 +03:00 committed by Daniel Vetter
parent de38b95cbb
commit 2cb389b7e4
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/i915/intel_pm.c
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@ -927,6 +927,12 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
}
/* zero (unused) WM1 watermarks */
I915_WRITE(DSPFW4, 0);
I915_WRITE(DSPFW5, 0);
I915_WRITE(DSPFW6, 0);
I915_WRITE(DSPHOWM1, 0);
POSTING_READ(DSPFW1);
}