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drm/ast: Fix incorrect register check for DRAM width

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During DRAM initialization on certain ASpeed devices, an incorrect
bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.

Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05.

Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Timothy Pearson 2016-02-26 15:29:32 -06:00 committed by Dave Airlie
parent ead8f34c70
commit 2d02b8bdba
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/ast/ast_main.c
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@ -227,7 +227,7 @@ static int ast_get_dram_info(struct drm_device *dev)
} while (ast_read32(ast, 0x10000) != 0x01);
data = ast_read32(ast, 0x10004);
if (data & 0x400)
if (data & 0x40)
ast->dram_bus_width = 16;
else
ast->dram_bus_width = 32;