MLK-21876-13 ipu: add uapi headfile for yocto build pass
Copied from 4.14.78 GA. Module onwer could merge it when adding drivers code. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>5.4-rM2-2.2.x-imx-squashed
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/*
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* Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @defgroup IPU MXC Image Processing Unit (IPU) Driver
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*/
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/*!
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* @file uapi/linux/ipu.h
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*
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* @brief This file contains the IPU driver API declarations.
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*
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* @ingroup IPU
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*/
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#ifndef __ASM_ARCH_IPU_H__
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#define __ASM_ARCH_IPU_H__
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#ifndef __KERNEL__
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#ifndef __cplusplus
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typedef unsigned char bool;
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#endif
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#define irqreturn_t int
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#define dma_addr_t int
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#define uint32_t unsigned int
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#define uint16_t unsigned short
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#define uint8_t unsigned char
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#define u32 unsigned int
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#define u8 unsigned char
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#define __u32 u32
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#endif
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/*!
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* Enumeration of IPU rotation modes
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*/
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typedef enum {
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/* Note the enum values correspond to BAM value */
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IPU_ROTATE_NONE = 0,
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IPU_ROTATE_VERT_FLIP = 1,
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IPU_ROTATE_HORIZ_FLIP = 2,
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IPU_ROTATE_180 = 3,
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IPU_ROTATE_90_RIGHT = 4,
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IPU_ROTATE_90_RIGHT_VFLIP = 5,
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IPU_ROTATE_90_RIGHT_HFLIP = 6,
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IPU_ROTATE_90_LEFT = 7,
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} ipu_rotate_mode_t;
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/*!
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* Enumeration of VDI MOTION select
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*/
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typedef enum {
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MED_MOTION = 0,
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LOW_MOTION = 1,
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HIGH_MOTION = 2,
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} ipu_motion_sel;
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/*!
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* Enumeration of DI ports for ADC.
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*/
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typedef enum {
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DISP0,
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DISP1,
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DISP2,
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DISP3
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} display_port_t;
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/* IPU Pixel format definitions */
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/* Four-character-code (FOURCC) */
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#define fourcc(a, b, c, d)\
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(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
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/*!
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* @name IPU Pixel Formats
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*
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* Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
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* the same used by V4L2 API.
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*/
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/*! @{ */
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/*! @name GPU Tile Formats */
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/*! @{ */
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#define IPU_PIX_FMT_GPU32_SB_ST fourcc('5', 'P', '4', 'S') /*!< 32bit split buf 4x4 standard */
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#define IPU_PIX_FMT_GPU32_SB_SRT fourcc('5', 'P', '4', 'R') /*!< 32bit split buf 4x4 super */
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#define IPU_PIX_FMT_GPU32_ST fourcc('5', 'I', '4', 'S') /*!< 32bit single buf 4x4 standard */
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#define IPU_PIX_FMT_GPU32_SRT fourcc('5', 'I', '4', 'R') /*!< 32bit single buf 4x4 super */
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#define IPU_PIX_FMT_GPU16_SB_ST fourcc('4', 'P', '8', 'S') /*!< 16bit split buf 8x4 standard */
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#define IPU_PIX_FMT_GPU16_SB_SRT fourcc('4', 'P', '8', 'R') /*!< 16bit split buf 8x4 super */
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#define IPU_PIX_FMT_GPU16_ST fourcc('4', 'I', '8', 'S') /*!< 16bit single buf 8x4 standard */
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#define IPU_PIX_FMT_GPU16_SRT fourcc('4', 'I', '8', 'R') /*!< 16bit single buf 8x4 super */
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/*! @{ */
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/*! @name Generic or Raw Data Formats */
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/*! @{ */
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#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */
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#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */
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#define IPU_PIX_FMT_GENERIC_16 fourcc('I', 'P', 'U', '2') /*!< IPU Generic Data */
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#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */
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#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */
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/*! @} */
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/*! @name RGB Formats */
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/*! @{ */
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#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
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#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
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#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
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#define IPU_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */
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#define IPU_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */
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#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
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#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
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#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
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#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
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#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */
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#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
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#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
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#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
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#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
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#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
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/*! @} */
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/*! @name YUV Interleaved Formats */
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/*! @{ */
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#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
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#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
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#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */
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#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */
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#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
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#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
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#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */
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#define IPU_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */
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/* two planes -- one Y, one Cb + Cr interleaved */
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#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
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#define PRE_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */
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#define IPU_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
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#define PRE_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 16 Y/CbCr 4:2:2 */
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/* two planes -- 12 tiled Y/CbCr 4:2:0 */
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#define IPU_PIX_FMT_TILED_NV12 fourcc('T', 'N', 'V', 'P')
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#define IPU_PIX_FMT_TILED_NV12F fourcc('T', 'N', 'V', 'F')
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/*! @} */
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/*! @name YUV Planar Formats */
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/*! @{ */
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#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
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#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
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#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
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#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
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#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
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#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
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#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
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#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
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/* non-interleaved 4:4:4 */
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#define IPU_PIX_FMT_YUV444P fourcc('4', '4', '4', 'P') /*!< 24 YUV 4:4:4 */
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/*! @} */
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#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16)
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#define TILED_NV12_FRAME_SIZE(w, h) \
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(ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K))
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/* IPU device */
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typedef enum {
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RGB_CS,
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YUV_CS,
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NULL_CS
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} cs_t;
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struct ipu_pos {
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u32 x;
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u32 y;
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};
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struct ipu_crop {
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struct ipu_pos pos;
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u32 w;
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u32 h;
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};
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struct ipu_deinterlace {
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bool enable;
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u8 motion; /*see ipu_motion_sel*/
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#define IPU_DEINTERLACE_FIELD_TOP 0
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#define IPU_DEINTERLACE_FIELD_BOTTOM 1
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#define IPU_DEINTERLACE_FIELD_MASK \
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(IPU_DEINTERLACE_FIELD_TOP | IPU_DEINTERLACE_FIELD_BOTTOM)
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/* deinterlace frame rate double flags */
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#define IPU_DEINTERLACE_RATE_EN 0x80
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#define IPU_DEINTERLACE_RATE_FRAME1 0x40
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#define IPU_DEINTERLACE_RATE_MASK \
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(IPU_DEINTERLACE_RATE_EN | IPU_DEINTERLACE_RATE_FRAME1)
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#define IPU_DEINTERLACE_MAX_FRAME 2
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u8 field_fmt;
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};
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struct ipu_input {
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u32 width;
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u32 height;
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u32 format;
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struct ipu_crop crop;
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dma_addr_t paddr;
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struct ipu_deinterlace deinterlace;
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dma_addr_t paddr_n; /*valid when deinterlace enable*/
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};
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struct ipu_alpha {
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#define IPU_ALPHA_MODE_GLOBAL 0
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#define IPU_ALPHA_MODE_LOCAL 1
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u8 mode;
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u8 gvalue; /* 0~255 */
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dma_addr_t loc_alp_paddr;
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};
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struct ipu_colorkey {
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bool enable;
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u32 value; /* RGB 24bit */
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};
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struct ipu_overlay {
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u32 width;
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u32 height;
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u32 format;
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struct ipu_crop crop;
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struct ipu_alpha alpha;
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struct ipu_colorkey colorkey;
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dma_addr_t paddr;
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};
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struct ipu_output {
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u32 width;
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u32 height;
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u32 format;
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u8 rotate;
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struct ipu_crop crop;
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dma_addr_t paddr;
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};
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struct ipu_task {
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struct ipu_input input;
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struct ipu_output output;
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bool overlay_en;
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struct ipu_overlay overlay;
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#define IPU_TASK_PRIORITY_NORMAL 0
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#define IPU_TASK_PRIORITY_HIGH 1
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u8 priority;
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#define IPU_TASK_ID_ANY 0
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#define IPU_TASK_ID_VF 1
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#define IPU_TASK_ID_PP 2
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#define IPU_TASK_ID_MAX 3
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u8 task_id;
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int timeout;
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};
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enum {
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IPU_CHECK_OK = 0,
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IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1,
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IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2,
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IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4,
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IPU_CHECK_ERR_MIN,
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IPU_CHECK_ERR_INPUT_CROP,
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IPU_CHECK_ERR_OUTPUT_CROP,
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IPU_CHECK_ERR_OVERLAY_CROP,
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IPU_CHECK_ERR_INPUT_OVER_LIMIT,
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IPU_CHECK_ERR_OV_OUT_NO_FIT,
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IPU_CHECK_ERR_OVERLAY_WITH_VDI,
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IPU_CHECK_ERR_PROC_NO_NEED,
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IPU_CHECK_ERR_SPLIT_INPUTW_OVER,
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IPU_CHECK_ERR_SPLIT_INPUTH_OVER,
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IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER,
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IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER,
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IPU_CHECK_ERR_SPLIT_WITH_ROT,
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IPU_CHECK_ERR_NOT_SUPPORT,
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IPU_CHECK_ERR_NOT16ALIGN,
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IPU_CHECK_ERR_W_DOWNSIZE_OVER,
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IPU_CHECK_ERR_H_DOWNSIZE_OVER,
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};
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/* IOCTL commands */
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#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task)
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#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task)
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#define IPU_ALLOC _IOWR('I', 0x3, int)
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#define IPU_FREE _IOW('I', 0x4, int)
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#endif
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