From 2dbaa6a6dcf01b84bcf076a0e906dc7dacbd0a1d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Jun 2019 02:19:44 +0200 Subject: [PATCH] ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew to minimum (-420 ps), to improve signal integrity. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 622cc7cc1471..a060718758b6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -96,10 +96,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1860>; }; }; };