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drm/amd/powerplay: fix byte alignment issue of smu11 pptable

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The smu_11_0_powerplay_table, smu_11_0_power_saving_clock_table, and
smu_11_0_overdrive_table need byte alignment. So we must add packed attribute
in the definitions.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2019-02-12 15:39:44 +08:00 committed by Alex Deucher
parent 4322e4c251
commit 2dd1209e57
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
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@ -91,7 +91,7 @@ struct smu_11_0_overdrive_table
uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags
uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings
uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings
};
} __attribute__((packed));
enum SMU_11_0_PPCLOCK_ID {
SMU_11_0_PPCLOCK_GFXCLK = 0,
@ -115,7 +115,7 @@ struct smu_11_0_power_saving_clock_table
uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
};
} __attribute__((packed));
struct smu_11_0_powerplay_table
{
@ -142,6 +142,6 @@ struct smu_11_0_powerplay_table
struct smu_11_0_overdrive_table overdrive_table;
PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
};
} __attribute__((packed));
#endif