Qualcomm ARM64 DT updates for v5.6
* Align SDM845 firmware paths with linux-firmware * Make WiFi work on Dragonboard845c * Wire up wakeup controller for SDM845 * Critical thermal interrupt support for SDM845, MSM8996 and MSM8998 * Enable UFS for SM8150 * Add remoteproc enablers and nodes for SM8150 * Add CPUfreq for SM8150 * Add RPMH power-domain node for SM8150 * Cleanup and refactor MSM8996 dts structure * Add initial Inforce Computing IFC6640 dts * Increase MSM8996 core voltage * Fix MSM8996 USB phy settings * Add missing alias for BLSP UART in MSM8998 MTP * Add remoteproc nodes for ADSP, modem and sensor core for MSM8998 * Enable WiFI for MSM8998 * Introduce the SC7180 platform and the IDP development board * Add CPUfreq, QUPs, USB, remoteproc etc for SC7180 * Enable USB OTG for Dragonboard 410c * Add vibrator motor node for PM8916 * Properly specify APCS clocks for MSM8916 * Add CPR and HFPLL for QCS404 * Enable full CPUfreq (with AVS) for QCS404 -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAl4czOIbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FqygP/Aw1zvnCyKYfWGYrzXi2 X7moY5Re0mm1ePQwlZyK681wrdGX3EghkpHeGxoHpApZGUE7K/bkeWH5shtEltmI SA1WrszRbcs9BL1jKXlC46kmjNTGkEjfqIJDwT0SxvN2XMQJGp/Dn8cg6eSOhDt4 UAsXMOPoOJiiOo6zuQZzDHcSzRvUl4Ea4ePPcVILRLjco33rjvKtJYg2Syq7v4Zi Jqd1UhWuY/s1KlfJ13Oi3q9/HuWjt4C756U3eHPQOyTbKVbAIMZq3g5qK+ph3oSp 6alwHagCLS945PvuZIZsy8XtKjowuNfMqHFJQVllkOF3bkVa/QnuMFHID2V+MHYC B1WFCGZPB0bn3ItGy+oBF/6H8Djz9iAmo7WD4pt25rSqDGMVRhd5vn3LhEo/p2wk Zs2RrQqYqr0gvklLX5CGts5WAND5Np8NGH6rAoC9HnfTSaCQucuCMi/kF3oS1m2X tihvXbJmbRfi/LHcKbM8Jvb+C5Hqw7BhuBohk5GExwEcrJoX2dCr7ZIjEKNr+NBI B2VmuPujwZjthl5CyZUlgTEYd4lko+Rq8WYfpHz6W9ZATuP1SMrMxhSHh1jWD2qT CHcWfyDRJ7/TVw7n90dLx8sbjKxw6cz7U9jh4hJ0ovEAeUS0MGaXxh0FzYlzGFjO 79D+Lz4GLL1OASC79crgDM36 =IqrO -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DT updates for v5.6 * Align SDM845 firmware paths with linux-firmware * Make WiFi work on Dragonboard845c * Wire up wakeup controller for SDM845 * Critical thermal interrupt support for SDM845, MSM8996 and MSM8998 * Enable UFS for SM8150 * Add remoteproc enablers and nodes for SM8150 * Add CPUfreq for SM8150 * Add RPMH power-domain node for SM8150 * Cleanup and refactor MSM8996 dts structure * Add initial Inforce Computing IFC6640 dts * Increase MSM8996 core voltage * Fix MSM8996 USB phy settings * Add missing alias for BLSP UART in MSM8998 MTP * Add remoteproc nodes for ADSP, modem and sensor core for MSM8998 * Enable WiFI for MSM8998 * Introduce the SC7180 platform and the IDP development board * Add CPUfreq, QUPs, USB, remoteproc etc for SC7180 * Enable USB OTG for Dragonboard 410c * Add vibrator motor node for PM8916 * Properly specify APCS clocks for MSM8916 * Add CPR and HFPLL for QCS404 * Enable full CPUfreq (with AVS) for QCS404 * tag 'qcom-arm64-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (88 commits) arm64: dts: qcom: sdm845: move gpu zap nodes to per-device dts arm64: dts: qcom: sm8150: Hard code rpmhpd constants arm64: dts: apq8096-db820c: Fix VDD core voltage arm64: dts: qcom: qcs404-evb: Set vdd_apc regulator in high power mode arm64: dts: qcom: msm8998-mtp: Add alias for blsp1_uart3 arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 arm64: dts: qcom: msm8996: Fix venus iommu nodename error arm64: dts: qcom: sdm845: add the ufs reset arm64: dts: qcom: sm8150: Fix UFS phy register size arm64: dts: qcom: sm8150-mtp: Add UFS gpio reset arm64: dts: qcom: qcs404: Add CPR and populate OPP table arm64: dts: qcom: qcs404: Add DVFS support arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider arm64: dts: qcom: qcs404: Add HFPLL node arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider arm64: dts: qcom: sc7180: Add rpmh power-domain node arm64: dts: pm8004: Add SPMI regulator and add phandles to lsids arm64: dts: msm8998: thermal: Add critical interrupt support arm64: dts: msm8996: thermal: Add critical interrupt support arm64: dts: qcom: db845c: Move remoteproc firmware to sdm845 ... Link: https://lore.kernel.org/r/20200113204225.GB3325@yoga Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
2e04d1bd54
|
@ -24,28 +24,30 @@ description: |
|
|||
|
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The 'SoC' element must be one of the following strings:
|
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|
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apq8016
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apq8074
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apq8084
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apq8096
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msm8916
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msm8974
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msm8992
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msm8994
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msm8996
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mdm9615
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ipq8074
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sdm845
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apq8016
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apq8074
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apq8084
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apq8096
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ipq8074
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mdm9615
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msm8916
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msm8974
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msm8992
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msm8994
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msm8996
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sc7180
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sdm845
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The 'board' element must be one of the following strings:
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cdp
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liquid
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dragonboard
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mtp
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sbc
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hk01
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qrd
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cdp
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dragonboard
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hk01
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idp
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liquid
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mtp
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qrd
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sbc
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The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
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where the minor number may be omitted when it's zero, i.e. v1.0 is the same
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|
@ -144,4 +146,8 @@ properties:
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- qcom,ipq8074-hk01
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- const: qcom,ipq8074
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- items:
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- enum:
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- qcom,sc7180-idp
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- const: qcom,sc7180
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...
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|
|
|
@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
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|
@ -13,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
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|
|
|
@ -5,6 +5,15 @@
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&pm8916_gpios {
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usb_hub_reset_pm: usb_hub_reset_pm {
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pinconf {
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pins = "gpio3";
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function = PMIC_GPIO_FUNC_NORMAL;
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input-disable;
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output-high;
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};
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};
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|
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usb_hub_reset_pm_device: usb_hub_reset_pm_device {
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pinconf {
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pins = "gpio3";
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function = PMIC_GPIO_FUNC_NORMAL;
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|
@ -22,6 +31,16 @@
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};
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};
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usb_sw_sel_pm_device: usb_sw_sel_pm_device {
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pinconf {
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pins = "gpio4";
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function = PMIC_GPIO_FUNC_NORMAL;
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power-source = <PM8916_GPIO_VPH>;
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input-disable;
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output-low;
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};
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};
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|
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pm8916_gpios_leds: pm8916_gpios_leds {
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pinconf {
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pins = "gpio1", "gpio2";
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|
|
|
@ -358,14 +358,15 @@
|
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};
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usb@78d9000 {
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extcon = <&usb_id>;
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extcon = <&usb_id>, <&usb_id>;
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status = "okay";
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adp-disable;
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hnp-disable;
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srp-disable;
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dr_mode = "host";
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pinctrl-names = "default";
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pinctrl-0 = <&usb_sw_sel_pm>;
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dr_mode = "otg";
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pinctrl-names = "default", "device";
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pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
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pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
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ulpi {
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phy {
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v1p8-supply = <&pm8916_l7>;
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|
@ -504,7 +505,7 @@
|
|||
|
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usb_id: usb-id {
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compatible = "linux,extcon-usb-gpio";
|
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vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
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id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb_id_default>;
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};
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|
|
|
@ -1,109 +0,0 @@
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|||
// SPDX-License-Identifier: GPL-2.0-only
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/*
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||||
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*/
|
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&msmgpio {
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sdc2_cd_on: sdc2_cd_on {
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mux {
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pins = "gpio38";
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function = "gpio";
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};
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config {
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pins = "gpio38";
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bias-pull-up; /* pull up */
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drive-strength = <16>; /* 16 MA */
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};
|
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};
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sdc2_cd_off: sdc2_cd_off {
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mux {
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pins = "gpio38";
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function = "gpio";
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};
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config {
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pins = "gpio38";
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bias-pull-up; /* pull up */
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drive-strength = <2>; /* 2 MA */
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};
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};
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blsp1_uart1_default: blsp1_uart1_default {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "blsp_uart2";
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};
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <16>;
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bias-disable;
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};
|
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};
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "gpio";
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};
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|
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <2>;
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bias-disable;
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};
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};
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hdmi_hpd_active: hdmi_hpd_active {
|
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mux {
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pins = "gpio34";
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function = "hdmi_hot";
|
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};
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config {
|
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pins = "gpio34";
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bias-pull-down;
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drive-strength = <16>;
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};
|
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};
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hdmi_hpd_suspend: hdmi_hpd_suspend {
|
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mux {
|
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pins = "gpio34";
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function = "hdmi_hot";
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};
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|
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config {
|
||||
pins = "gpio34";
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bias-pull-down;
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drive-strength = <2>;
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};
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};
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hdmi_ddc_active: hdmi_ddc_active {
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mux {
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pins = "gpio32", "gpio33";
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function = "hdmi_ddc";
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};
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config {
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pins = "gpio32", "gpio33";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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hdmi_ddc_suspend: hdmi_ddc_suspend {
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mux {
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pins = "gpio32", "gpio33";
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function = "hdmi_ddc";
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};
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config {
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pins = "gpio32", "gpio33";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
|
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@ -1,92 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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&pm8994_gpios {
|
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pinctrl-names = "default";
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pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
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ls_exp_gpio_f: pm8994_gpio5 {
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pinconf {
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pins = "gpio5";
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output-low;
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power-source = <2>; // PM8994_GPIO_S4, 1.8V
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};
|
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};
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bt_en_gpios: bt_en_gpios {
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pinconf {
|
||||
pins = "gpio19";
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function = PMIC_GPIO_FUNC_NORMAL;
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output-low;
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power-source = <PM8994_GPIO_S4>; // 1.8V
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
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bias-pull-down;
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};
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};
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wlan_en_gpios: wlan_en_gpios {
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||||
pinconf {
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||||
pins = "gpio8";
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function = PMIC_GPIO_FUNC_NORMAL;
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output-low;
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power-source = <PM8994_GPIO_S4>; // 1.8V
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qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
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bias-pull-down;
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||||
};
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};
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|
||||
audio_mclk: clk_div1 {
|
||||
pinconf {
|
||||
pins = "gpio15";
|
||||
function = "func1";
|
||||
power-source = <PM8994_GPIO_S4>; // 1.8V
|
||||
};
|
||||
};
|
||||
|
||||
volume_up_gpio: pm8996_gpio2 {
|
||||
pinconf {
|
||||
pins = "gpio2";
|
||||
function = "normal";
|
||||
input-enable;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
|
||||
power-source = <PM8994_GPIO_S4>; // 1.8V
|
||||
};
|
||||
};
|
||||
|
||||
divclk4_pin_a: divclk4 {
|
||||
pinconf {
|
||||
pins = "gpio18";
|
||||
function = PMIC_GPIO_FUNC_FUNC2;
|
||||
|
||||
bias-disable;
|
||||
power-source = <PM8994_GPIO_S4>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3_vbus_det_gpio: pm8996_gpio22 {
|
||||
pinconf {
|
||||
pins = "gpio22";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
|
||||
power-source = <PM8994_GPIO_S4>; // 1.8V
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmi8994_gpios {
|
||||
usb2_vbus_det_gpio: pmi8996_gpio6 {
|
||||
pinconf {
|
||||
pins = "gpio6";
|
||||
function = PMIC_GPIO_FUNC_NORMAL;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
|
||||
power-source = <PM8994_GPIO_S4>; // 1.8V
|
||||
};
|
||||
};
|
||||
};
|
File diff suppressed because it is too large
Load diff
385
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
Normal file
385
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
Normal file
|
@ -0,0 +1,385 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8996.dtsi"
|
||||
#include "pm8994.dtsi"
|
||||
#include "pmi8994.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Inforce 6640 Single Board Computer";
|
||||
compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096";
|
||||
|
||||
qcom,msm-id = <291 0x00030001>;
|
||||
qcom,board-id = <0x00010018 0>;
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp2_uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
v1p05: v1p05-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reglator-name = "v1p05";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
|
||||
vin-supply = <&v5p0>;
|
||||
};
|
||||
|
||||
v12_poe: v12-poe-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reglator-name = "v12_poe";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
v3p3: v3p3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3p3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
vin-supply = <&v12_poe>;
|
||||
};
|
||||
|
||||
v5p0: v5p0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5p0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
vin-supply = <&v12_poe>;
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-min-microvolt = <3800000>;
|
||||
regulator-max-microvolt = <3800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp2_uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&blsp2_uart1_2pins_default>;
|
||||
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
|
||||
};
|
||||
|
||||
&msmgpio {
|
||||
sdc2_pins_default: sdc2-pins-default {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
cd {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_pins_sleep: sdc2-pins-sleep {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cd {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
pm8994-regulators {
|
||||
compatible = "qcom,rpm-pm8994-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_s2-supply = <&vph_pwr>;
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_s6-supply = <&vph_pwr>;
|
||||
vdd_s7-supply = <&vph_pwr>;
|
||||
vdd_s8-supply = <&vph_pwr>;
|
||||
vdd_s9-supply = <&vph_pwr>;
|
||||
vdd_s10-supply = <&vph_pwr>;
|
||||
vdd_s11-supply = <&vph_pwr>;
|
||||
vdd_s12-supply = <&vph_pwr>;
|
||||
vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
|
||||
vdd_l3_l11-supply = <&vreg_s3a_1p3>;
|
||||
vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
|
||||
vdd_l5_l7-supply = <&vreg_s5a_2p15>;
|
||||
vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
|
||||
vdd_l8_l16_l30-supply = <&vph_pwr>;
|
||||
vdd_l25-supply = <&vreg_s3a_1p3>;
|
||||
vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vreg_s3a_1p3: s3 {
|
||||
regulator-name = "vreg_s3a_1p3";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: s4 {
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
vreg_s5a_2p15: s5 {
|
||||
regulator-name = "vreg_s5a_2p15";
|
||||
regulator-min-microvolt = <2150000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
};
|
||||
vreg_s7a_1p0: s7 {
|
||||
regulator-name = "vreg_s7a_1p0";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
};
|
||||
|
||||
vreg_l1a_1p0: l1 {
|
||||
regulator-name = "vreg_l1a_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
vreg_l2a_1p25: l2 {
|
||||
regulator-name = "vreg_l2a_1p25";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
};
|
||||
vreg_l3a_0p875: l3 {
|
||||
regulator-name = "vreg_l3a_0p875";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
};
|
||||
vreg_l4a_1p225: l4 {
|
||||
regulator-name = "vreg_l4a_1p225";
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
};
|
||||
vreg_l6a_1p2: l6 {
|
||||
regulator-name = "vreg_l6a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
vreg_l8a_1p8: l8 {
|
||||
regulator-name = "vreg_l8a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l9a_1p8: l9 {
|
||||
regulator-name = "vreg_l9a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l10a_1p8: l10 {
|
||||
regulator-name = "vreg_l10a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l11a_1p15: l11 {
|
||||
regulator-name = "vreg_l11a_1p15";
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
};
|
||||
vreg_l12a_1p8: l12 {
|
||||
regulator-name = "vreg_l12a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l13a_2p95: l13 {
|
||||
regulator-name = "vreg_l13a_2p95";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
vreg_l14a_1p8: l14 {
|
||||
regulator-name = "vreg_l14a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l15a_1p8: l15 {
|
||||
regulator-name = "vreg_l15a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l16a_2p7: l16 {
|
||||
regulator-name = "vreg_l16a_2p7";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
vreg_l17a_2p8: l17 {
|
||||
regulator-name = "vreg_l17a_2p8";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
vreg_l18a_2p85: l18 {
|
||||
regulator-name = "vreg_l18a_2p85";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
vreg_l19a_2p8: l19 {
|
||||
regulator-name = "vreg_l19a_2p8";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
vreg_l20a_2p95: l20 {
|
||||
regulator-name = "vreg_l20a_2p95";
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_l21a_2p95: l21 {
|
||||
regulator-name = "vreg_l21a_2p95";
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
vreg_l22a_3p0: l22 {
|
||||
regulator-name = "vreg_l22a_3p0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
vreg_l23a_2p8: l23 {
|
||||
regulator-name = "vreg_l23a_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
vreg_l24a_3p075: l24 {
|
||||
regulator-name = "vreg_l24a_3p075";
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
vreg_l25a_1p2: l25 {
|
||||
regulator-name = "vreg_l25a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_l26a_0p8: l27 {
|
||||
regulator-name = "vreg_l26a_0p8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
vreg_l28a_0p925: l28 {
|
||||
regulator-name = "vreg_l28a_0p925";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <925000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
vreg_l29a_2p8: l29 {
|
||||
regulator-name = "vreg_l29a_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
vreg_l30a_1p8: l30 {
|
||||
regulator-name = "vreg_l30a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
vreg_l32a_1p8: l32 {
|
||||
regulator-name = "vreg_l32a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vreg_lvs1a_1p8: lvs1 {
|
||||
regulator-name = "vreg_lvs1a_1p8";
|
||||
};
|
||||
|
||||
vreg_lvs2a_1p8: lvs2 {
|
||||
regulator-name = "vreg_lvs2a_1p8";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc2 {
|
||||
status = "okay";
|
||||
|
||||
bus-width = <4>;
|
||||
|
||||
cd-gpios = <&msmgpio 38 0x1>;
|
||||
|
||||
vmmc-supply = <&vreg_l21a_2p95>;
|
||||
vqmmc-supply = <&vreg_l13a_2p95>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_pins_default>;
|
||||
pinctrl-1 = <&sdc2_pins_sleep>;
|
||||
};
|
||||
|
||||
&ufshc {
|
||||
status = "okay";
|
||||
|
||||
vcc-supply = <&vreg_l20a_2p95>;
|
||||
vccq-supply = <&vreg_l25a_1p2>;
|
||||
vccq2-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vcc-max-microamp = <600000>;
|
||||
vccq-max-microamp = <450000>;
|
||||
vccq2-max-microamp = <450000>;
|
||||
};
|
||||
|
||||
&ufsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l28a_0p925>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
|
||||
vdda-phy-max-microamp = <18380>;
|
||||
vdda-pll-max-microamp = <9440>;
|
||||
};
|
|
@ -429,7 +429,8 @@
|
|||
compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
|
||||
reg = <0xb011000 0x1000>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&a53pll>;
|
||||
clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
|
||||
clock-names = "pll", "aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
|
@ -816,6 +817,8 @@
|
|||
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
|
||||
nvmem-cell-names = "calib", "calib_sel";
|
||||
#qcom,sensors = <5>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -74,6 +74,23 @@
|
|||
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
&pm8005_lsid1 {
|
||||
pm8005-regulators {
|
||||
compatible = "qcom,pm8005-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
|
||||
pm8005_s1: s1 { /* VDD_GFX supply */
|
||||
regulator-min-microvolt = <524000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-enable-ramp-delay = <500>;
|
||||
|
||||
/* hack until we rig up the gpu consumer */
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
|
@ -292,3 +309,35 @@
|
|||
vdda-phy-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l2a_1p2>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
};
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
&blsp1_uart3_on {
|
||||
rx {
|
||||
/delete-property/ bias-disable;
|
||||
/*
|
||||
* Configure a pull-up on 45 (RX). This is needed to
|
||||
* avoid garbage data when the TX pin of the Bluetooth
|
||||
* module is in tri-state (module powered off or not
|
||||
* driving the signal yet).
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
cts {
|
||||
/delete-property/ bias-disable;
|
||||
/*
|
||||
* Configure a pull-down on 47 (CTS) to match the pull
|
||||
* of the Bluetooth module.
|
||||
*/
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -9,6 +9,7 @@
|
|||
/ {
|
||||
aliases {
|
||||
serial0 = &blsp2_uart1;
|
||||
serial1 = &blsp1_uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
@ -311,6 +312,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_slpi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
};
|
||||
|
@ -364,3 +373,35 @@
|
|||
vdda-phy-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l2a_1p2>;
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
};
|
||||
|
||||
/* PINCTRL - board-specific pinctrl */
|
||||
&blsp1_uart3_on {
|
||||
rx {
|
||||
/delete-property/ bias-disable;
|
||||
/*
|
||||
* Configure a pull-up on 45 (RX). This is needed to
|
||||
* avoid garbage data when the TX pin of the Bluetooth
|
||||
* module is in tri-state (module powered off or not
|
||||
* driving the signal yet).
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
cts {
|
||||
/delete-property/ bias-disable;
|
||||
/*
|
||||
* Configure a pull-down on 47 (CTS) to match the pull
|
||||
* of the Bluetooth module.
|
||||
*/
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -77,13 +77,30 @@
|
|||
};
|
||||
|
||||
blsp1_uart3_on: blsp1_uart3_on {
|
||||
mux {
|
||||
pins = "gpio45", "gpio46", "gpio47", "gpio48";
|
||||
tx {
|
||||
pins = "gpio45";
|
||||
function = "blsp_uart3_a";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio45", "gpio46", "gpio47", "gpio48";
|
||||
rx {
|
||||
pins = "gpio46";
|
||||
function = "blsp_uart3_a";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cts {
|
||||
pins = "gpio47";
|
||||
function = "blsp_uart3_a";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rfr {
|
||||
pins = "gpio48";
|
||||
function = "blsp_uart3_a";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
@ -28,8 +29,13 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
memory@85800000 {
|
||||
reg = <0x0 0x85800000 0x0 0x800000>;
|
||||
hyp_mem: memory@85800000 {
|
||||
reg = <0x0 0x85800000 0x0 0x600000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
xbl_mem: memory@85e00000 {
|
||||
reg = <0x0 0x85e00000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
|
@ -38,21 +44,69 @@
|
|||
no-map;
|
||||
};
|
||||
|
||||
memory@86200000 {
|
||||
tz_mem: memory@86200000 {
|
||||
reg = <0x0 0x86200000 0x0 0x2d00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rmtfs {
|
||||
rmtfs_mem: memory@88f00000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
|
||||
size = <0x0 0x200000>;
|
||||
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
|
||||
reg = <0x0 0x88f00000 0x0 0x200000>;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
qcom,vmid = <15>;
|
||||
};
|
||||
|
||||
spss_mem: memory@8ab00000 {
|
||||
reg = <0x0 0x8ab00000 0x0 0x700000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
adsp_mem: memory@8b200000 {
|
||||
reg = <0x0 0x8b200000 0x0 0x1a00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_mem: memory@8cc00000 {
|
||||
reg = <0x0 0x8cc00000 0x0 0x7000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
venus_mem: memory@93c00000 {
|
||||
reg = <0x0 0x93c00000 0x0 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mba_mem: memory@94100000 {
|
||||
reg = <0x0 0x94100000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
slpi_mem: memory@94300000 {
|
||||
reg = <0x0 0x94300000 0x0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_fw_mem: memory@95200000 {
|
||||
reg = <0x0 0x95200000 0x0 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_gsi_mem: memory@95210000 {
|
||||
reg = <0x0 0x95210000 0x0 0x5000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
gpu_mem: memory@95600000 {
|
||||
reg = <0x0 0x95600000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wlan_msa_mem: memory@95700000 {
|
||||
reg = <0x0 0x95700000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
@ -817,8 +871,9 @@
|
|||
reg = <0x010ab000 0x1000>, /* TM */
|
||||
<0x010aa000 0x1000>; /* SROT */
|
||||
#qcom,sensors = <14>;
|
||||
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
@ -827,8 +882,9 @@
|
|||
reg = <0x010ae000 0x1000>, /* TM */
|
||||
<0x010ad000 0x1000>; /* SROT */
|
||||
#qcom,sensors = <8>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
@ -847,6 +903,25 @@
|
|||
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
anoc2_smmu: iommu@16c0000 {
|
||||
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0x016c0000 0x40000>;
|
||||
#iommu-cells = <1>;
|
||||
|
||||
#global-interrupts = <0>;
|
||||
interrupts =
|
||||
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie0: pci@1c00000 {
|
||||
compatible = "qcom,pcie-msm8996";
|
||||
reg = <0x01c00000 0x2000>,
|
||||
|
@ -987,7 +1062,7 @@
|
|||
|
||||
tcsr_mutex_regs: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x01f40000 0x20000>;
|
||||
reg = <0x01f40000 0x40000>;
|
||||
};
|
||||
|
||||
tlmm: pinctrl@3400000 {
|
||||
|
@ -1000,6 +1075,110 @@
|
|||
#interrupt-cells = <0x2>;
|
||||
};
|
||||
|
||||
remoteproc_mss: remoteproc@4080000 {
|
||||
compatible = "qcom,msm8998-mss-pil";
|
||||
reg = <0x04080000 0x100>, <0x04180000 0x20>;
|
||||
reg-names = "qdsp6", "rmb";
|
||||
|
||||
interrupts-extended =
|
||||
<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack",
|
||||
"shutdown-ack";
|
||||
|
||||
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
|
||||
<&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
|
||||
<&gcc GCC_BOOT_ROM_AHB_CLK>,
|
||||
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_MSS_SNOC_AXI_CLK>,
|
||||
<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
|
||||
<&rpmcc RPM_SMD_QDSS_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "bus", "mem", "gpll0_mss",
|
||||
"snoc_axi", "mnoc_axi", "qdss", "xo";
|
||||
|
||||
qcom,smem-states = <&modem_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
resets = <&gcc GCC_MSS_RESTART>;
|
||||
reset-names = "mss_restart";
|
||||
|
||||
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
|
||||
|
||||
power-domains = <&rpmpd MSM8998_VDDCX>,
|
||||
<&rpmpd MSM8998_VDDMX>;
|
||||
power-domain-names = "cx", "mx";
|
||||
|
||||
mba {
|
||||
memory-region = <&mba_mem>;
|
||||
};
|
||||
|
||||
mpss {
|
||||
memory-region = <&mpss_mem>;
|
||||
};
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "modem";
|
||||
qcom,remote-pid = <1>;
|
||||
mboxes = <&apcs_glb 15>;
|
||||
};
|
||||
};
|
||||
|
||||
gpucc: clock-controller@5065000 {
|
||||
compatible = "qcom,msm8998-gpucc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x05065000 0x9000>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GPLL0_OUT_MAIN>;
|
||||
clock-names = "xo",
|
||||
"gpll0";
|
||||
};
|
||||
|
||||
remoteproc_slpi: remoteproc@5800000 {
|
||||
compatible = "qcom,msm8998-slpi-pas";
|
||||
reg = <0x05800000 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
px-supply = <&vreg_lvs2a_1p8>;
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
|
||||
clock-names = "xo", "aggre2";
|
||||
|
||||
memory-region = <&slpi_mem>;
|
||||
|
||||
qcom,smem-states = <&slpi_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
power-domains = <&rpmpd MSM8998_SSCCX>;
|
||||
power-domain-names = "ssc_cx";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "dsps";
|
||||
qcom,remote-pid = <3>;
|
||||
mboxes = <&apcs_glb 27>;
|
||||
};
|
||||
};
|
||||
|
||||
stm: stm@6002000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0x06002000 0x1000>,
|
||||
|
@ -1792,6 +1971,39 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
remoteproc_adsp: remoteproc@17300000 {
|
||||
compatible = "qcom,msm8998-adsp-pas";
|
||||
reg = <0x17300000 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "xo";
|
||||
|
||||
memory-region = <&adsp_mem>;
|
||||
|
||||
qcom,smem-states = <&adsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
power-domains = <&rpmpd MSM8998_VDDCX>;
|
||||
power-domain-names = "cx";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "lpass";
|
||||
qcom,remote-pid = <2>;
|
||||
mboxes = <&apcs_glb 9>;
|
||||
};
|
||||
};
|
||||
|
||||
apcs_glb: mailbox@17911000 {
|
||||
compatible = "qcom,msm8998-apcs-hmss-global";
|
||||
reg = <0x17911000 0x1000>;
|
||||
|
@ -1870,6 +2082,32 @@
|
|||
redistributor-stride = <0x0 0x20000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifi: wifi@18800000 {
|
||||
compatible = "qcom,wcn3990-wifi";
|
||||
status = "disabled";
|
||||
reg = <0x18800000 0x800000>;
|
||||
reg-names = "membase";
|
||||
memory-region = <&wlan_msa_mem>;
|
||||
clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
|
||||
clock-names = "cxo_ref_clk_pin";
|
||||
interrupts =
|
||||
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&anoc2_smmu 0x1900>,
|
||||
<&anoc2_smmu 0x1901>;
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
72
arch/arm64/boot/dts/qcom/pm6150.dtsi
Normal file
72
arch/arm64/boot/dts/qcom/pm6150.dtsi
Normal file
|
@ -0,0 +1,72 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
|
||||
#include <dt-bindings/iio/qcom,spmi-vadc.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
&spmi_bus {
|
||||
pm6150_lsid0: pmic@0 {
|
||||
compatible = "qcom,pm6150", "qcom,spmi-pmic";
|
||||
reg = <0x0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm6150_pon: pon@800 {
|
||||
compatible = "qcom,pm8998-pon";
|
||||
reg = <0x800>;
|
||||
mode-bootloader = <0x2>;
|
||||
mode-recovery = <0x1>;
|
||||
|
||||
pwrkey {
|
||||
compatible = "qcom,pm8941-pwrkey";
|
||||
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
|
||||
pm6150_temp: temp-alarm@2400 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0x2400>;
|
||||
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
|
||||
io-channel-names = "thermal";
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm6150_adc: adc@3100 {
|
||||
compatible = "qcom,spmi-adc5";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
adc-chan@6 {
|
||||
reg = <ADC5_DIE_TEMP>;
|
||||
label = "die_temp";
|
||||
};
|
||||
};
|
||||
|
||||
pm6150_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pm6150_gpio 0 0 10>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pm6150_lsid1: pmic@1 {
|
||||
compatible = "qcom,pm6150", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
31
arch/arm64/boot/dts/qcom/pm6150l.dtsi
Normal file
31
arch/arm64/boot/dts/qcom/pm6150l.dtsi
Normal file
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
pm6150l_lsid4: pmic@4 {
|
||||
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
|
||||
reg = <0x4 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm6150l_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pm6150l_gpio 0 0 12>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pm6150l_lsid5: pmic@5 {
|
||||
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
|
@ -4,17 +4,23 @@
|
|||
|
||||
&spmi_bus {
|
||||
|
||||
pmic@4 {
|
||||
pm8004_lsid4: pmic@4 {
|
||||
compatible = "qcom,pm8004", "qcom,spmi-pmic";
|
||||
reg = <0x4 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmic@5 {
|
||||
pm8004_lsid5: pmic@5 {
|
||||
compatible = "qcom,pm8004", "qcom,spmi-pmic";
|
||||
reg = <0x5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pm8004_spmi_regulators: regulators {
|
||||
compatible = "qcom,pm8004-regulators";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -111,6 +111,12 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8916_vib: vibrator@c000 {
|
||||
compatible = "qcom,pm8916-vib";
|
||||
reg = <0xc000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wcd_codec: codec@f000 {
|
||||
compatible = "qcom,pm8916-wcd-analog-codec";
|
||||
reg = <0xf000 0x200>;
|
||||
|
|
|
@ -85,5 +85,9 @@
|
|||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8994_spmi_regulators: regulators {
|
||||
compatible = "qcom,pm8994-regulators";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -73,6 +73,7 @@
|
|||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd_apc";
|
||||
regulator-initial-mode = <1>;
|
||||
regulator-min-microvolt = <1048000>;
|
||||
regulator-max-microvolt = <1384000>;
|
||||
};
|
||||
|
|
|
@ -42,6 +42,10 @@
|
|||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
|
@ -52,6 +56,10 @@
|
|||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
|
@ -62,6 +70,10 @@
|
|||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
|
@ -72,6 +84,10 @@
|
|||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
|
@ -94,6 +110,41 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: cpr-opp-table {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scm: scm {
|
||||
compatible = "qcom,scm-qcs404", "qcom,scm";
|
||||
|
@ -280,6 +331,62 @@
|
|||
tsens_caldata: caldata@d0 {
|
||||
reg = <0x1f8 0x14>;
|
||||
};
|
||||
cpr_efuse_speedbin: speedbin@13c {
|
||||
reg = <0x13c 0x4>;
|
||||
bits = <2 3>;
|
||||
};
|
||||
cpr_efuse_quot_offset1: qoffset1@231 {
|
||||
reg = <0x231 0x4>;
|
||||
bits = <4 7>;
|
||||
};
|
||||
cpr_efuse_quot_offset2: qoffset2@232 {
|
||||
reg = <0x232 0x4>;
|
||||
bits = <3 7>;
|
||||
};
|
||||
cpr_efuse_quot_offset3: qoffset3@233 {
|
||||
reg = <0x233 0x4>;
|
||||
bits = <2 7>;
|
||||
};
|
||||
cpr_efuse_init_voltage1: ivoltage1@229 {
|
||||
reg = <0x229 0x4>;
|
||||
bits = <4 6>;
|
||||
};
|
||||
cpr_efuse_init_voltage2: ivoltage2@22a {
|
||||
reg = <0x22a 0x4>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
cpr_efuse_init_voltage3: ivoltage3@22b {
|
||||
reg = <0x22b 0x4>;
|
||||
bits = <0 6>;
|
||||
};
|
||||
cpr_efuse_quot1: quot1@22b {
|
||||
reg = <0x22b 0x4>;
|
||||
bits = <6 12>;
|
||||
};
|
||||
cpr_efuse_quot2: quot2@22d {
|
||||
reg = <0x22d 0x4>;
|
||||
bits = <2 12>;
|
||||
};
|
||||
cpr_efuse_quot3: quot3@230 {
|
||||
reg = <0x230 0x4>;
|
||||
bits = <0 12>;
|
||||
};
|
||||
cpr_efuse_ring1: ring1@228 {
|
||||
reg = <0x228 0x4>;
|
||||
bits = <0 3>;
|
||||
};
|
||||
cpr_efuse_ring2: ring2@228 {
|
||||
reg = <0x228 0x4>;
|
||||
bits = <4 3>;
|
||||
};
|
||||
cpr_efuse_ring3: ring3@229 {
|
||||
reg = <0x229 0x4>;
|
||||
bits = <0 3>;
|
||||
};
|
||||
cpr_efuse_revision: revision@218 {
|
||||
reg = <0x218 0x4>;
|
||||
bits = <3 3>;
|
||||
};
|
||||
};
|
||||
|
||||
rng: rng@e3000 {
|
||||
|
@ -902,14 +1009,65 @@
|
|||
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
|
||||
reg = <0x0b011000 0x1000>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
|
||||
clock-names = "pll", "aux";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
apcs_hfpll: clock-controller@b016000 {
|
||||
compatible = "qcom,hfpll";
|
||||
reg = <0x0b016000 0x30>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "apcs_hfpll";
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
compatible = "qcom,kpss-wdt";
|
||||
compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
|
||||
reg = <0x0b017000 0x1000>;
|
||||
clocks = <&sleep_clk>;
|
||||
};
|
||||
|
||||
cpr: power-controller@b018000 {
|
||||
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
||||
reg = <0x0b018000 0x1000>;
|
||||
interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "ref";
|
||||
vdd-apc-supply = <&pms405_s3>;
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&cpr_opp_table>;
|
||||
acc-syscon = <&tcsr>;
|
||||
|
||||
nvmem-cells = <&cpr_efuse_quot_offset1>,
|
||||
<&cpr_efuse_quot_offset2>,
|
||||
<&cpr_efuse_quot_offset3>,
|
||||
<&cpr_efuse_init_voltage1>,
|
||||
<&cpr_efuse_init_voltage2>,
|
||||
<&cpr_efuse_init_voltage3>,
|
||||
<&cpr_efuse_quot1>,
|
||||
<&cpr_efuse_quot2>,
|
||||
<&cpr_efuse_quot3>,
|
||||
<&cpr_efuse_ring1>,
|
||||
<&cpr_efuse_ring2>,
|
||||
<&cpr_efuse_ring3>,
|
||||
<&cpr_efuse_revision>;
|
||||
nvmem-cell-names = "cpr_quotient_offset1",
|
||||
"cpr_quotient_offset2",
|
||||
"cpr_quotient_offset3",
|
||||
"cpr_init_voltage1",
|
||||
"cpr_init_voltage2",
|
||||
"cpr_init_voltage3",
|
||||
"cpr_quotient1",
|
||||
"cpr_quotient2",
|
||||
"cpr_quotient3",
|
||||
"cpr_ring_osc1",
|
||||
"cpr_ring_osc2",
|
||||
"cpr_ring_osc3",
|
||||
"cpr_fuse_revision";
|
||||
};
|
||||
|
||||
timer@b120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
430
arch/arm64/boot/dts/qcom/sc7180-idp.dts
Normal file
430
arch/arm64/boot/dts/qcom/sc7180-idp.dts
Normal file
|
@ -0,0 +1,430 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* SC7180 IDP board device tree source
|
||||
*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sc7180.dtsi"
|
||||
#include "pm6150.dtsi"
|
||||
#include "pm6150l.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SC7180 IDP";
|
||||
compatible = "qcom,sc7180-idp", "qcom,sc7180";
|
||||
|
||||
aliases {
|
||||
hsuart0 = &uart3;
|
||||
serial0 = &uart8;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm6150-rpmh-regulators {
|
||||
compatible = "qcom,pm6150-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vreg_s1a_1p1: smps1 {
|
||||
regulator-min-microvolt = <1128000>;
|
||||
regulator-max-microvolt = <1128000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p0: smps4 {
|
||||
regulator-min-microvolt = <824000>;
|
||||
regulator-max-microvolt = <1120000>;
|
||||
};
|
||||
|
||||
vreg_s5a_2p0: smps5 {
|
||||
regulator-min-microvolt = <1744000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
vreg_l1a_1p2: ldo1 {
|
||||
regulator-min-microvolt = <1178000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l2a_1p0: ldo2 {
|
||||
regulator-min-microvolt = <944000>;
|
||||
regulator-max-microvolt = <1056000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l3a_1p0: ldo3 {
|
||||
regulator-min-microvolt = <968000>;
|
||||
regulator-max-microvolt = <1064000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l4a_0p8: ldo4 {
|
||||
regulator-min-microvolt = <824000>;
|
||||
regulator-max-microvolt = <928000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l5a_2p7: ldo5 {
|
||||
regulator-min-microvolt = <2496000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l6a_0p6: ldo6 {
|
||||
regulator-min-microvolt = <568000>;
|
||||
regulator-max-microvolt = <648000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l9a_0p6: ldo9 {
|
||||
regulator-min-microvolt = <488000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l10a_1p8: ldo10 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1832000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l11a_1p8: ldo11 {
|
||||
regulator-min-microvolt = <1696000>;
|
||||
regulator-max-microvolt = <1904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-min-microvolt = <1696000>;
|
||||
regulator-max-microvolt = <1952000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l13a_1p8: ldo13 {
|
||||
regulator-min-microvolt = <1696000>;
|
||||
regulator-max-microvolt = <1904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-min-microvolt = <1728000>;
|
||||
regulator-max-microvolt = <1832000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p8: ldo15 {
|
||||
regulator-min-microvolt = <1696000>;
|
||||
regulator-max-microvolt = <1904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l16a_2p7: ldo16 {
|
||||
regulator-min-microvolt = <2496000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l17a_3p0: ldo17 {
|
||||
regulator-min-microvolt = <2920000>;
|
||||
regulator-max-microvolt = <3232000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l18a_2p8: ldo18 {
|
||||
regulator-min-microvolt = <2496000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l19a_2p9: ldo19 {
|
||||
regulator-min-microvolt = <2696000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm6150l-rpmh-regulators {
|
||||
compatible = "qcom,pm6150l-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vreg_s8c_1p3: smps8 {
|
||||
regulator-min-microvolt = <1120000>;
|
||||
regulator-max-microvolt = <1408000>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-min-microvolt = <1616000>;
|
||||
regulator-max-microvolt = <1984000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_1p3: ldo2 {
|
||||
regulator-min-microvolt = <1168000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_1p2: ldo3 {
|
||||
regulator-min-microvolt = <1144000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l4c_1p8: ldo4 {
|
||||
regulator-min-microvolt = <1648000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l5c_1p8: ldo5 {
|
||||
regulator-min-microvolt = <1648000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l6c_2p9: ldo6 {
|
||||
regulator-min-microvolt = <2696000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p9: ldo9 {
|
||||
regulator-min-microvolt = <2952000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l10c_3p3: ldo10 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_l11c_3p3: ldo11 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
spi-tx-bus-width = <2>;
|
||||
spi-rx-bus-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
vdd-supply = <&vreg_l4a_0p8>;
|
||||
vdda-pll-supply = <&vreg_l11a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l17a_3p0>;
|
||||
qcom,imp-res-offset-value = <8>;
|
||||
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
|
||||
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
|
||||
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vreg_l4a_0p8>;
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
|
||||
|
||||
&qspi_clk {
|
||||
pinconf {
|
||||
pins = "gpio63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_cs0 {
|
||||
pinconf {
|
||||
pins = "gpio68";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_data01 {
|
||||
pinconf {
|
||||
pins = "gpio64", "gpio65";
|
||||
|
||||
/* High-Z when no transfers; nice to park the lines */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c2_default {
|
||||
pinconf {
|
||||
pins = "gpio15", "gpio16";
|
||||
drive-strength = <2>;
|
||||
|
||||
/* Has external pullup */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c4_default {
|
||||
pinconf {
|
||||
pins = "gpio115", "gpio116";
|
||||
drive-strength = <2>;
|
||||
|
||||
/* Has external pullup */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c7_default {
|
||||
pinconf {
|
||||
pins = "gpio6", "gpio7";
|
||||
drive-strength = <2>;
|
||||
|
||||
/* Has external pullup */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c9_default {
|
||||
pinconf {
|
||||
pins = "gpio46", "gpio47";
|
||||
drive-strength = <2>;
|
||||
|
||||
/* Has external pullup */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_uart3_default {
|
||||
pinconf-cts {
|
||||
/*
|
||||
* Configure a pull-down on 38 (CTS) to match the pull of
|
||||
* the Bluetooth module.
|
||||
*/
|
||||
pins = "gpio38";
|
||||
bias-pull-down;
|
||||
output-high;
|
||||
};
|
||||
|
||||
pinconf-rts {
|
||||
/* We'll drive 39 (RTS), so no pull */
|
||||
pins = "gpio39";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinconf-tx {
|
||||
/* We'll drive 40 (TX), so no pull */
|
||||
pins = "gpio40";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
|
||||
pinconf-rx {
|
||||
/*
|
||||
* Configure a pull-up on 41 (RX). This is needed to avoid
|
||||
* garbage data when the TX pin of the Bluetooth module is
|
||||
* in tri-state (module powered off or not driving the
|
||||
* signal yet).
|
||||
*/
|
||||
pins = "gpio41";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_uart8_default {
|
||||
pinconf-tx {
|
||||
pins = "gpio44";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinconf-rx {
|
||||
pins = "gpio45";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_spi0_default {
|
||||
pinconf {
|
||||
pins = "gpio34", "gpio35", "gpio36", "gpio37";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_spi6_default {
|
||||
pinconf {
|
||||
pins = "gpio59", "gpio60", "gpio61", "gpio62";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_spi10_default {
|
||||
pinconf {
|
||||
pins = "gpio86", "gpio87", "gpio88", "gpio89";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
2187
arch/arm64/boot/dts/qcom/sc7180.dtsi
Normal file
2187
arch/arm64/boot/dts/qcom/sc7180.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
@ -165,7 +165,6 @@
|
|||
/delete-node/ &venus_mem;
|
||||
/delete-node/ &cdsp_mem;
|
||||
/delete-node/ &cdsp_pas;
|
||||
/delete-node/ &zap_shader;
|
||||
/delete-node/ &gpu_mem;
|
||||
|
||||
/* Increase the size from 120 MB to 128 MB */
|
||||
|
@ -651,6 +650,20 @@ ap_ts_i2c: &i2c14 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&spi5 {
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
compatible = "google,cr50";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&h1_ap_int_odl>;
|
||||
spi-max-frequency = <800000>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <129 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi10 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -197,7 +197,7 @@
|
|||
&adsp_pas {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "qcom/db845c/adsp.mdt";
|
||||
firmware-name = "qcom/sdm845/adsp.mdt";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
|
@ -343,7 +343,7 @@
|
|||
|
||||
&cdsp_pas {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/db845c/cdsp.mdt";
|
||||
firmware-name = "qcom/sdm845/cdsp.mdt";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
|
@ -352,6 +352,18 @@
|
|||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
firmware-name = "qcom/sdm845/a630_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
|
||||
};
|
||||
|
||||
&pm8998_gpio {
|
||||
vol_up_pin_a: vol-up-active {
|
||||
pins = "gpio6";
|
||||
|
@ -529,6 +541,8 @@
|
|||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
|
||||
|
||||
qcom,snoc-host-cap-8bit-quirk;
|
||||
};
|
||||
|
||||
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
|
||||
|
|
|
@ -360,6 +360,13 @@
|
|||
<GCC_LPASS_SWAY_CLK>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
firmware-name = "qcom/sdm845/a630_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
|
@ -1357,7 +1357,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cache-controller@1100000 {
|
||||
system-cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
|
@ -1374,6 +1374,8 @@
|
|||
lanes-per-direction = <2>;
|
||||
power-domains = <&gcc UFS_PHY_GDSC>;
|
||||
#reset-cells = <1>;
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
iommus = <&apps_smmu 0x100 0xf>;
|
||||
|
||||
|
@ -1447,6 +1449,7 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 150>;
|
||||
wakeup-parent = <&pdc_intc>;
|
||||
|
||||
qspi_clk: qspi-clk {
|
||||
pinmux {
|
||||
|
@ -2804,7 +2807,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpu@5000000 {
|
||||
gpu: gpu@5000000 {
|
||||
compatible = "qcom,adreno-630.2", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
|
@ -2824,10 +2827,6 @@
|
|||
|
||||
qcom,gmu = <&gmu>;
|
||||
|
||||
zap_shader: zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
|
@ -2939,6 +2938,15 @@
|
|||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pdc_intc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sdm845-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>;
|
||||
qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
pdc_reset: reset-controller@b2e0000 {
|
||||
compatible = "qcom,sdm845-pdc-global";
|
||||
reg = <0 0x0b2e0000 0 0x20000>;
|
||||
|
@ -2950,8 +2958,9 @@
|
|||
reg = <0 0x0c263000 0 0x1ff>, /* TM */
|
||||
<0 0x0c222000 0 0x1ff>; /* SROT */
|
||||
#qcom,sensors = <13>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
@ -2960,8 +2969,9 @@
|
|||
reg = <0 0x0c265000 0 0x1ff>, /* TM */
|
||||
<0 0x0c223000 0 0x1ff>; /* SROT */
|
||||
#qcom,sensors = <8>;
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
|
@ -3191,7 +3201,7 @@
|
|||
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gic-its@17a40000 {
|
||||
msi-controller@17a40000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
|
|
|
@ -245,6 +245,13 @@
|
|||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "sm8150.dtsi"
|
||||
#include "pm8150.dtsi"
|
||||
#include "pm8150b.dtsi"
|
||||
|
@ -366,6 +367,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_slpi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <126 4>;
|
||||
};
|
||||
|
@ -373,3 +386,25 @@
|
|||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l10a_2p5>;
|
||||
vcc-max-microamp = <750000>;
|
||||
vccq-supply = <&vreg_l9a_1p2>;
|
||||
vccq-max-microamp = <700000>;
|
||||
vccq2-supply = <&vreg_s4a_1p8>;
|
||||
vccq2-max-microamp = <750000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
|
||||
vdda-max-microamp = <90200>;
|
||||
vdda-pll-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-max-microamp = <19000>;
|
||||
};
|
||||
|
|
|
@ -5,8 +5,11 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-aoss-qmp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
@ -42,6 +45,7 @@
|
|||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -57,6 +61,7 @@
|
|||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -70,6 +75,7 @@
|
|||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -82,6 +88,7 @@
|
|||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -94,6 +101,7 @@
|
|||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -106,6 +114,7 @@
|
|||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -118,6 +127,7 @@
|
|||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -130,6 +140,7 @@
|
|||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
|
@ -283,6 +294,102 @@
|
|||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
smp2p-cdsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
|
||||
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
mboxes = <&apss_shared 6>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
cdsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
cdsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
smp2p-lpass {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
mboxes = <&apss_shared 10>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
adsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
adsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
smp2p-mpss {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <435>, <428>;
|
||||
|
||||
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
mboxes = <&apss_shared 14>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <1>;
|
||||
|
||||
modem_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
modem_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
smp2p-slpi {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <481>, <430>;
|
||||
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
mboxes = <&apss_shared 26>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <3>;
|
||||
|
||||
slpi_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
slpi_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
@ -306,8 +413,8 @@
|
|||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc 123>,
|
||||
<&gcc 124>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
@ -317,17 +424,120 @@
|
|||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00a90000 0x0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc 105>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ufs_mem_hc: ufshc@1d84000 {
|
||||
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
|
||||
"jedec,ufs-2.0";
|
||||
reg = <0 0x01d84000 0 0x2500>;
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&ufs_mem_phy_lanes>;
|
||||
phy-names = "ufsphy";
|
||||
lanes-per-direction = <2>;
|
||||
#reset-cells = <1>;
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
freq-table-hz =
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_mem_phy: phy@1d87000 {
|
||||
compatible = "qcom,sm8150-qmp-ufs-phy";
|
||||
reg = <0 0x01d87000 0 0x1c0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-names = "ref",
|
||||
"ref_aux";
|
||||
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
||||
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
||||
|
||||
resets = <&ufs_mem_hc 0>;
|
||||
reset-names = "ufsphy";
|
||||
status = "disabled";
|
||||
|
||||
ufs_mem_phy_lanes: lanes@1d87400 {
|
||||
reg = <0 0x01d87400 0 0x108>,
|
||||
<0 0x01d87600 0 0x1e0>,
|
||||
<0 0x01d87c00 0 0x1dc>,
|
||||
<0 0x01d87800 0 0x108>,
|
||||
<0 0x01d87a00 0 0x1e0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex_regs: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x01f40000 0x0 0x40000>;
|
||||
};
|
||||
|
||||
remoteproc_slpi: remoteproc@2400000 {
|
||||
compatible = "qcom,sm8150-slpi-pas";
|
||||
reg = <0x0 0x02400000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
|
||||
<&rpmhpd 3>,
|
||||
<&rpmhpd 2>;
|
||||
power-domain-names = "load_state", "lcx", "lmx";
|
||||
|
||||
memory-region = <&slpi_mem>;
|
||||
|
||||
qcom,smem-states = <&slpi_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "dsps";
|
||||
qcom,remote-pid = <3>;
|
||||
mboxes = <&apss_shared 24>;
|
||||
};
|
||||
};
|
||||
|
||||
tlmm: pinctrl@3100000 {
|
||||
compatible = "qcom,sm8150-pinctrl";
|
||||
reg = <0x0 0x03100000 0x0 0x300000>,
|
||||
|
@ -343,6 +553,74 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
remoteproc_mpss: remoteproc@4080000 {
|
||||
compatible = "qcom,sm8150-mpss-pas";
|
||||
reg = <0x0 0x04080000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready", "handover",
|
||||
"stop-ack", "shutdown-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
|
||||
<&rpmhpd 7>,
|
||||
<&rpmhpd 0>;
|
||||
power-domain-names = "load_state", "cx", "mss";
|
||||
|
||||
memory-region = <&mpss_mem>;
|
||||
|
||||
qcom,smem-states = <&modem_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "modem";
|
||||
qcom,remote-pid = <1>;
|
||||
mboxes = <&apss_shared 12>;
|
||||
};
|
||||
};
|
||||
|
||||
remoteproc_cdsp: remoteproc@8300000 {
|
||||
compatible = "qcom,sm8150-cdsp-pas";
|
||||
reg = <0x0 0x08300000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
|
||||
<&rpmhpd 7>;
|
||||
power-domain-names = "load_state", "cx";
|
||||
|
||||
memory-region = <&cdsp_mem>;
|
||||
|
||||
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "cdsp";
|
||||
qcom,remote-pid = <5>;
|
||||
mboxes = <&apss_shared 4>;
|
||||
};
|
||||
};
|
||||
|
||||
aoss_qmp: power-controller@c300000 {
|
||||
compatible = "qcom,sm8150-aoss-qmp";
|
||||
reg = <0x0 0x0c300000 0x0 0x100000>;
|
||||
|
@ -372,6 +650,40 @@
|
|||
cell-index = <0>;
|
||||
};
|
||||
|
||||
remoteproc_adsp: remoteproc@17300000 {
|
||||
compatible = "qcom,sm8150-adsp-pas";
|
||||
reg = <0x0 0x17300000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
|
||||
<&rpmhpd 7>;
|
||||
power-domain-names = "load_state", "cx";
|
||||
|
||||
memory-region = <&adsp_mem>;
|
||||
|
||||
qcom,smem-states = <&adsp_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
||||
label = "lpass";
|
||||
qcom,remote-pid = <2>;
|
||||
mboxes = <&apss_shared 8>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17a00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
|
@ -387,6 +699,12 @@
|
|||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog@17c10000 {
|
||||
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
|
||||
reg = <0 0x17c10000 0 0x1000>;
|
||||
clocks = <&sleep_clk>;
|
||||
};
|
||||
|
||||
timer@17c20000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
@ -469,6 +787,73 @@
|
|||
clock-names = "xo";
|
||||
clocks = <&xo_board>;
|
||||
};
|
||||
|
||||
rpmhpd: power-controller {
|
||||
compatible = "qcom,sm8150-rpmhpd";
|
||||
#power-domain-cells = <1>;
|
||||
operating-points-v2 = <&rpmhpd_opp_table>;
|
||||
|
||||
rpmhpd_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
rpmhpd_opp_ret: opp1 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_min_svs: opp2 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_low_svs: opp3 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_svs: opp4 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_svs_l1: opp5 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_svs_l2: opp6 {
|
||||
opp-level = <224>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom: opp7 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom_l1: opp8 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_nom_l2: opp9 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_turbo: opp10 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_turbo_l1: opp11 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@18323000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
|
||||
<0 0x18327800 0 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1",
|
||||
"freq-domain2";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue