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clocksource/drivers/tegra: Add verbose definition for 1MHz constant 

Convert all 1MHz literals to a verbose constant for better readability.

Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
alistair/sunxi64-5.4-dsi
Dmitry Osipenko 2019-06-18 17:03:55 +03:00 committed by Daniel Lezcano
parent 7c708fda79
commit 2e08a4bb96
1 changed files with 7 additions and 5 deletions
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12
drivers/clocksource/timer-tegra.c
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@ -46,6 +46,8 @@
#define TIMER1_IRQ_IDX 0
#define TIMER10_IRQ_IDX 10
#define TIMER_1MHz 1000000
static u32 usec_config;
static void __iomem *timer_reg_base;
@ -160,7 +162,7 @@ static unsigned long tegra_delay_timer_read_counter_long(void)
static struct delay_timer tegra_delay_timer = {
.read_current_timer = tegra_delay_timer_read_counter_long,
.freq = 1000000,
.freq = TIMER_1MHz,
};
#endif
@ -226,7 +228,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
* parent clock.
*/
if (tegra20)
return 1000000;
return TIMER_1MHz;
return timer_of_rate(to);
}
@ -315,11 +317,11 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
}
}
sched_clock_register(tegra_read_sched_clock, 32, 1000000);
sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000,
300, 32, clocksource_mmio_readl_up);
"timer_us", TIMER_1MHz, 300, 32,
clocksource_mmio_readl_up);
if (ret)
pr_err("failed to register clocksource: %d\n", ret);