[POWERPC] Cell interrupt rework
This patch reworks the cell iic interrupt handling so that: - Node ID is back in the interrupt number (only one IRQ host is created for all nodes). This allows interrupts from sources on another node to be routed non-locally. This will allow possibly one day to fix maxcpus=1 or 2 and still get interrupts from devices on BE 1. (A bit more fixing is needed for that) and it will allow us to implement actual affinity control of external interrupts. - Added handling of the IO exceptions interrupts (badly named, but I re-used the name initially used by STI). Those are the interrupts exposed by IIC_ISR and IIC_IRR, such as the IOC translation exception, performance monitor, etc... Those get their special numbers in the IRQ number space and are internally implemented as a cascade on unit 0xe, class 1 of each node. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
f3c87a8999
commit
2e19458312
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@ -21,6 +21,12 @@
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* TODO:
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* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
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* vs node numbers in the setup code
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* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
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* a non-active node to the active node)
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*/
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#include <linux/interrupt.h>
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@ -44,24 +50,25 @@ struct iic {
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u8 target_id;
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u8 eoi_stack[16];
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int eoi_ptr;
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struct irq_host *host;
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struct device_node *node;
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};
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static DEFINE_PER_CPU(struct iic, iic);
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#define IIC_NODE_COUNT 2
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static struct irq_host *iic_hosts[IIC_NODE_COUNT];
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static struct irq_host *iic_host;
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/* Convert between "pending" bits and hw irq number */
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static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
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{
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unsigned char unit = bits.source & 0xf;
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unsigned char node = bits.source >> 4;
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unsigned char class = bits.class & 3;
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/* Decode IPIs */
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if (bits.flags & CBE_IIC_IRQ_IPI)
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return IIC_IRQ_IPI0 | (bits.prio >> 4);
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else if (bits.class <= 3)
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return (bits.class << 4) | unit;
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return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
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else
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return IIC_IRQ_INVALID;
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return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
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}
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static void iic_mask(unsigned int irq)
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@ -86,21 +93,70 @@ static struct irq_chip iic_chip = {
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.eoi = iic_eoi,
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};
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static void iic_ioexc_eoi(unsigned int irq)
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{
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}
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static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc,
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struct pt_regs *regs)
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{
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struct cbe_iic_regs *node_iic = desc->handler_data;
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unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
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unsigned long bits, ack;
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int cascade;
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for (;;) {
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bits = in_be64(&node_iic->iic_is);
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if (bits == 0)
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break;
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/* pre-ack edge interrupts */
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ack = bits & IIC_ISR_EDGE_MASK;
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if (ack)
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out_be64(&node_iic->iic_is, ack);
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/* handle them */
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for (cascade = 63; cascade >= 0; cascade--)
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if (bits & (0x8000000000000000UL >> cascade)) {
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unsigned int cirq =
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irq_linear_revmap(iic_host,
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base | cascade);
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if (cirq != NO_IRQ)
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generic_handle_irq(cirq, regs);
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}
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/* post-ack level interrupts */
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ack = bits & ~IIC_ISR_EDGE_MASK;
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if (ack)
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out_be64(&node_iic->iic_is, ack);
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}
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desc->chip->eoi(irq);
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}
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static struct irq_chip iic_ioexc_chip = {
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.typename = " CELL-IOEX",
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.mask = iic_mask,
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.unmask = iic_unmask,
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.eoi = iic_ioexc_eoi,
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};
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/* Get an IRQ number from the pending state register of the IIC */
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static unsigned int iic_get_irq(struct pt_regs *regs)
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{
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struct cbe_iic_pending_bits pending;
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struct iic *iic;
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unsigned int virq;
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iic = &__get_cpu_var(iic);
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*(unsigned long *) &pending =
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in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
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if (!(pending.flags & CBE_IIC_IRQ_VALID))
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return NO_IRQ;
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virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
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if (virq == NO_IRQ)
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return NO_IRQ;
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iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
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BUG_ON(iic->eoi_ptr > 15);
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if (pending.flags & CBE_IIC_IRQ_VALID)
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return irq_linear_revmap(iic->host,
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iic_pending_to_hwnum(pending));
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return NO_IRQ;
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return virq;
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}
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#ifdef CONFIG_SMP
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@ -108,12 +164,7 @@ static unsigned int iic_get_irq(struct pt_regs *regs)
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/* Use the highest interrupt priorities for IPI */
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static inline int iic_ipi_to_irq(int ipi)
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{
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return IIC_IRQ_IPI0 + IIC_NUM_IPIS - 1 - ipi;
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}
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static inline int iic_irq_to_ipi(int irq)
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{
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return IIC_NUM_IPIS - 1 - (irq - IIC_IRQ_IPI0);
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return IIC_IRQ_TYPE_IPI + 0xf - ipi;
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}
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void iic_setup_cpu(void)
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@ -123,7 +174,7 @@ void iic_setup_cpu(void)
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void iic_cause_IPI(int cpu, int mesg)
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{
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out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
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out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
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}
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u8 iic_get_target_id(int cpu)
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@ -134,9 +185,7 @@ EXPORT_SYMBOL_GPL(iic_get_target_id);
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struct irq_host *iic_get_irq_host(int node)
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{
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if (node < 0 || node >= IIC_NODE_COUNT)
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return NULL;
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return iic_hosts[node];
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return iic_host;
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}
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EXPORT_SYMBOL_GPL(iic_get_irq_host);
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@ -149,34 +198,20 @@ static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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return IRQ_HANDLED;
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}
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static void iic_request_ipi(int ipi, const char *name)
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{
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int node, virq;
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int virq;
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for (node = 0; node < IIC_NODE_COUNT; node++) {
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char *rname;
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if (iic_hosts[node] == NULL)
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continue;
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virq = irq_create_mapping(iic_hosts[node],
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iic_ipi_to_irq(ipi));
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if (virq == NO_IRQ) {
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printk(KERN_ERR
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"iic: failed to map IPI %s on node %d\n",
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name, node);
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continue;
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}
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rname = kzalloc(strlen(name) + 16, GFP_KERNEL);
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if (rname)
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sprintf(rname, "%s node %d", name, node);
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else
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rname = (char *)name;
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if (request_irq(virq, iic_ipi_action, IRQF_DISABLED,
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rname, (void *)(long)ipi))
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printk(KERN_ERR
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"iic: failed to request IPI %s on node %d\n",
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name, node);
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virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
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if (virq == NO_IRQ) {
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printk(KERN_ERR
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"iic: failed to map IPI %s\n", name);
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return;
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}
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if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
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(void *)(long)ipi))
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printk(KERN_ERR
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"iic: failed to request IPI %s\n", name);
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}
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void iic_request_IPIs(void)
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@ -193,16 +228,24 @@ void iic_request_IPIs(void)
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static int iic_host_match(struct irq_host *h, struct device_node *node)
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{
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return h->host_data != NULL && node == h->host_data;
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return device_is_compatible(node,
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"IBM,CBEA-Internal-Interrupt-Controller");
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}
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static int iic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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if (hw < IIC_IRQ_IPI0)
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set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
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else
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switch (hw & IIC_IRQ_TYPE_MASK) {
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case IIC_IRQ_TYPE_IPI:
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set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
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break;
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case IIC_IRQ_TYPE_IOEXC:
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set_irq_chip_and_handler(virq, &iic_ioexc_chip,
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handle_fasteoi_irq);
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break;
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default:
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set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
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}
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return 0;
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}
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@ -211,11 +254,39 @@ static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/* Currently, we don't translate anything. That needs to be fixed as
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* we get better defined device-trees. iic interrupts have to be
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* explicitely mapped by whoever needs them
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*/
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return -ENODEV;
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unsigned int node, ext, unit, class;
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const u32 *val;
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if (!device_is_compatible(ct,
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"IBM,CBEA-Internal-Interrupt-Controller"))
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return -ENODEV;
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if (intsize != 1)
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return -ENODEV;
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val = get_property(ct, "#interrupt-cells", NULL);
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if (val == NULL || *val != 1)
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return -ENODEV;
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node = intspec[0] >> 24;
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ext = (intspec[0] >> 16) & 0xff;
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class = (intspec[0] >> 8) & 0xff;
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unit = intspec[0] & 0xff;
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/* Check if node is in supported range */
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if (node > 1)
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return -EINVAL;
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/* Build up interrupt number, special case for IO exceptions */
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*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
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if (unit == IIC_UNIT_IIC && class == 1)
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*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
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else
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*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
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(class << IIC_IRQ_CLASS_SHIFT) | unit;
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/* Dummy flags, ignored by iic code */
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*out_flags = IRQ_TYPE_EDGE_RISING;
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return 0;
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}
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static struct irq_host_ops iic_host_ops = {
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@ -225,7 +296,7 @@ static struct irq_host_ops iic_host_ops = {
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};
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static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
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struct irq_host *host)
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struct device_node *node)
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{
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/* XXX FIXME: should locate the linux CPU number from the HW cpu
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* number properly. We are lucky for now
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@ -237,19 +308,19 @@ static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
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iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
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iic->eoi_stack[0] = 0xff;
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iic->host = host;
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iic->node = of_node_get(node);
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out_be64(&iic->regs->prio, 0);
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printk(KERN_INFO "IIC for CPU %d at %lx mapped to %p, target id 0x%x\n",
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hw_cpu, addr, iic->regs, iic->target_id);
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printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
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hw_cpu, iic->target_id, node->full_name);
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}
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static int __init setup_iic(void)
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{
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struct device_node *dn;
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struct resource r0, r1;
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struct irq_host *host;
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int found = 0;
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unsigned int node, cascade, found = 0;
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struct cbe_iic_regs *node_iic;
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const u32 *np;
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for (dn = NULL;
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@ -269,19 +340,33 @@ static int __init setup_iic(void)
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of_node_put(dn);
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return -ENODEV;
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}
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host = NULL;
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if (found < IIC_NODE_COUNT) {
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host = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
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IIC_SOURCE_COUNT,
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&iic_host_ops,
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IIC_IRQ_INVALID);
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iic_hosts[found] = host;
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BUG_ON(iic_hosts[found] == NULL);
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iic_hosts[found]->host_data = of_node_get(dn);
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found++;
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}
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init_one_iic(np[0], r0.start, host);
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init_one_iic(np[1], r1.start, host);
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found++;
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init_one_iic(np[0], r0.start, dn);
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init_one_iic(np[1], r1.start, dn);
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/* Setup cascade for IO exceptions. XXX cleanup tricks to get
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* node vs CPU etc...
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* Note that we configure the IIC_IRR here with a hard coded
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* priority of 1. We might want to improve that later.
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*/
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node = np[0] >> 1;
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node_iic = cbe_get_cpu_iic_regs(np[0]);
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cascade = node << IIC_IRQ_NODE_SHIFT;
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cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
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cascade |= IIC_UNIT_IIC;
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cascade = irq_create_mapping(iic_host, cascade);
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if (cascade == NO_IRQ)
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continue;
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set_irq_data(cascade, node_iic);
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set_irq_chained_handler(cascade , iic_ioexc_cascade);
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out_be64(&node_iic->iic_ir,
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(1 << 12) /* priority */ |
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(node << 4) /* dest node */ |
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IIC_UNIT_THREAD_0 /* route them to thread 0 */);
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/* Flush pending (make sure it triggers if there is
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* anything pending
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*/
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out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
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}
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if (found)
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@ -292,6 +377,12 @@ static int __init setup_iic(void)
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void __init iic_init_IRQ(void)
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{
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/* Setup an irq host data structure */
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iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
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&iic_host_ops, IIC_IRQ_INVALID);
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BUG_ON(iic_host == NULL);
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irq_set_default_host(iic_host);
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/* Discover and initialize iics */
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if (setup_iic() < 0)
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panic("IIC: Failed to initialize !\n");
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@ -2,48 +2,76 @@
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#define ASM_CELL_PIC_H
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#ifdef __KERNEL__
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/*
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* Mapping of IIC pending bits into per-node
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* interrupt numbers.
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* Mapping of IIC pending bits into per-node interrupt numbers.
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*
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* IRQ FF CC SS PP FF CC SS PP Description
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* Interrupt numbers are in the range 0...0x1ff where the top bit
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* (0x100) represent the source node. Only 2 nodes are supported with
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* the current code though it's trivial to extend that if necessary using
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* higher level bits
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*
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* 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge
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* 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge
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* 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0
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* 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1
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* 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2
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* 70-7f C0 ** ** 00 - C0 ** ** 0f IPI
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* The bottom 8 bits are split into 2 type bits and 6 data bits that
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* depend on the type:
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*
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* F flags
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* C class
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* S source
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* P Priority
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* + node number
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* * don't care
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* 00 (0x00 | data) : normal interrupt. data is (class << 4) | source
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* 01 (0x40 | data) : IO exception. data is the exception number as
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* defined by bit numbers in IIC_SR
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* 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)
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* and node is always 0 (IPIs are per-cpu, their source is
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* not relevant)
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* 11 (0xc0 | data) : reserved
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*
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* A node consists of a Cell Broadband Engine and an optional
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* south bridge device providing a maximum of 64 IRQs.
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* The south bridge may be connected to either IOIF0
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* or IOIF1.
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* Each SPE is represented as three IRQ lines, one per
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* interrupt class.
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* 16 IRQ numbers are reserved for inter processor
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* interruptions, although these are only used in the
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* range of the first node.
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* In addition, interrupt number 0x80000000 is defined as always invalid
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* (that is the node field is expected to never extend to move than 23 bits)
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*
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* This scheme needs 128 IRQ numbers per BIF node ID,
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* which means that with the total of 512 lines
|
||||
* available, we can have a maximum of four nodes.
|
||||
*/
|
||||
|
||||
enum {
|
||||
IIC_IRQ_INVALID = 0xff,
|
||||
IIC_IRQ_MAX = 0x3f,
|
||||
IIC_IRQ_EXT_IOIF0 = 0x20,
|
||||
IIC_IRQ_EXT_IOIF1 = 0x2b,
|
||||
IIC_IRQ_IPI0 = 0x40,
|
||||
IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */
|
||||
IIC_SOURCE_COUNT = 0x50,
|
||||
IIC_IRQ_INVALID = 0x80000000u,
|
||||
IIC_IRQ_NODE_MASK = 0x100,
|
||||
IIC_IRQ_NODE_SHIFT = 8,
|
||||
IIC_IRQ_MAX = 0x1ff,
|
||||
IIC_IRQ_TYPE_MASK = 0xc0,
|
||||
IIC_IRQ_TYPE_NORMAL = 0x00,
|
||||
IIC_IRQ_TYPE_IOEXC = 0x40,
|
||||
IIC_IRQ_TYPE_IPI = 0x80,
|
||||
IIC_IRQ_CLASS_SHIFT = 4,
|
||||
IIC_IRQ_CLASS_0 = 0x00,
|
||||
IIC_IRQ_CLASS_1 = 0x10,
|
||||
IIC_IRQ_CLASS_2 = 0x20,
|
||||
IIC_SOURCE_COUNT = 0x200,
|
||||
|
||||
/* Here are defined the various source/dest units. Avoid using those
|
||||
* definitions if you can, they are mostly here for reference
|
||||
*/
|
||||
IIC_UNIT_SPU_0 = 0x4,
|
||||
IIC_UNIT_SPU_1 = 0x7,
|
||||
IIC_UNIT_SPU_2 = 0x3,
|
||||
IIC_UNIT_SPU_3 = 0x8,
|
||||
IIC_UNIT_SPU_4 = 0x2,
|
||||
IIC_UNIT_SPU_5 = 0x9,
|
||||
IIC_UNIT_SPU_6 = 0x1,
|
||||
IIC_UNIT_SPU_7 = 0xa,
|
||||
IIC_UNIT_IOC_0 = 0x0,
|
||||
IIC_UNIT_IOC_1 = 0xb,
|
||||
IIC_UNIT_THREAD_0 = 0xe, /* target only */
|
||||
IIC_UNIT_THREAD_1 = 0xf, /* target only */
|
||||
IIC_UNIT_IIC = 0xe, /* source only (IO exceptions) */
|
||||
|
||||
/* Base numbers for the external interrupts */
|
||||
IIC_IRQ_EXT_IOIF0 =
|
||||
IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,
|
||||
IIC_IRQ_EXT_IOIF1 =
|
||||
IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,
|
||||
|
||||
/* Base numbers for the IIC_ISR interrupts */
|
||||
IIC_IRQ_IOEX_TMI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,
|
||||
IIC_IRQ_IOEX_PMI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,
|
||||
IIC_IRQ_IOEX_ATI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,
|
||||
IIC_IRQ_IOEX_MATBFI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,
|
||||
IIC_IRQ_IOEX_ELDI = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,
|
||||
|
||||
/* Which bits in IIC_ISR are edge sensitive */
|
||||
IIC_ISR_EDGE_MASK = 0x4ul,
|
||||
};
|
||||
|
||||
extern void iic_init_IRQ(void);
|
||||
|
|
@ -52,7 +80,6 @@ extern void iic_request_IPIs(void);
|
|||
extern void iic_setup_cpu(void);
|
||||
|
||||
extern u8 iic_get_target_id(int cpu);
|
||||
extern struct irq_host *iic_get_irq_host(int node);
|
||||
|
||||
extern void spider_init_IRQ(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -243,7 +243,6 @@ static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
|
|||
const u32 *imap, *tmp;
|
||||
int imaplen, intsize, unit;
|
||||
struct device_node *iic;
|
||||
struct irq_host *iic_host;
|
||||
|
||||
#if 0 /* Enable that when we have a way to retreive the node as well */
|
||||
/* First, we check wether we have a real "interrupts" in the device
|
||||
|
|
@ -289,11 +288,11 @@ static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
|
|||
* the iic host from the iic OF node, but that way I'm still compatible
|
||||
* with really really old old firmwares for which we don't have a node
|
||||
*/
|
||||
iic_host = iic_get_irq_host(pic->node_id);
|
||||
if (iic_host == NULL)
|
||||
return NO_IRQ;
|
||||
/* Manufacture an IIC interrupt number of class 2 */
|
||||
virq = irq_create_mapping(iic_host, 0x20 | unit);
|
||||
virq = irq_create_mapping(NULL,
|
||||
(pic->node_id << IIC_IRQ_NODE_SHIFT) |
|
||||
(2 << IIC_IRQ_CLASS_SHIFT) |
|
||||
unit);
|
||||
if (virq == NO_IRQ)
|
||||
printk(KERN_ERR "spider_pic: failed to map cascade !");
|
||||
return virq;
|
||||
|
|
|
|||
|
|
@ -568,24 +568,23 @@ static void spu_unmap(struct spu *spu)
|
|||
/* This function shall be abstracted for HV platforms */
|
||||
static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
|
||||
{
|
||||
struct irq_host *host;
|
||||
unsigned int isrc;
|
||||
const u32 *tmp;
|
||||
|
||||
host = iic_get_irq_host(spu->node);
|
||||
if (host == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
/* Get the interrupt source from the device-tree */
|
||||
/* Get the interrupt source unit from the device-tree */
|
||||
tmp = get_property(np, "isrc", NULL);
|
||||
if (!tmp)
|
||||
return -ENODEV;
|
||||
spu->isrc = isrc = tmp[0];
|
||||
isrc = tmp[0];
|
||||
|
||||
/* Add the node number */
|
||||
isrc |= spu->node << IIC_IRQ_NODE_SHIFT;
|
||||
spu->isrc = isrc;
|
||||
|
||||
/* Now map interrupts of all 3 classes */
|
||||
spu->irqs[0] = irq_create_mapping(host, 0x00 | isrc);
|
||||
spu->irqs[1] = irq_create_mapping(host, 0x10 | isrc);
|
||||
spu->irqs[2] = irq_create_mapping(host, 0x20 | isrc);
|
||||
spu->irqs[0] = irq_create_mapping(NULL, IIC_IRQ_CLASS_0 | isrc);
|
||||
spu->irqs[1] = irq_create_mapping(NULL, IIC_IRQ_CLASS_1 | isrc);
|
||||
spu->irqs[2] = irq_create_mapping(NULL, IIC_IRQ_CLASS_2 | isrc);
|
||||
|
||||
/* Right now, we only fail if class 2 failed */
|
||||
return spu->irqs[2] == NO_IRQ ? -EINVAL : 0;
|
||||
|
|
|
|||
Loading…
Reference in a new issue