drm/radeon: add helper function to support golden registers
Golden registers are arrays of register settings from the hw team that need to be initialized at asic startup. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1946,6 +1946,9 @@ extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc
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extern int radeon_resume_kms(struct drm_device *dev);
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extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
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extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
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extern void radeon_program_register_sequence(struct radeon_device *rdev,
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const u32 *registers,
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const u32 array_size);
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/*
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* vm
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@ -97,6 +97,42 @@ static const char radeon_family_name[][16] = {
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"LAST",
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};
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/**
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* radeon_program_register_sequence - program an array of registers.
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*
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* @rdev: radeon_device pointer
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* @registers: pointer to the register array
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* @array_size: size of the register array
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*
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* Programs an array or registers with and and or masks.
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* This is a helper for setting golden registers.
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*/
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void radeon_program_register_sequence(struct radeon_device *rdev,
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const u32 *registers,
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const u32 array_size)
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{
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u32 tmp, reg, and_mask, or_mask;
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int i;
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if (array_size % 3)
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return;
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for (i = 0; i < array_size; i +=3) {
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reg = registers[i + 0];
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and_mask = registers[i + 1];
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or_mask = registers[i + 2];
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if (and_mask == 0xffffffff) {
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tmp = or_mask;
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} else {
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tmp = RREG32(reg);
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tmp &= ~and_mask;
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tmp |= or_mask;
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}
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WREG32(reg, tmp);
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}
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}
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/**
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* radeon_surface_init - Clear GPU surface registers.
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*
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