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drm/radeon: add helper function to support golden registers

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Golden registers are arrays of register settings from the
hw team that need to be initialized at asic startup.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-02-26 11:26:51 -05:00
parent 79b52d6a70
commit 2e1b65f98b
2 changed files with 39 additions and 0 deletions
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3
drivers/gpu/drm/radeon/radeon.h
View file

@ -1946,6 +1946,9 @@ extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc
extern int radeon_resume_kms(struct drm_device *dev);
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
extern void radeon_program_register_sequence(struct radeon_device *rdev,
const u32 *registers,
const u32 array_size);
/*
* vm

36
drivers/gpu/drm/radeon/radeon_device.c
View file

@ -97,6 +97,42 @@ static const char radeon_family_name[][16] = {
"LAST",
};
/**
* radeon_program_register_sequence - program an array of registers.
*
* @rdev: radeon_device pointer
* @registers: pointer to the register array
* @array_size: size of the register array
*
* Programs an array or registers with and and or masks.
* This is a helper for setting golden registers.
*/
void radeon_program_register_sequence(struct radeon_device *rdev,
const u32 *registers,
const u32 array_size)
{
u32 tmp, reg, and_mask, or_mask;
int i;
if (array_size % 3)
return;
for (i = 0; i < array_size; i +=3) {
reg = registers[i + 0];
and_mask = registers[i + 1];
or_mask = registers[i + 2];
if (and_mask == 0xffffffff) {
tmp = or_mask;
} else {
tmp = RREG32(reg);
tmp &= ~and_mask;
tmp |= or_mask;
}
WREG32(reg, tmp);
}
}
/**
* radeon_surface_init - Clear GPU surface registers.
*