Fixes for omaps against v4.6-rc1. Mostly minor fixes for the newer
SoCs with few board fixes and a fix for a long time hwmod bug: - Fix cpsw_emac0 link type for baltos-ir5221 - Fix interrupt type for TWD - Fix edma memcpy channel allocation for am43x - Fix am43x-epos sycntimer32k by using the correct assigned clock - Fix interconnect barrier for dra7 - Fix a long time hwmod bug for updating sysconfig register properly - Fix flakey booting on dm814x where USB reset needs a delay And there is one minor change that is not strictly a fix, but is good to have for proper hardware detection: - Detect dra7 silicon revision 2.0 properly -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW/pp4AAoJEBvUPslcq6VzqQgP/RjKTIdwRnpjUryPwxwMwQ52 gt9GjqMKvS3IvRyFewsjgTtoB/7l14qz3cVzurYeov+PekbqxnIJG1tVzltGVHQX WO13hzSV+Nuaf/4yFCCOcWSVtC4+26DvUCljfcUuxKiAsoXHrAIJJClHTtzqkXWK oJ5vipMKe166s7ULB9yKLoqU0wWBSsTqPK2IVjqdyF+eBcyy0BitJBembzWS6c8C FqhX3QOkU8PnzmUcJlVzqchA8ES7Cp2cgGnRcdFUV7A8gdBQrDDfAdJwb+CXhSYN 3Csd++gcU/J3N8Rsbdv1mOVaHjQ+SVk22iWGT9z6FDBzg+S3thknCpDpP9qipV+i vV1LsCydKRVvXJO3SN5Pykhdwmod5zw/FSPe+0xyVsk3zxe8jzF3TKWkIeS43POA 6e6DdhFfxI6u5BQydohOoMwDd/SzRQxA6IxZxpresDWeoE3Ffu4/ZyIhcUsZfcSK 0kVEc+ayQQnLfN5P1jQ5gWvxWXvQ/p7DBfnDL+kfyShjFHJo5ZO51IVr1rNfdIQc fvtklMI82E4lf3qsRtHxrfPUuigWJcslfoQEJ7B3NVyXP7VXmB2iuKRUEI8QuvU4 AxXwp5qmKVvnUoXNIsX9PGL9FLTokAFJ8YWPvjFOIIHP0JphZ/AEMhgVwbW7Ze6/ VGjsmATRQqXSYqavc4No =5fhs -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.6/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Fixes for omaps against v4.6-rc1. Mostly minor fixes for the newer SoCs with few board fixes and a fix for a long time hwmod bug: - Fix cpsw_emac0 link type for baltos-ir5221 - Fix interrupt type for TWD - Fix edma memcpy channel allocation for am43x - Fix am43x-epos sycntimer32k by using the correct assigned clock - Fix interconnect barrier for dra7 - Fix a long time hwmod bug for updating sysconfig register properly - Fix flakey booting on dm814x where USB reset needs a delay And there is one minor change that is not strictly a fix, but is good to have for proper hardware detection: - Detect dra7 silicon revision 2.0 properly * tag 'omap-for-v4.6/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type ARM: OMAP: Correct interrupt type for ARM TWD ARM: DRA722: Add ID detect for Silicon Rev 2.0 ARM: dts: am43xx: fix edma memcpy channel allocation ARM: dts: AM43x-epos: Fix clk parent for synctimer ARM: OMAP2: Fix up interconnect barrier initialization for DRA7 ARM: OMAP2+: hwmod: Fix updating of sysconfig register ARM: OMAP2+: Use srst_udelay for USB on dm814x Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
2e1d18c699
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@ -470,9 +470,12 @@
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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phy-mode = "rmii";
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dual_emac_res_vlan = <1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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&cpsw_emac1 {
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@ -207,7 +207,7 @@
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <32 33>;
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ti,edma-memcpy-channels = <58 59>;
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};
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edma_tptc0: tptc@49800000 {
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@ -794,3 +794,8 @@
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tx-num-evt = <32>;
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rx-num-evt = <32>;
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};
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&synctimer_32kclk {
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assigned-clocks = <&mux_synctimer32k_ck>;
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assigned-clock-parents = <&clkdiv32k_ick>;
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};
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@ -70,7 +70,7 @@
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compatible = "arm,cortex-a9-twd-timer";
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clocks = <&mpu_periphclk>;
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reg = <0x48240600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
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interrupt-parent = <&gic>;
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};
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@ -669,9 +669,9 @@ void __init dra7xxx_check_revision(void)
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case 0:
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omap_revision = DRA722_REV_ES1_0;
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break;
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case 1:
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default:
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/* If we have no new revisions */
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omap_revision = DRA722_REV_ES1_0;
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omap_revision = DRA722_REV_ES2_0;
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break;
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}
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break;
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@ -368,6 +368,7 @@ void __init omap5_map_io(void)
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void __init dra7xx_map_io(void)
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{
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iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
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omap_barriers_init();
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}
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#endif
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/*
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@ -1416,9 +1416,7 @@ static void _enable_sysc(struct omap_hwmod *oh)
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(sf & SYSC_HAS_CLOCKACTIVITY))
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_set_clockactivity(oh, oh->class->sysc->clockact, &v);
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/* If the cached value is the same as the new value, skip the write */
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if (oh->_sysc_cache != v)
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_write_sysconfig(v, oh);
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_write_sysconfig(v, oh);
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/*
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* Set the autoidle bit only after setting the smartidle bit
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@ -1481,7 +1479,9 @@ static void _idle_sysc(struct omap_hwmod *oh)
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_set_master_standbymode(oh, idlemode, &v);
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}
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_write_sysconfig(v, oh);
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/* If the cached value is the same as the new value, skip the write */
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if (oh->_sysc_cache != v)
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_write_sysconfig(v, oh);
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}
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/**
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@ -582,9 +582,11 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
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.user = OCP_USER_MPU,
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};
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/* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
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static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x10,
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.srst_udelay = 2,
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.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SOFTRESET,
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.idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
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@ -489,6 +489,7 @@ IS_OMAP_TYPE(3430, 0x3430)
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#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
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#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
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#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
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#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8))
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void omap2xxx_check_revision(void);
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void omap3xxx_check_revision(void);
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