dmaengine: dw: revisit data_width property
There several changes are done here: - Convert the property to be in bytes Besides that this is a common practice for such property, the use of a value in bytes much more convenient than handling the encoded one. - Rename data_width to data-width in the device tree bindings The change leaves the support for the old format as well just in case someone will use a newer kernel with an old device tree blob. - While here, replace dwc_fast_ffs() by __ffs() Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>hifive-unleashed-5.1
Andy Shevchenko
Vinod Koul
parent
969f750fc6
commit
2e65060e80
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@ -13,6 +13,11 @@ Required properties:
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- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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increase from chan n->0
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- block_size: Maximum block size supported by the controller
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- data-width: Maximum data width supported by hardware per AHB master
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(in bytes, power of 2)
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Deprecated properties:
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- data_width: Maximum data width supported by hardware per AHB master
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(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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@ -38,7 +43,7 @@ Example:
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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data_width = <3 3>;
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data-width = <8 8>;
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};
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DMA clients connected to the Designware DMA controller must use the format
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@ -112,7 +112,7 @@
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chan_allocation_order = <0>;
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chan_priority = <1>;
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block_size = <0x7ff>;
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data_width = <2>;
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data-width = <4>;
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clocks = <&ahb_clk>;
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clock-names = "hclk";
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};
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@ -117,7 +117,7 @@
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chan_priority = <1>;
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block_size = <0xfff>;
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dma-masters = <2>;
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data_width = <3 3>;
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data-width = <8 8>;
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};
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dma@eb000000 {
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@ -133,7 +133,7 @@
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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data_width = <3 3>;
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data-width = <8 8>;
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};
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fsmc: flash@b0000000 {
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@ -162,21 +162,6 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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/*----------------------------------------------------------------------*/
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static inline unsigned int dwc_fast_ffs(unsigned long long v)
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{
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/*
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* We can be a lot more clever here, but this should take care
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* of the most common optimization.
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*/
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if (!(v & 7))
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return 3;
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else if (!(v & 3))
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return 2;
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else if (!(v & 1))
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return 1;
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return 0;
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}
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static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
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{
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dev_err(chan2dev(&dwc->chan),
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@ -677,11 +662,12 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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struct dw_desc *prev;
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size_t xfer_count;
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size_t offset;
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u8 m_master = dwc->m_master;
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unsigned int src_width;
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unsigned int dst_width;
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unsigned int data_width;
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unsigned int data_width = dw->data_width[m_master];
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u32 ctllo;
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u8 lms = DWC_LLP_LMS(dwc->m_master);
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u8 lms = DWC_LLP_LMS(m_master);
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dev_vdbg(chan2dev(chan),
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"%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
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@ -694,10 +680,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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dwc->direction = DMA_MEM_TO_MEM;
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data_width = dw->data_width[dwc->m_master];
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src_width = dst_width = min_t(unsigned int, data_width,
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dwc_fast_ffs(src | dest | len));
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src_width = dst_width = __ffs(data_width | src | dest | len);
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ctllo = DWC_DEFAULT_CTLLO(chan)
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| DWC_CTLL_DST_WIDTH(dst_width)
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@ -757,11 +740,12 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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struct dw_desc *prev;
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struct dw_desc *first;
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u32 ctllo;
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u8 lms = DWC_LLP_LMS(dwc->m_master);
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u8 m_master = dwc->m_master;
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u8 lms = DWC_LLP_LMS(m_master);
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dma_addr_t reg;
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unsigned int reg_width;
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unsigned int mem_width;
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unsigned int data_width;
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unsigned int data_width = dw->data_width[m_master];
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unsigned int i;
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struct scatterlist *sg;
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size_t total_len = 0;
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@ -787,8 +771,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
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DWC_CTLL_FC(DW_DMA_FC_D_M2P);
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data_width = dw->data_width[dwc->m_master];
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for_each_sg(sgl, sg, sg_len, i) {
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struct dw_desc *desc;
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u32 len, dlen, mem;
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@ -796,8 +778,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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mem = sg_dma_address(sg);
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len = sg_dma_len(sg);
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mem_width = min_t(unsigned int,
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data_width, dwc_fast_ffs(mem | len));
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mem_width = __ffs(data_width | mem | len);
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slave_sg_todev_fill_desc:
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desc = dwc_desc_get(dwc);
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@ -843,8 +824,6 @@ slave_sg_todev_fill_desc:
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
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DWC_CTLL_FC(DW_DMA_FC_D_P2M);
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data_width = dw->data_width[dwc->m_master];
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for_each_sg(sgl, sg, sg_len, i) {
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struct dw_desc *desc;
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u32 len, dlen, mem;
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@ -852,8 +831,7 @@ slave_sg_todev_fill_desc:
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mem = sg_dma_address(sg);
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len = sg_dma_len(sg);
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mem_width = min_t(unsigned int,
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data_width, dwc_fast_ffs(mem | len));
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mem_width = __ffs(data_width | mem | len);
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slave_sg_fromdev_fill_desc:
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desc = dwc_desc_get(dwc);
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@ -1500,7 +1478,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
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for (i = 0; i < pdata->nr_masters; i++) {
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pdata->data_width[i] =
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(dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
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4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
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}
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max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
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@ -138,9 +138,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
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if (!of_property_read_u32(np, "block_size", &tmp))
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pdata->block_size = tmp;
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if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
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if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) {
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for (tmp = 0; tmp < nr_masters; tmp++)
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pdata->data_width[tmp] = arr[tmp];
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} else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
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for (tmp = 0; tmp < nr_masters; tmp++)
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pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
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}
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return pdata;
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@ -43,7 +43,7 @@ struct dw_dma_slave {
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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* (in bytes, power of 2)
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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