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drm/i915/execlists: Relax the locked clear_bit(IRQ_EXECLIST) 

We only need to care about the ordering of the clearing of the bit with
the uncached CSB read in order to correctly detect a new interrupt
before the read completes. The uncached read itself acts as a full
memory barrier, so we do not need to enforce another in the form of a
locked clear_bit.

v2: Clarify why the split and unlocked test/clear is harmless.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170323134803.10418-1-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
hifive-unleashed-5.1
Chris Wilson 2017-03-23 13:48:03 +00:00
parent 292889e1ff
commit 2e70b8c6bf
1 changed files with 11 additions and 1 deletions
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12
drivers/gpu/drm/i915/intel_lrc.c
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@ -540,7 +540,17 @@ static void intel_lrc_irq_handler(unsigned long data)
dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
unsigned int csb, head, tail;
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
/* The write will be ordered by the uncached read (itself
* a memory barrier), so we do not need another in the form
* of a locked instruction. The race between the interrupt
* handler and the split test/clear is harmless as we order
* our clear before the CSB read. If the interrupt arrived
* first between the test and the clear, we read the updated
* CSB and clear the bit. If the interrupt arrives as we read
* the CSB or later (i.e. after we had cleared the bit) the bit
* is set and we do a new loop.
*/
__clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
csb = readl(csb_mmio);
head = GEN8_CSB_READ_PTR(csb);
tail = GEN8_CSB_WRITE_PTR(csb);