drm/radeon/kms: flush HDP cache on GART table updates.
Suggested by Alex Deucher @ AMD Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
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unsigned i;
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u32 tmp;
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/* flush hdp cache so updates hit vram */
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WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
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WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
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WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
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