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drm/radeon/kms: flush HDP cache on GART table updates.

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Suggested by Alex Deucher @ AMD

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2010-02-15 15:54:45 +10:00
parent 7cb72ef4d3
commit 2e98f10a7a
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/radeon/r600.c
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@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
unsigned i;
u32 tmp;
/* flush hdp cache so updates hit vram */
WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));