openrisc: entry: Whitespace and comment cleanups
Cleanups to whitespace and add some comments. Reading through the delay slot logic I noticed some things: - Delay slot instructions were not indented - Some comments are not lined up - Use tabs and spaces consistent with other code No functional change Signed-off-by: Stafford Horne <shorne@gmail.com>hifive-unleashed-5.1
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f72deab378
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2ead7aba44
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@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
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* DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
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* DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
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*/
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*/
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#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
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#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
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l.lwz r6,PT_PC(r3) // address of an offending insn
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l.lwz r6,PT_PC(r3) // address of an offending insn
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l.lwz r6,0(r6) // instruction that caused pf
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l.lwz r6,0(r6) // instruction that caused pf
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l.srli r6,r6,26 // check opcode for jump insn
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l.srli r6,r6,26 // check opcode for jump insn
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@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
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l.bf 8f
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l.bf 8f
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l.sfeqi r6,0x12 // l.jalr
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l.sfeqi r6,0x12 // l.jalr
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l.bf 8f
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l.bf 8f
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l.nop
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l.nop
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l.j 9f
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l.j 9f
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l.nop
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l.nop
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8:
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l.lwz r6,PT_PC(r3) // address of an offending insn
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8: // offending insn is in delay slot
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l.lwz r6,PT_PC(r3) // address of an offending insn
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l.addi r6,r6,4
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l.addi r6,r6,4
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l.lwz r6,0(r6) // instruction that caused pf
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l.lwz r6,0(r6) // instruction that caused pf
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l.srli r6,r6,26 // get opcode
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l.srli r6,r6,26 // get opcode
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9:
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9: // offending instruction opcode loaded in r6
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#else
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#else
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l.mfspr r6,r0,SPR_SR // SR
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l.mfspr r6,r0,SPR_SR // SR
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// l.lwz r6,PT_SR(r3) // ESR
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l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
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l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
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l.sfeqi r6,0x1 // exception happened in delay slot
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l.sfeqi r6,0x1 // exception happened in delay slot
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l.bnf 7f
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l.bnf 7f
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l.lwz r6,PT_PC(r3) // address of an offending insn
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l.lwz r6,PT_PC(r3) // address of an offending insn
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l.addi r6,r6,4 // offending insn is in delay slot
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l.addi r6,r6,4 // offending insn is in delay slot
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7:
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7:
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l.lwz r6,0(r6) // instruction that caused pf
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l.lwz r6,0(r6) // instruction that caused pf
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l.srli r6,r6,26 // check opcode for write access
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l.srli r6,r6,26 // check opcode for write access
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#endif
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#endif
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l.sfgeui r6,0x33 // check opcode for write access
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l.sfgeui r6,0x33 // check opcode for write access
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l.bnf 1f
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l.bnf 1f
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l.sfleui r6,0x37
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l.sfleui r6,0x37
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l.bnf 1f
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l.bnf 1f
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l.ori r6,r0,0x1 // write access
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l.ori r6,r0,0x1 // write access
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l.j 2f
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l.j 2f
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l.nop
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l.nop
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1: l.ori r6,r0,0x0 // !write access
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1: l.ori r6,r0,0x0 // !write access
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2:
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2:
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/* call fault.c handler in or32/mm/fault.c */
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/* call fault.c handler in or32/mm/fault.c */
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l.jal do_page_fault
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l.jal do_page_fault
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l.nop
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l.nop
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l.j _ret_from_exception
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l.j _ret_from_exception
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l.nop
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l.nop
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/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
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/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
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EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
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EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
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@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler)
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/* call fault.c handler in or32/mm/fault.c */
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/* call fault.c handler in or32/mm/fault.c */
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l.jal do_page_fault
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l.jal do_page_fault
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l.nop
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l.nop
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l.j _ret_from_exception
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l.j _ret_from_exception
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l.nop
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l.nop
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/* ---[ 0x500: Timer exception ]----------------------------------------- */
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/* ---[ 0x500: Timer exception ]----------------------------------------- */
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