Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Just a few fixes for 4.6 this week: - Add some SI DPM quirks - Improve the ACP Kconfig text - Additional BO pinning checks * 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: Don't move pinned BOs drm/radeon: Don't move pinned BOs drm/radeon: add a dpm quirk for all R7 370 parts drm/radeon: add another R7 370 quirk drm/radeon: add a dpm quirk for sapphire Dual-X R7 370 2G D5 drm/amd: Beef up ACP Kconfig menu text
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2f4fcb3eaf
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@ -1,10 +1,14 @@
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menu "ACP Configuration"
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menu "ACP (Audio CoProcessor) Configuration"
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config DRM_AMD_ACP
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config DRM_AMD_ACP
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bool "Enable ACP IP support"
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bool "Enable AMD Audio CoProcessor IP support"
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select MFD_CORE
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select MFD_CORE
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select PM_GENERIC_DOMAINS if PM
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select PM_GENERIC_DOMAINS if PM
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help
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help
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Choose this option to enable ACP IP support for AMD SOCs.
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Choose this option to enable ACP IP support for AMD SOCs.
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This adds the ACP (Audio CoProcessor) IP driver and wires
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it up into the amdgpu driver. The ACP block provides the DMA
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engine for the i2s-based ALSA driver. It is required for audio
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on APUs which utilize an i2s codec.
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endmenu
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endmenu
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@ -608,6 +608,10 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
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if ((offset + size) <= adev->mc.visible_vram_size)
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if ((offset + size) <= adev->mc.visible_vram_size)
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return 0;
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return 0;
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/* Can't move a pinned BO to visible VRAM */
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if (abo->pin_count > 0)
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return -EINVAL;
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/* hurrah the memory is not visible ! */
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/* hurrah the memory is not visible ! */
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
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lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
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lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
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@ -384,9 +384,15 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem)
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struct ttm_mem_reg *new_mem)
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{
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{
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struct amdgpu_device *adev;
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struct amdgpu_device *adev;
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struct amdgpu_bo *abo;
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct ttm_mem_reg *old_mem = &bo->mem;
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int r;
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int r;
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/* Can't move a pinned BO */
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abo = container_of(bo, struct amdgpu_bo, tbo);
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if (WARN_ON_ONCE(abo->pin_count > 0))
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return -EINVAL;
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adev = amdgpu_get_adev(bo->bdev);
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adev = amdgpu_get_adev(bo->bdev);
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if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
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if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
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amdgpu_move_null(bo, new_mem);
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amdgpu_move_null(bo, new_mem);
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@ -799,6 +799,10 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
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if ((offset + size) <= rdev->mc.visible_vram_size)
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if ((offset + size) <= rdev->mc.visible_vram_size)
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return 0;
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return 0;
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/* Can't move a pinned BO to visible VRAM */
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if (rbo->pin_count > 0)
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return -EINVAL;
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/* hurrah the memory is not visible ! */
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/* hurrah the memory is not visible ! */
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
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lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
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lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
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@ -397,9 +397,15 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem)
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struct ttm_mem_reg *new_mem)
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{
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{
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struct radeon_device *rdev;
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struct radeon_device *rdev;
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struct radeon_bo *rbo;
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struct ttm_mem_reg *old_mem = &bo->mem;
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struct ttm_mem_reg *old_mem = &bo->mem;
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int r;
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int r;
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/* Can't move a pinned BO */
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rbo = container_of(bo, struct radeon_bo, tbo);
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if (WARN_ON_ONCE(rbo->pin_count > 0))
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return -EINVAL;
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rdev = radeon_get_rdev(bo->bdev);
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rdev = radeon_get_rdev(bo->bdev);
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if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
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if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
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radeon_move_null(bo, new_mem);
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radeon_move_null(bo, new_mem);
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@ -2926,9 +2926,11 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = {
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/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
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/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
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{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
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{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
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{ 0, 0, 0, 0 },
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{ 0, 0, 0, 0 },
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};
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};
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@ -3008,6 +3010,10 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
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}
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}
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++p;
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++p;
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}
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}
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/* limit mclk on all R7 370 parts for stability */
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if (rdev->pdev->device == 0x6811 &&
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rdev->pdev->revision == 0x81)
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max_mclk = 120000;
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if (rps->vce_active) {
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if (rps->vce_active) {
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rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
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rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
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