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ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15 

When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
hifive-unleashed-5.1
Joseph Lo 2013-07-03 17:50:39 +08:00 committed by Stephen Warren
parent ac2527bfc2
commit 2f5aaa3d27
2 changed files with 23 additions and 0 deletions
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1
arch/arm/mach-tegra/reset-handler.S
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@ -45,6 +45,7 @@
ENTRY(tegra_resume)
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
blne tegra_init_l2_for_a15
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6

22
arch/arm/mach-tegra/sleep.S
View File

@ -68,6 +68,28 @@ ENDPROC(tegra_disable_clean_inv_dcache)
#endif
#ifdef CONFIG_PM_SLEEP
/*
* tegra_init_l2_for_a15
*
* set up the correct L2 cache data RAM latency
*/
ENTRY(tegra_init_l2_for_a15)
mrc p15, 0, r0, c0, c0, 5
ubfx r0, r0, #8, #4
tst r0, #1 @ only need for cluster 0
bne _exit_init_l2_a15
mrc p15, 0x1, r0, c9, c0, 2
and r0, r0, #7
cmp r0, #2
bicne r0, r0, #7
orrne r0, r0, #2
mcrne p15, 0x1, r0, c9, c0, 2
_exit_init_l2_a15:
mov pc, lr
ENDPROC(tegra_init_l2_for_a15)
/*
* tegra_sleep_cpu_finish(unsigned long v2p)
*