ARM: plat-nomadik: timer: Add support for periodic timers
This adds support for a periodic mode in the MTU (Nomadik) timer clockevent driver. It also include changes needed for deeper powerstates where MTU block gets powered off. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.1
Jonas Aaberg
Linus Walleij
parent
5f5663a436
commit
2f73a06843
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@ -23,7 +23,12 @@
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#include <plat/mtu.h>
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static bool clkevt_periodic;
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static u32 clk_prescale;
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static u32 nmdk_cycle; /* write-once */
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void __iomem *mtu_base; /* Assigned by machine code */
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#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
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/*
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* Override the global weak sched_clock symbol with this
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@ -49,31 +54,55 @@ static void notrace nomadik_update_sched_clock(void)
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update_sched_clock(&cd, cyc, (u32)~0);
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}
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#endif
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/* Clockevent device: use one-shot mode */
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static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
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{
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writel(1 << 1, mtu_base + MTU_IMSC);
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writel(evt, mtu_base + MTU_LR(1));
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/* Load highest value, enable device, enable interrupts */
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writel(MTU_CRn_ONESHOT | clk_prescale |
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MTU_CRn_32BITS | MTU_CRn_ENA,
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mtu_base + MTU_CR(1));
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return 0;
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}
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static void nmdk_clkevt_reset(void)
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{
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if (clkevt_periodic) {
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/* Timer: configure load and background-load, and fire it up */
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writel(nmdk_cycle, mtu_base + MTU_LR(1));
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writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
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writel(MTU_CRn_PERIODIC | clk_prescale |
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MTU_CRn_32BITS | MTU_CRn_ENA,
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mtu_base + MTU_CR(1));
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writel(1 << 1, mtu_base + MTU_IMSC);
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} else {
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/* Generate an interrupt to start the clockevent again */
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(void) nmdk_clkevt_next(nmdk_cycle, NULL);
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}
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}
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static void nmdk_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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u32 cr;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_err("%s: periodic mode not supported\n", __func__);
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clkevt_periodic = true;
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nmdk_clkevt_reset();
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Load highest value, enable device, enable interrupts */
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cr = readl(mtu_base + MTU_CR(1));
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writel(0, mtu_base + MTU_LR(1));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
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writel(1 << 1, mtu_base + MTU_IMSC);
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clkevt_periodic = false;
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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/* disable irq */
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writel(0, mtu_base + MTU_IMSC);
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/* disable timer */
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cr = readl(mtu_base + MTU_CR(1));
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cr &= ~MTU_CRn_ENA;
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writel(cr, mtu_base + MTU_CR(1));
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writel(0, mtu_base + MTU_CR(1));
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/* load some high default value */
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writel(0xffffffff, mtu_base + MTU_LR(1));
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break;
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@ -82,16 +111,9 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
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}
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}
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static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
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{
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/* writing the value has immediate effect */
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writel(evt, mtu_base + MTU_LR(1));
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return 0;
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}
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static struct clock_event_device nmdk_clkevt = {
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.name = "mtu_1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.rating = 200,
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.set_mode = nmdk_clkevt_mode,
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.set_next_event = nmdk_clkevt_next,
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@ -116,11 +138,23 @@ static struct irqaction nmdk_timer_irq = {
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.dev_id = &nmdk_clkevt,
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};
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static void nmdk_clksrc_reset(void)
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{
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/* Disable */
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writel(0, mtu_base + MTU_CR(0));
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/* ClockSource: configure load and background-load, and fire it up */
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writel(nmdk_cycle, mtu_base + MTU_LR(0));
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writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
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writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
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mtu_base + MTU_CR(0));
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}
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void __init nmdk_timer_init(void)
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{
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unsigned long rate;
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struct clk *clk0;
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u32 cr = MTU_CRn_32BITS;
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clk0 = clk_get_sys("mtu0", NULL);
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BUG_ON(IS_ERR(clk0));
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@ -138,16 +172,16 @@ void __init nmdk_timer_init(void)
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rate = clk_get_rate(clk0);
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if (rate > 32000000) {
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rate /= 16;
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cr |= MTU_CRn_PRESCALE_16;
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clk_prescale = MTU_CRn_PRESCALE_16;
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} else {
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cr |= MTU_CRn_PRESCALE_1;
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clk_prescale = MTU_CRn_PRESCALE_1;
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}
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nmdk_cycle = (rate + HZ/2) / HZ;
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/* Timer 0 is the free running clocksource */
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writel(cr, mtu_base + MTU_CR(0));
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writel(0, mtu_base + MTU_LR(0));
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writel(0, mtu_base + MTU_BGLR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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nmdk_clksrc_reset();
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if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
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rate, 200, 32, clocksource_mmio_readl_down))
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@ -160,8 +194,6 @@ void __init nmdk_timer_init(void)
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clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
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writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
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nmdk_clkevt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
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nmdk_clkevt.min_delta_ns =
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