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[PATCH] x86-64: - Ignore long SMI interrupts in clock calibration code - update 1 

Add failsafe mechanism to HPET/TSC clock calibration.

	Signed-off-by: Jack Steiner <steiner@sgi.com>

Updated to include failsafe mechanism & additional community feedback.
Patch built on latest 2.6.20-rc4-mm1 tree.

Signed-off-by: Andi Kleen <ak@suse.de>
hifive-unleashed-5.1
Jack Steiner 2007-02-13 13:26:24 +01:00 committed by Andi Kleen
parent 6c5806cae5
commit 2f7a2a79c3
1 changed files with 7 additions and 2 deletions
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9
arch/x86_64/kernel/time.c
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@ -657,6 +657,7 @@ core_initcall(cpufreq_tsc);
#define TICK_COUNT 100000000
#define TICK_MIN 5000
#define MAX_READ_RETRIES 5
/*
* Some platforms take periodic SMI interrupts with 5ms duration. Make sure none
@ -664,13 +665,17 @@ core_initcall(cpufreq_tsc);
*/
static void __init read_hpet_tsc(int *hpet, int *tsc)
{
int tsc1, tsc2, hpet1;
int tsc1, tsc2, hpet1, retries = 0;
static int msg;
do {
tsc1 = get_cycles_sync();
hpet1 = hpet_readl(HPET_COUNTER);
tsc2 = get_cycles_sync();
} while (tsc2 - tsc1 > TICK_MIN);
} while (tsc2 - tsc1 > TICK_MIN && retries++ < MAX_READ_RETRIES);
if (retries >= MAX_READ_RETRIES && !msg++)
printk(KERN_WARNING
"hpet.c: exceeded max retries to read HPET & TSC\n");
*hpet = hpet1;
*tsc = tsc2;
}