NTB: Rename Intel code names to platform names
Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>hifive-unleashed-5.1
Dave Jiang
Jon Mason
parent
a41ef053f7
commit
2f887b9a44
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@ -115,13 +115,13 @@ Module Parameters:
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* b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if
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the memory window is large enough, still allow the client to use the
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second half of the memory window for address translation to the peer.
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* snb\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use this
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64 bit address on the bus between the NTB devices for the window at
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BAR2, on the upstream side of the link.
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* snb\_b2b\_usd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_usd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_usd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_dsd\_bar2\_addr64 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_dsd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_dsd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*.
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* snb\_b2b\_dsd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use
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this 64 bit address on the bus between the NTB devices for the window
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at BAR2, on the upstream side of the link.
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* xeon\_b2b\_usd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_usd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_usd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_dsd\_bar2\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_dsd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_dsd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
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* xeon\_b2b\_dsd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
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File diff suppressed because it is too large
Load Diff
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@ -68,141 +68,141 @@
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#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
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/* SNB hardware (and JSF, IVT, HSX) */
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/* Intel Xeon hardware */
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#define SNB_PBAR23LMT_OFFSET 0x0000
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#define SNB_PBAR45LMT_OFFSET 0x0008
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#define SNB_PBAR4LMT_OFFSET 0x0008
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#define SNB_PBAR5LMT_OFFSET 0x000c
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#define SNB_PBAR23XLAT_OFFSET 0x0010
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#define SNB_PBAR45XLAT_OFFSET 0x0018
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#define SNB_PBAR4XLAT_OFFSET 0x0018
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#define SNB_PBAR5XLAT_OFFSET 0x001c
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#define SNB_SBAR23LMT_OFFSET 0x0020
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#define SNB_SBAR45LMT_OFFSET 0x0028
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#define SNB_SBAR4LMT_OFFSET 0x0028
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#define SNB_SBAR5LMT_OFFSET 0x002c
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#define SNB_SBAR23XLAT_OFFSET 0x0030
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#define SNB_SBAR45XLAT_OFFSET 0x0038
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#define SNB_SBAR4XLAT_OFFSET 0x0038
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#define SNB_SBAR5XLAT_OFFSET 0x003c
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#define SNB_SBAR0BASE_OFFSET 0x0040
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#define SNB_SBAR23BASE_OFFSET 0x0048
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#define SNB_SBAR45BASE_OFFSET 0x0050
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#define SNB_SBAR4BASE_OFFSET 0x0050
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#define SNB_SBAR5BASE_OFFSET 0x0054
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#define SNB_SBDF_OFFSET 0x005c
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#define SNB_NTBCNTL_OFFSET 0x0058
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#define SNB_PDOORBELL_OFFSET 0x0060
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#define SNB_PDBMSK_OFFSET 0x0062
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#define SNB_SDOORBELL_OFFSET 0x0064
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#define SNB_SDBMSK_OFFSET 0x0066
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#define SNB_USMEMMISS_OFFSET 0x0070
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#define SNB_SPAD_OFFSET 0x0080
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#define SNB_PBAR23SZ_OFFSET 0x00d0
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#define SNB_PBAR45SZ_OFFSET 0x00d1
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#define SNB_PBAR4SZ_OFFSET 0x00d1
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#define SNB_SBAR23SZ_OFFSET 0x00d2
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#define SNB_SBAR45SZ_OFFSET 0x00d3
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#define SNB_SBAR4SZ_OFFSET 0x00d3
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#define SNB_PPD_OFFSET 0x00d4
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#define SNB_PBAR5SZ_OFFSET 0x00d5
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#define SNB_SBAR5SZ_OFFSET 0x00d6
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#define SNB_WCCNTRL_OFFSET 0x00e0
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#define SNB_UNCERRSTS_OFFSET 0x014c
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#define SNB_CORERRSTS_OFFSET 0x0158
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#define SNB_LINK_STATUS_OFFSET 0x01a2
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#define SNB_SPCICMD_OFFSET 0x0504
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#define SNB_DEVCTRL_OFFSET 0x0598
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#define SNB_DEVSTS_OFFSET 0x059a
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#define SNB_SLINK_STATUS_OFFSET 0x05a2
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#define SNB_B2B_SPAD_OFFSET 0x0100
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#define SNB_B2B_DOORBELL_OFFSET 0x0140
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#define SNB_B2B_XLAT_OFFSETL 0x0144
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#define SNB_B2B_XLAT_OFFSETU 0x0148
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#define SNB_PPD_CONN_MASK 0x03
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#define SNB_PPD_CONN_TRANSPARENT 0x00
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#define SNB_PPD_CONN_B2B 0x01
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#define SNB_PPD_CONN_RP 0x02
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#define SNB_PPD_DEV_MASK 0x10
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#define SNB_PPD_DEV_USD 0x00
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#define SNB_PPD_DEV_DSD 0x10
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#define SNB_PPD_SPLIT_BAR_MASK 0x40
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#define XEON_PBAR23LMT_OFFSET 0x0000
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#define XEON_PBAR45LMT_OFFSET 0x0008
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#define XEON_PBAR4LMT_OFFSET 0x0008
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#define XEON_PBAR5LMT_OFFSET 0x000c
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#define XEON_PBAR23XLAT_OFFSET 0x0010
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#define XEON_PBAR45XLAT_OFFSET 0x0018
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#define XEON_PBAR4XLAT_OFFSET 0x0018
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#define XEON_PBAR5XLAT_OFFSET 0x001c
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#define XEON_SBAR23LMT_OFFSET 0x0020
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#define XEON_SBAR45LMT_OFFSET 0x0028
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#define XEON_SBAR4LMT_OFFSET 0x0028
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#define XEON_SBAR5LMT_OFFSET 0x002c
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#define XEON_SBAR23XLAT_OFFSET 0x0030
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#define XEON_SBAR45XLAT_OFFSET 0x0038
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#define XEON_SBAR4XLAT_OFFSET 0x0038
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#define XEON_SBAR5XLAT_OFFSET 0x003c
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#define XEON_SBAR0BASE_OFFSET 0x0040
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#define XEON_SBAR23BASE_OFFSET 0x0048
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#define XEON_SBAR45BASE_OFFSET 0x0050
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#define XEON_SBAR4BASE_OFFSET 0x0050
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#define XEON_SBAR5BASE_OFFSET 0x0054
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#define XEON_SBDF_OFFSET 0x005c
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#define XEON_NTBCNTL_OFFSET 0x0058
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#define XEON_PDOORBELL_OFFSET 0x0060
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#define XEON_PDBMSK_OFFSET 0x0062
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#define XEON_SDOORBELL_OFFSET 0x0064
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#define XEON_SDBMSK_OFFSET 0x0066
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#define XEON_USMEMMISS_OFFSET 0x0070
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#define XEON_SPAD_OFFSET 0x0080
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#define XEON_PBAR23SZ_OFFSET 0x00d0
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#define XEON_PBAR45SZ_OFFSET 0x00d1
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#define XEON_PBAR4SZ_OFFSET 0x00d1
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#define XEON_SBAR23SZ_OFFSET 0x00d2
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#define XEON_SBAR45SZ_OFFSET 0x00d3
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#define XEON_SBAR4SZ_OFFSET 0x00d3
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#define XEON_PPD_OFFSET 0x00d4
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#define XEON_PBAR5SZ_OFFSET 0x00d5
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#define XEON_SBAR5SZ_OFFSET 0x00d6
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#define XEON_WCCNTRL_OFFSET 0x00e0
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_SPCICMD_OFFSET 0x0504
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#define XEON_DEVCTRL_OFFSET 0x0598
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#define XEON_DEVSTS_OFFSET 0x059a
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#define XEON_SLINK_STATUS_OFFSET 0x05a2
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#define XEON_B2B_SPAD_OFFSET 0x0100
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#define XEON_B2B_DOORBELL_OFFSET 0x0140
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#define XEON_B2B_XLAT_OFFSETL 0x0144
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#define XEON_B2B_XLAT_OFFSETU 0x0148
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#define XEON_PPD_CONN_MASK 0x03
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#define XEON_PPD_CONN_TRANSPARENT 0x00
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#define XEON_PPD_CONN_B2B 0x01
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#define XEON_PPD_CONN_RP 0x02
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#define XEON_PPD_DEV_MASK 0x10
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#define XEON_PPD_DEV_USD 0x00
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#define XEON_PPD_DEV_DSD 0x10
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#define XEON_PPD_SPLIT_BAR_MASK 0x40
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#define SNB_PPD_TOPO_MASK (SNB_PPD_CONN_MASK | SNB_PPD_DEV_MASK)
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#define SNB_PPD_TOPO_PRI_USD (SNB_PPD_CONN_RP | SNB_PPD_DEV_USD)
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#define SNB_PPD_TOPO_PRI_DSD (SNB_PPD_CONN_RP | SNB_PPD_DEV_DSD)
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#define SNB_PPD_TOPO_SEC_USD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_USD)
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#define SNB_PPD_TOPO_SEC_DSD (SNB_PPD_CONN_TRANSPARENT | SNB_PPD_DEV_DSD)
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#define SNB_PPD_TOPO_B2B_USD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_USD)
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#define SNB_PPD_TOPO_B2B_DSD (SNB_PPD_CONN_B2B | SNB_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
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#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
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#define SNB_MW_COUNT 2
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#define XEON_MW_COUNT 2
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#define HSX_SPLIT_BAR_MW_COUNT 3
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#define SNB_DB_COUNT 15
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#define SNB_DB_LINK 15
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#define SNB_DB_LINK_BIT BIT_ULL(SNB_DB_LINK)
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#define SNB_DB_MSIX_VECTOR_COUNT 4
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#define SNB_DB_MSIX_VECTOR_SHIFT 5
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#define SNB_DB_TOTAL_SHIFT 16
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#define SNB_SPAD_COUNT 16
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#define XEON_DB_COUNT 15
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#define XEON_DB_LINK 15
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#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
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#define XEON_DB_MSIX_VECTOR_COUNT 4
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#define XEON_DB_MSIX_VECTOR_SHIFT 5
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#define XEON_DB_TOTAL_SHIFT 16
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#define XEON_SPAD_COUNT 16
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/* BWD hardware */
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/* Intel Atom hardware */
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#define BWD_SBAR2XLAT_OFFSET 0x0008
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#define BWD_PDOORBELL_OFFSET 0x0020
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#define BWD_PDBMSK_OFFSET 0x0028
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#define BWD_NTBCNTL_OFFSET 0x0060
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#define BWD_SPAD_OFFSET 0x0080
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#define BWD_PPD_OFFSET 0x00d4
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#define BWD_PBAR2XLAT_OFFSET 0x8008
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#define BWD_B2B_DOORBELL_OFFSET 0x8020
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#define BWD_B2B_SPAD_OFFSET 0x8080
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#define BWD_SPCICMD_OFFSET 0xb004
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#define BWD_LINK_STATUS_OFFSET 0xb052
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#define BWD_ERRCORSTS_OFFSET 0xb110
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#define BWD_IP_BASE 0xc000
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#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
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#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
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#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
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#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
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#define BWD_MODPHY_PCSREG4 0x1c004
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#define BWD_MODPHY_PCSREG6 0x1c006
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#define ATOM_SBAR2XLAT_OFFSET 0x0008
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#define ATOM_PDOORBELL_OFFSET 0x0020
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#define ATOM_PDBMSK_OFFSET 0x0028
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#define ATOM_NTBCNTL_OFFSET 0x0060
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#define ATOM_SPAD_OFFSET 0x0080
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#define ATOM_PPD_OFFSET 0x00d4
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#define ATOM_PBAR2XLAT_OFFSET 0x8008
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#define ATOM_B2B_DOORBELL_OFFSET 0x8020
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#define ATOM_B2B_SPAD_OFFSET 0x8080
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#define ATOM_SPCICMD_OFFSET 0xb004
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#define ATOM_LINK_STATUS_OFFSET 0xb052
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#define ATOM_ERRCORSTS_OFFSET 0xb110
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#define ATOM_IP_BASE 0xc000
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#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
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#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
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#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
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#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
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#define ATOM_MODPHY_PCSREG4 0x1c004
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#define ATOM_MODPHY_PCSREG6 0x1c006
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#define BWD_PPD_INIT_LINK 0x0008
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#define BWD_PPD_CONN_MASK 0x0300
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#define BWD_PPD_CONN_TRANSPARENT 0x0000
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#define BWD_PPD_CONN_B2B 0x0100
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#define BWD_PPD_CONN_RP 0x0200
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#define BWD_PPD_DEV_MASK 0x1000
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#define BWD_PPD_DEV_USD 0x0000
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#define BWD_PPD_DEV_DSD 0x1000
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#define BWD_PPD_TOPO_MASK (BWD_PPD_CONN_MASK | BWD_PPD_DEV_MASK)
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#define BWD_PPD_TOPO_PRI_USD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_USD)
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#define BWD_PPD_TOPO_PRI_DSD (BWD_PPD_CONN_TRANSPARENT | BWD_PPD_DEV_DSD)
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#define BWD_PPD_TOPO_SEC_USD (BWD_PPD_CONN_RP | BWD_PPD_DEV_USD)
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#define BWD_PPD_TOPO_SEC_DSD (BWD_PPD_CONN_RP | BWD_PPD_DEV_DSD)
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#define BWD_PPD_TOPO_B2B_USD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_USD)
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#define BWD_PPD_TOPO_B2B_DSD (BWD_PPD_CONN_B2B | BWD_PPD_DEV_DSD)
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#define ATOM_PPD_INIT_LINK 0x0008
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#define ATOM_PPD_CONN_MASK 0x0300
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#define ATOM_PPD_CONN_TRANSPARENT 0x0000
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#define ATOM_PPD_CONN_B2B 0x0100
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#define ATOM_PPD_CONN_RP 0x0200
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#define ATOM_PPD_DEV_MASK 0x1000
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#define ATOM_PPD_DEV_USD 0x0000
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#define ATOM_PPD_DEV_DSD 0x1000
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#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK)
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#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD)
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#define BWD_MW_COUNT 2
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#define BWD_DB_COUNT 34
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#define BWD_DB_VALID_MASK (BIT_ULL(BWD_DB_COUNT) - 1)
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#define BWD_DB_MSIX_VECTOR_COUNT 34
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#define BWD_DB_MSIX_VECTOR_SHIFT 1
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#define BWD_DB_TOTAL_SHIFT 34
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#define BWD_SPAD_COUNT 16
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#define ATOM_MW_COUNT 2
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#define ATOM_DB_COUNT 34
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#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
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#define ATOM_DB_MSIX_VECTOR_COUNT 34
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#define ATOM_DB_MSIX_VECTOR_SHIFT 1
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#define ATOM_DB_TOTAL_SHIFT 34
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#define ATOM_SPAD_COUNT 16
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#define BWD_NTB_CTL_DOWN_BIT BIT(16)
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#define BWD_NTB_CTL_ACTIVE(x) !(x & BWD_NTB_CTL_DOWN_BIT)
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#define ATOM_NTB_CTL_DOWN_BIT BIT(16)
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#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT)
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#define BWD_DESKEWSTS_DBERR BIT(15)
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#define BWD_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
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#define BWD_LTSSMSTATEJMP_FORCEDETECT BIT(2)
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#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
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#define ATOM_DESKEWSTS_DBERR BIT(15)
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#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
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#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2)
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#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF
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#define BWD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
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#define BWD_LINK_RECOVERY_TIME msecs_to_jiffies(500)
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#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
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#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500)
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/* Ntb control and link status */
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@ -224,19 +224,19 @@
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/* Use the following addresses for translation between b2b ntb devices in case
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* the hardware default values are not reliable. */
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#define SNB_B2B_BAR0_USD_ADDR 0x1000000000000000ull
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#define SNB_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
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||||
#define SNB_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
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||||
#define SNB_B2B_BAR4_USD_ADDR32 0x20000000u
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||||
#define SNB_B2B_BAR5_USD_ADDR32 0x40000000u
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||||
#define SNB_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
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||||
#define SNB_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
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||||
#define SNB_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
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#define SNB_B2B_BAR4_DSD_ADDR32 0xa0000000u
|
||||
#define SNB_B2B_BAR5_DSD_ADDR32 0xc0000000u
|
||||
#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
|
||||
#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
|
||||
#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
|
||||
#define XEON_B2B_BAR4_USD_ADDR32 0x20000000u
|
||||
#define XEON_B2B_BAR5_USD_ADDR32 0x40000000u
|
||||
#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
|
||||
#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
|
||||
#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
|
||||
#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000u
|
||||
#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000u
|
||||
|
||||
/* The peer ntb secondary config space is 32KB fixed size */
|
||||
#define SNB_B2B_MIN_SIZE 0x8000
|
||||
#define XEON_B2B_MIN_SIZE 0x8000
|
||||
|
||||
/* flags to indicate hardware errata */
|
||||
#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue