Merge branch 'mmci' into fixes
This commit is contained in:
commit
2f8e728560
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@ -46,10 +46,6 @@ static unsigned int fmax = 515633;
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* is asserted (likewise for RX)
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* @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
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* is asserted (likewise for RX)
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* @broken_blockend: the MCI_DATABLOCKEND is broken on the hardware
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* and will not work at all.
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* @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware when
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* using DMA.
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* @sdio: variant supports SDIO
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* @st_clkdiv: true if using a ST-specific clock divider algorithm
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*/
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@ -59,8 +55,6 @@ struct variant_data {
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unsigned int datalength_bits;
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unsigned int fifosize;
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unsigned int fifohalfsize;
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bool broken_blockend;
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bool broken_blockend_dma;
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bool sdio;
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bool st_clkdiv;
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};
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@ -76,7 +70,6 @@ static struct variant_data variant_u300 = {
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.fifohalfsize = 8 * 4,
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.clkreg_enable = 1 << 13, /* HWFCEN */
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.datalength_bits = 16,
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.broken_blockend_dma = true,
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.sdio = true,
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};
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@ -86,7 +79,6 @@ static struct variant_data variant_ux500 = {
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.clkreg = MCI_CLK_ENABLE,
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.clkreg_enable = 1 << 14, /* HWFCEN */
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.datalength_bits = 24,
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.broken_blockend = true,
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.sdio = true,
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.st_clkdiv = true,
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};
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@ -210,8 +202,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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host->data = data;
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host->size = data->blksz * data->blocks;
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host->data_xfered = 0;
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host->blockend = false;
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host->dataend = false;
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mmci_init_sg(host, data);
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@ -288,21 +278,26 @@ static void
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mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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unsigned int status)
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{
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struct variant_data *variant = host->variant;
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/* First check for errors */
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
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if (status & MCI_DATACRCFAIL)
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data->error = -EILSEQ;
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else if (status & MCI_DATATIMEOUT)
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data->error = -ETIMEDOUT;
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else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
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data->error = -EIO;
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u32 remain, success;
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/* Force-complete the transaction */
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host->blockend = true;
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host->dataend = true;
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/* Calculate how far we are into the transfer */
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remain = readl(host->base + MMCIDATACNT) << 2;
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success = data->blksz * data->blocks - remain;
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dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
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if (status & MCI_DATACRCFAIL) {
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/* Last block was not successful */
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host->data_xfered = ((success / data->blksz) - 1 * data->blksz);
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data->error = -EILSEQ;
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} else if (status & MCI_DATATIMEOUT) {
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host->data_xfered = success;
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data->error = -ETIMEDOUT;
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} else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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host->data_xfered = success;
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data->error = -EIO;
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}
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/*
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* We hit an error condition. Ensure that any data
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@ -321,61 +316,14 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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}
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}
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/*
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* On ARM variants in PIO mode, MCI_DATABLOCKEND
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* is always sent first, and we increase the
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* transfered number of bytes for that IRQ. Then
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* MCI_DATAEND follows and we conclude the transaction.
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*
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* On the Ux500 single-IRQ variant MCI_DATABLOCKEND
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* doesn't seem to immediately clear from the status,
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* so we can't use it keep count when only one irq is
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* used because the irq will hit for other reasons, and
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* then the flag is still up. So we use the MCI_DATAEND
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* IRQ at the end of the entire transfer because
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* MCI_DATABLOCKEND is broken.
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*
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* In the U300, the IRQs can arrive out-of-order,
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* e.g. MCI_DATABLOCKEND sometimes arrives after MCI_DATAEND,
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* so for this case we use the flags "blockend" and
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* "dataend" to make sure both IRQs have arrived before
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* concluding the transaction. (This does not apply
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* to the Ux500 which doesn't fire MCI_DATABLOCKEND
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* at all.) In DMA mode it suffers from the same problem
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* as the Ux500.
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*/
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if (status & MCI_DATABLOCKEND) {
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/*
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* Just being a little over-cautious, we do not
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* use this progressive update if the hardware blockend
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* flag is unreliable: since it can stay high between
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* IRQs it will corrupt the transfer counter.
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*/
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if (!variant->broken_blockend)
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host->data_xfered += data->blksz;
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host->blockend = true;
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}
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if (status & MCI_DATABLOCKEND)
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dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
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if (status & MCI_DATAEND)
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host->dataend = true;
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/*
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* On variants with broken blockend we shall only wait for dataend,
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* on others we must sync with the blockend signal since they can
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* appear out-of-order.
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*/
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if (host->dataend && (host->blockend || variant->broken_blockend)) {
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if (status & MCI_DATAEND) {
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mmci_stop_data(host);
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/* Reset these flags */
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host->blockend = false;
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host->dataend = false;
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/*
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* Variants with broken blockend flags need to handle the
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* end of the entire transfer here.
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*/
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if (variant->broken_blockend && !data->error)
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if (!data->error)
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/* The error clause is handled above, success! */
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host->data_xfered += data->blksz * data->blocks;
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if (!data->stop) {
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@ -770,7 +718,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
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struct variant_data *variant = id->data;
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struct mmci_host *host;
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struct mmc_host *mmc;
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unsigned int mask;
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int ret;
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/* must have platform data */
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@ -951,12 +898,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
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goto irq0_free;
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}
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mask = MCI_IRQENABLE;
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/* Don't use the datablockend flag if it's broken */
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if (variant->broken_blockend)
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mask &= ~MCI_DATABLOCKEND;
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writel(mask, host->base + MMCIMASK0);
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writel(MCI_IRQENABLE, host->base + MMCIMASK0);
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amba_set_drvdata(dev, mmc);
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@ -137,7 +137,7 @@
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK)
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/* These interrupts are directed to IRQ1 when two IRQ lines are available */
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#define MCI_IRQ1MASK \
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@ -177,9 +177,6 @@ struct mmci_host {
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struct timer_list timer;
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unsigned int oldstat;
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bool blockend;
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bool dataend;
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/* pio stuff */
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struct sg_mapping_iter sg_miter;
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unsigned int size;
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