MLK-14610 DMA: fsl-edma-v3: add fsl-edma-v3 support
Add edma-v3 driver on i.mx8qm. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit d0ac0971c2e637ebddc853f12f71d130f5df4f91)5.4-rM2-2.2.x-imx-squashed
Robin Gong
Dong Aisheng
parent
219d54332a
commit
2f9e74892d
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@ -0,0 +1,64 @@
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* Freescale enhanced Direct Memory Access(eDMA-v3) Controller
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The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated
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on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by
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programmble memory-mapped registers. Specific DMA request source has fixed channel.
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* eDMA Controller
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Required properties:
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- compatible :
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- "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC
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- "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM
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- reg : Specifies base physical address(s) and size of the eDMA channel registers.
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Each eDMA channel has separated register's address and size.
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- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
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- interrupt-names : Should contain:
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"edma-chan12-tx" - the channel12 transmission interrupt
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- #dma-cells : Must be <3>.
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The 1st cell specifies the channel ID.
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The 2nd cell specifies the channel priority.
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The 3rd cell specifies the channel type like for transmit or receive:
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0: transmit, 1: receive.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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Examples:
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edma0: dma-controller@40018000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
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<0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
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<0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
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<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
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#dma-cells = <3>;
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dma-channels = <4>;
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interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-chan12-tx", "edma-chan13-tx",
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"edma-chan14-tx", "edma-chan15-tx";
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status = "okay";
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};
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* DMA clients
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DMA client drivers that uses the DMA function must use the format described
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in the dma.txt file, using a three-cell specifier for each channel: the 1st
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specifies the channel number, the 2nd specifies the priority, and the 3rd
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specifies the channel type is for transmit or receive: 0: transmit, 1: receive.
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Examples:
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lpuart1: serial@5a070000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a070000 0x0 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QM_UART1_CLK>;
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clock-names = "ipg";
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assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart1>;
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dma-names = "tx","rx";
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dmas = <&edma0 15 0 0>,
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<&edma0 14 0 1>;
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status = "disabled";
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};
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@ -227,6 +227,17 @@ config FSL_QDMA
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or dequeuing DMA jobs from, different work queues.
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or dequeuing DMA jobs from, different work queues.
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This module can be found on NXP Layerscape SoCs.
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This module can be found on NXP Layerscape SoCs.
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The qdma driver only work on SoCs with a DPAA hardware block.
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The qdma driver only work on SoCs with a DPAA hardware block.
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config FSL_EDMA_V3
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tristate "Freescale eDMA v3 engine support"
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depends on OF
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the Freescale eDMA v3 engine with programmable channel.
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This driver is based on FSL_EDMA but big changes come such as
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different interrupt for different channel, different register
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scope for different channel.
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This module can be found on Freescale i.MX8QM.
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config FSL_RAID
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config FSL_RAID
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tristate "Freescale RAID engine Support"
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tristate "Freescale RAID engine Support"
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@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
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obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
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obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o
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obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
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obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
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obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
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obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
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obj-$(CONFIG_FSL_RAID) += fsl_raid.o
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obj-$(CONFIG_FSL_RAID) += fsl_raid.o
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@ -0,0 +1,890 @@
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/*
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* drivers/dma/fsl-edma3-v3.c
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*
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* Copyright 2017 NXP .
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*
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* Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c
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* but changed to meet the IP change on i.MX8QM: every dma channel is specific
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* to hardware. For example, channel 14 for LPUART1 receive request and channel
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* 13 for transmit requesst. The eDMA block can be found on i.MX8QM
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_dma.h>
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#include "virt-dma.h"
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#define EDMA_CH_CSR 0x00
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#define EDMA_CH_ES 0x04
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#define EDMA_CH_INT 0x08
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#define EDMA_CH_SBR 0x0C
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#define EDMA_CH_PRI 0x10
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#define EDMA_TCD_SADDR 0x20
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#define EDMA_TCD_SOFF 0x24
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#define EDMA_TCD_ATTR 0x26
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#define EDMA_TCD_NBYTES 0x28
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#define EDMA_TCD_SLAST 0x2C
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#define EDMA_TCD_DADDR 0x30
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#define EDMA_TCD_DOFF 0x34
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#define EDMA_TCD_CITER_ELINK 0x36
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#define EDMA_TCD_CITER 0x36
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#define EDMA_TCD_DLAST_SGA 0x38
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#define EDMA_TCD_CSR 0x3C
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#define EDMA_TCD_BITER_ELINK 0x3E
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#define EDMA_TCD_BITER 0x3E
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#define EDMA_CH_SBR_RD BIT(22)
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#define EDMA_CH_SBR_WR BIT(21)
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#define EDMA_CH_CSR_ERQ BIT(0)
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#define EDMA_CH_CSR_EARQ BIT(1)
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#define EDMA_CH_CSR_EEI BIT(2)
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#define EDMA_CH_CSR_DONE BIT(30)
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#define EDMA_CH_CSR_ACTIVE BIT(31)
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#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007))
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#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3)
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#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8)
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#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11)
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#define EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
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#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
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#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
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#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300)
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#define EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
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#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500)
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#define EDMA_TCD_ATTR_SSIZE_64BYTE (0x0600)
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#define EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
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#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
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#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
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#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003)
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#define EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
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#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005)
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#define EDMA_TCD_ATTR_DSIZE_64BYTE (0x0006)
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#define EDMA_TCD_SOFF_SOFF(x) (x)
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#define EDMA_TCD_NBYTES_NBYTES(x) (x)
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#define EDMA_TCD_SLAST_SLAST(x) (x)
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#define EDMA_TCD_DADDR_DADDR(x) (x)
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#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF)
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#define EDMA_TCD_DOFF_DOFF(x) (x)
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#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
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#define EDMA_TCD_BITER_BITER(x) ((x) & 0x7FFF)
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#define EDMA_TCD_CSR_START BIT(0)
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#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
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#define EDMA_TCD_CSR_INT_HALF BIT(2)
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#define EDMA_TCD_CSR_D_REQ BIT(3)
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#define EDMA_TCD_CSR_E_SG BIT(4)
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#define EDMA_TCD_CSR_E_LINK BIT(5)
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#define EDMA_TCD_CSR_ACTIVE BIT(6)
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#define EDMA_TCD_CSR_DONE BIT(7)
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#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_16_BYTES))
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struct fsl_edma3_hw_tcd {
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__le32 saddr;
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__le16 soff;
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__le16 attr;
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__le32 nbytes;
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__le32 slast;
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__le32 daddr;
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__le16 doff;
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__le16 citer;
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__le32 dlast_sga;
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__le16 csr;
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__le16 biter;
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};
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struct fsl_edma3_sw_tcd {
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dma_addr_t ptcd;
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struct fsl_edma3_hw_tcd *vtcd;
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};
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struct fsl_edma3_slave_config {
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enum dma_transfer_direction dir;
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enum dma_slave_buswidth addr_width;
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u32 dev_addr;
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u32 dev2_addr; /* source addr for dev2dev */
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u32 burst;
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u32 attr;
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};
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struct fsl_edma3_chan {
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struct virt_dma_chan vchan;
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enum dma_status status;
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struct fsl_edma3_engine *edma3;
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struct fsl_edma3_desc *edesc;
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struct fsl_edma3_slave_config fsc;
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void __iomem *membase;
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int txirq;
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int hw_chanid;
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int priority;
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int is_rxchan;
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struct dma_pool *tcd_pool;
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u32 chn_real_count;
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char txirq_name[32];
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};
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struct fsl_edma3_desc {
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struct virt_dma_desc vdesc;
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struct fsl_edma3_chan *echan;
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bool iscyclic;
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unsigned int n_tcds;
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struct fsl_edma3_sw_tcd tcd[];
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};
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struct fsl_edma3_engine {
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struct dma_device dma_dev;
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struct mutex fsl_edma3_mutex;
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u32 n_chans;
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int errirq;
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bool swap; /* remote/local swapped on Audio edma */
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struct fsl_edma3_chan chans[];
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};
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static struct fsl_edma3_chan *to_fsl_edma3_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct fsl_edma3_chan, vchan.chan);
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}
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static struct fsl_edma3_desc *to_fsl_edma3_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct fsl_edma3_desc, vdesc);
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}
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static void fsl_edma3_enable_request(struct fsl_edma3_chan *fsl_chan)
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{
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void __iomem *addr = fsl_chan->membase;
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u32 val;
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val = readl(addr + EDMA_CH_SBR);
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/* Remote/local swapped wrongly on iMX8 QM Audio edma */
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if (fsl_chan->edma3->swap) {
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if (!fsl_chan->is_rxchan)
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val |= EDMA_CH_SBR_RD;
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else
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val |= EDMA_CH_SBR_WR;
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} else {
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if (fsl_chan->is_rxchan)
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val |= EDMA_CH_SBR_RD;
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else
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val |= EDMA_CH_SBR_WR;
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}
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writel(val, addr + EDMA_CH_SBR);
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val = readl(addr + EDMA_CH_CSR);
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val |= EDMA_CH_CSR_ERQ;
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writel(val, addr + EDMA_CH_CSR);
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}
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static void fsl_edma3_disable_request(struct fsl_edma3_chan *fsl_chan)
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{
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void __iomem *addr = fsl_chan->membase;
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u32 val = readl(addr + EDMA_CH_CSR);
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val &= ~EDMA_CH_CSR_ERQ;
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writel(val, addr + EDMA_CH_CSR);
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}
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static unsigned int fsl_edma3_get_tcd_attr(enum dma_slave_buswidth addr_width)
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{
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switch (addr_width) {
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case 1:
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return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
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case 2:
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return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
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case 4:
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return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
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case 8:
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return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
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case 16:
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return EDMA_TCD_ATTR_SSIZE_16BYTE | EDMA_TCD_ATTR_DSIZE_16BYTE;
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case 32:
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return EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE;
|
||||||
|
case 64:
|
||||||
|
return EDMA_TCD_ATTR_SSIZE_64BYTE | EDMA_TCD_ATTR_DSIZE_64BYTE;
|
||||||
|
default:
|
||||||
|
return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_edma3_free_desc(struct virt_dma_desc *vdesc)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_desc *fsl_desc;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
fsl_desc = to_fsl_edma3_desc(vdesc);
|
||||||
|
for (i = 0; i < fsl_desc->n_tcds; i++)
|
||||||
|
dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
|
||||||
|
fsl_desc->tcd[i].ptcd);
|
||||||
|
kfree(fsl_desc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_terminate_all(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
unsigned long flags;
|
||||||
|
LIST_HEAD(head);
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
fsl_edma3_disable_request(fsl_chan);
|
||||||
|
fsl_chan->edesc = NULL;
|
||||||
|
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_pause(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
if (fsl_chan->edesc) {
|
||||||
|
fsl_edma3_disable_request(fsl_chan);
|
||||||
|
fsl_chan->status = DMA_PAUSED;
|
||||||
|
}
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_resume(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
if (fsl_chan->edesc) {
|
||||||
|
fsl_edma3_enable_request(fsl_chan);
|
||||||
|
fsl_chan->status = DMA_IN_PROGRESS;
|
||||||
|
}
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_slave_config(struct dma_chan *chan,
|
||||||
|
struct dma_slave_config *cfg)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
|
||||||
|
fsl_chan->fsc.dir = cfg->direction;
|
||||||
|
if (cfg->direction == DMA_DEV_TO_MEM) {
|
||||||
|
fsl_chan->fsc.dev_addr = cfg->src_addr;
|
||||||
|
fsl_chan->fsc.addr_width = cfg->src_addr_width;
|
||||||
|
fsl_chan->fsc.burst = cfg->src_maxburst;
|
||||||
|
fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr
|
||||||
|
(cfg->src_addr_width);
|
||||||
|
} else if (cfg->direction == DMA_MEM_TO_DEV) {
|
||||||
|
fsl_chan->fsc.dev_addr = cfg->dst_addr;
|
||||||
|
fsl_chan->fsc.addr_width = cfg->dst_addr_width;
|
||||||
|
fsl_chan->fsc.burst = cfg->dst_maxburst;
|
||||||
|
fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr
|
||||||
|
(cfg->dst_addr_width);
|
||||||
|
} else if (cfg->direction == DMA_DEV_TO_DEV) {
|
||||||
|
fsl_chan->fsc.dev2_addr = cfg->src_addr;
|
||||||
|
fsl_chan->fsc.dev_addr = cfg->dst_addr;
|
||||||
|
fsl_chan->fsc.addr_width = cfg->dst_addr_width;
|
||||||
|
fsl_chan->fsc.burst = cfg->dst_maxburst;
|
||||||
|
fsl_chan->fsc.attr = fsl_edma3_get_tcd_attr
|
||||||
|
(cfg->dst_addr_width);
|
||||||
|
} else {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan,
|
||||||
|
struct virt_dma_desc *vdesc, bool in_progress)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_desc *edesc = fsl_chan->edesc;
|
||||||
|
void __iomem *addr = fsl_chan->membase;
|
||||||
|
enum dma_transfer_direction dir = fsl_chan->fsc.dir;
|
||||||
|
dma_addr_t cur_addr, dma_addr;
|
||||||
|
size_t len, size;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* calculate the total size in this desc */
|
||||||
|
for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
|
||||||
|
len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
|
||||||
|
* le16_to_cpu(edesc->tcd[i].vtcd->biter);
|
||||||
|
|
||||||
|
if (!in_progress)
|
||||||
|
return len;
|
||||||
|
|
||||||
|
if (dir == DMA_MEM_TO_DEV)
|
||||||
|
cur_addr = readl(addr + EDMA_TCD_SADDR);
|
||||||
|
else
|
||||||
|
cur_addr = readl(addr + EDMA_TCD_DADDR);
|
||||||
|
|
||||||
|
/* figure out the finished and calculate the residue */
|
||||||
|
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
|
||||||
|
size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
|
||||||
|
* le16_to_cpu(edesc->tcd[i].vtcd->biter);
|
||||||
|
if (dir == DMA_MEM_TO_DEV)
|
||||||
|
dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
|
||||||
|
else
|
||||||
|
dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
|
||||||
|
|
||||||
|
len -= size;
|
||||||
|
if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
|
||||||
|
len += dma_addr + size - cur_addr;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
static enum dma_status fsl_edma3_tx_status(struct dma_chan *chan,
|
||||||
|
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
struct virt_dma_desc *vdesc;
|
||||||
|
enum dma_status status;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
status = dma_cookie_status(chan, cookie, txstate);
|
||||||
|
if (status == DMA_COMPLETE) {
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
txstate->residue = fsl_chan->chn_real_count;
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!txstate)
|
||||||
|
return fsl_chan->status;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
|
||||||
|
if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
|
||||||
|
txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc,
|
||||||
|
true);
|
||||||
|
else if (vdesc)
|
||||||
|
txstate->residue = fsl_edma3_desc_residue(fsl_chan, vdesc,
|
||||||
|
false);
|
||||||
|
else
|
||||||
|
txstate->residue = 0;
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
|
||||||
|
return fsl_chan->status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_edma3_set_tcd_regs(struct fsl_edma3_chan *fsl_chan,
|
||||||
|
struct fsl_edma3_hw_tcd *tcd)
|
||||||
|
{
|
||||||
|
void __iomem *addr = fsl_chan->membase;
|
||||||
|
/*
|
||||||
|
* TCD parameters are stored in struct fsl_edma3_hw_tcd in little
|
||||||
|
* endian format. However, we need to load the TCD registers in
|
||||||
|
* big- or little-endian obeying the eDMA engine model endian.
|
||||||
|
*/
|
||||||
|
writew(0, addr + EDMA_TCD_CSR);
|
||||||
|
writel(le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR);
|
||||||
|
writel(le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR);
|
||||||
|
|
||||||
|
writew(le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR);
|
||||||
|
writew(le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF);
|
||||||
|
|
||||||
|
writel(le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES);
|
||||||
|
writel(le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST);
|
||||||
|
|
||||||
|
writew(le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER);
|
||||||
|
writew(le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER);
|
||||||
|
writew(le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF);
|
||||||
|
|
||||||
|
writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
|
||||||
|
|
||||||
|
writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline
|
||||||
|
void fsl_edma3_fill_tcd(struct fsl_edma3_chan *fsl_chan,
|
||||||
|
struct fsl_edma3_hw_tcd *tcd, u32 src, u32 dst,
|
||||||
|
u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
|
||||||
|
u16 biter, u16 doff, u32 dlast_sga, bool major_int,
|
||||||
|
bool disable_req, bool enable_sg)
|
||||||
|
{
|
||||||
|
u16 csr = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* eDMA hardware SGs require the TCDs to be stored in little
|
||||||
|
* endian format irrespective of the register endian model.
|
||||||
|
* So we put the value in little endian in memory, waiting
|
||||||
|
* for fsl_edma3_set_tcd_regs doing the swap.
|
||||||
|
*/
|
||||||
|
tcd->saddr = cpu_to_le32(src);
|
||||||
|
tcd->daddr = cpu_to_le32(dst);
|
||||||
|
|
||||||
|
tcd->attr = cpu_to_le16(attr);
|
||||||
|
|
||||||
|
tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff));
|
||||||
|
|
||||||
|
tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes));
|
||||||
|
tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast));
|
||||||
|
|
||||||
|
tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
|
||||||
|
tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff));
|
||||||
|
|
||||||
|
tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga));
|
||||||
|
|
||||||
|
tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
|
||||||
|
if (major_int)
|
||||||
|
csr |= EDMA_TCD_CSR_INT_MAJOR;
|
||||||
|
|
||||||
|
if (disable_req)
|
||||||
|
csr |= EDMA_TCD_CSR_D_REQ;
|
||||||
|
|
||||||
|
if (enable_sg)
|
||||||
|
csr |= EDMA_TCD_CSR_E_SG;
|
||||||
|
|
||||||
|
if (fsl_chan->is_rxchan)
|
||||||
|
csr |= EDMA_TCD_CSR_ACTIVE;
|
||||||
|
|
||||||
|
tcd->csr = cpu_to_le16(csr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct fsl_edma3_desc *fsl_edma3_alloc_desc(struct fsl_edma3_chan
|
||||||
|
*fsl_chan, int sg_len)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_desc *fsl_desc;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma3_sw_tcd)
|
||||||
|
* sg_len, GFP_ATOMIC);
|
||||||
|
if (!fsl_desc)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
fsl_desc->echan = fsl_chan;
|
||||||
|
fsl_desc->n_tcds = sg_len;
|
||||||
|
for (i = 0; i < sg_len; i++) {
|
||||||
|
fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
|
||||||
|
GFP_ATOMIC, &fsl_desc->tcd[i].ptcd);
|
||||||
|
if (!fsl_desc->tcd[i].vtcd)
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
return fsl_desc;
|
||||||
|
|
||||||
|
err:
|
||||||
|
while (--i >= 0)
|
||||||
|
dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
|
||||||
|
fsl_desc->tcd[i].ptcd);
|
||||||
|
kfree(fsl_desc);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct dma_async_tx_descriptor *fsl_edma3_prep_dma_cyclic(
|
||||||
|
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
||||||
|
size_t period_len, enum dma_transfer_direction direction,
|
||||||
|
unsigned long flags)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
struct fsl_edma3_desc *fsl_desc;
|
||||||
|
dma_addr_t dma_buf_next;
|
||||||
|
int sg_len, i;
|
||||||
|
u32 src_addr, dst_addr, last_sg, nbytes;
|
||||||
|
u16 soff, doff, iter;
|
||||||
|
|
||||||
|
sg_len = buf_len / period_len;
|
||||||
|
fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len);
|
||||||
|
if (!fsl_desc)
|
||||||
|
return NULL;
|
||||||
|
fsl_desc->iscyclic = true;
|
||||||
|
|
||||||
|
dma_buf_next = dma_addr;
|
||||||
|
nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
|
||||||
|
iter = period_len / nbytes;
|
||||||
|
|
||||||
|
for (i = 0; i < sg_len; i++) {
|
||||||
|
if (dma_buf_next >= dma_addr + buf_len)
|
||||||
|
dma_buf_next = dma_addr;
|
||||||
|
|
||||||
|
/* get next sg's physical address */
|
||||||
|
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
||||||
|
|
||||||
|
if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
|
||||||
|
src_addr = dma_buf_next;
|
||||||
|
dst_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
soff = fsl_chan->fsc.addr_width;
|
||||||
|
doff = 0;
|
||||||
|
} else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) {
|
||||||
|
src_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
dst_addr = dma_buf_next;
|
||||||
|
soff = 0;
|
||||||
|
doff = fsl_chan->fsc.addr_width;
|
||||||
|
} else {
|
||||||
|
/* DMA_DEV_TO_DEV */
|
||||||
|
src_addr = fsl_chan->fsc.dev2_addr;
|
||||||
|
dst_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
soff = 0;
|
||||||
|
doff = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
|
||||||
|
dst_addr, fsl_chan->fsc.attr, soff, nbytes, 0,
|
||||||
|
iter, iter, doff, last_sg, true, false, true);
|
||||||
|
dma_buf_next += period_len;
|
||||||
|
}
|
||||||
|
|
||||||
|
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct dma_async_tx_descriptor *fsl_edma3_prep_slave_sg(
|
||||||
|
struct dma_chan *chan, struct scatterlist *sgl,
|
||||||
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
||||||
|
unsigned long flags, void *context)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
struct fsl_edma3_desc *fsl_desc;
|
||||||
|
struct scatterlist *sg;
|
||||||
|
u32 src_addr, dst_addr, last_sg, nbytes;
|
||||||
|
u16 soff, doff, iter;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!is_slave_direction(fsl_chan->fsc.dir))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
fsl_desc = fsl_edma3_alloc_desc(fsl_chan, sg_len);
|
||||||
|
if (!fsl_desc)
|
||||||
|
return NULL;
|
||||||
|
fsl_desc->iscyclic = false;
|
||||||
|
|
||||||
|
nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
|
||||||
|
for_each_sg(sgl, sg, sg_len, i) {
|
||||||
|
/* get next sg's physical address */
|
||||||
|
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
|
||||||
|
|
||||||
|
if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
|
||||||
|
src_addr = sg_dma_address(sg);
|
||||||
|
dst_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
soff = fsl_chan->fsc.addr_width;
|
||||||
|
doff = 0;
|
||||||
|
} else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) {
|
||||||
|
src_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
dst_addr = sg_dma_address(sg);
|
||||||
|
soff = 0;
|
||||||
|
doff = fsl_chan->fsc.addr_width;
|
||||||
|
} else {
|
||||||
|
/* DMA_DEV_TO_DEV */
|
||||||
|
src_addr = fsl_chan->fsc.dev2_addr;
|
||||||
|
dst_addr = fsl_chan->fsc.dev_addr;
|
||||||
|
soff = 0;
|
||||||
|
doff = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
iter = sg_dma_len(sg) / nbytes;
|
||||||
|
if (i < sg_len - 1) {
|
||||||
|
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
|
||||||
|
fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd,
|
||||||
|
src_addr, dst_addr, fsl_chan->fsc.attr,
|
||||||
|
soff, nbytes, 0, iter, iter, doff,
|
||||||
|
last_sg, false, false, true);
|
||||||
|
} else {
|
||||||
|
last_sg = 0;
|
||||||
|
fsl_edma3_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd,
|
||||||
|
src_addr, dst_addr, fsl_chan->fsc.attr,
|
||||||
|
soff, nbytes, 0, iter, iter, doff,
|
||||||
|
last_sg, true, true, false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_edma3_xfer_desc(struct fsl_edma3_chan *fsl_chan)
|
||||||
|
{
|
||||||
|
struct virt_dma_desc *vdesc;
|
||||||
|
|
||||||
|
vdesc = vchan_next_desc(&fsl_chan->vchan);
|
||||||
|
if (!vdesc)
|
||||||
|
return;
|
||||||
|
fsl_chan->edesc = to_fsl_edma3_desc(vdesc);
|
||||||
|
fsl_edma3_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
|
||||||
|
fsl_edma3_enable_request(fsl_chan);
|
||||||
|
fsl_chan->status = DMA_IN_PROGRESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
static size_t fsl_edma3_desc_residue(struct fsl_edma3_chan *fsl_chan,
|
||||||
|
struct virt_dma_desc *vdesc, bool in_progress);
|
||||||
|
|
||||||
|
static void fsl_edma3_get_realcnt(struct fsl_edma3_chan *fsl_chan)
|
||||||
|
{
|
||||||
|
fsl_chan->chn_real_count = fsl_edma3_desc_residue(fsl_chan, NULL, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = dev_id;
|
||||||
|
unsigned int intr;
|
||||||
|
void __iomem *base_addr;
|
||||||
|
|
||||||
|
base_addr = fsl_chan->membase;
|
||||||
|
|
||||||
|
intr = readl(base_addr + EDMA_CH_INT);
|
||||||
|
if (!intr)
|
||||||
|
return IRQ_NONE;
|
||||||
|
|
||||||
|
writel(1, base_addr + EDMA_CH_INT);
|
||||||
|
|
||||||
|
spin_lock(&fsl_chan->vchan.lock);
|
||||||
|
if (!fsl_chan->edesc->iscyclic) {
|
||||||
|
fsl_edma3_get_realcnt(fsl_chan);
|
||||||
|
list_del(&fsl_chan->edesc->vdesc.node);
|
||||||
|
vchan_cookie_complete(&fsl_chan->edesc->vdesc);
|
||||||
|
fsl_chan->edesc = NULL;
|
||||||
|
fsl_chan->status = DMA_COMPLETE;
|
||||||
|
} else {
|
||||||
|
vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!fsl_chan->edesc)
|
||||||
|
fsl_edma3_xfer_desc(fsl_chan);
|
||||||
|
|
||||||
|
spin_unlock(&fsl_chan->vchan.lock);
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_edma3_issue_pending(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
|
||||||
|
if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
|
||||||
|
fsl_edma3_xfer_desc(fsl_chan);
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
|
||||||
|
struct of_dma *ofdma)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_engine *fsl_edma3 = ofdma->of_dma_data;
|
||||||
|
struct dma_chan *chan, *_chan;
|
||||||
|
struct fsl_edma3_chan *fsl_chan;
|
||||||
|
|
||||||
|
if (dma_spec->args_count != 3)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
mutex_lock(&fsl_edma3->fsl_edma3_mutex);
|
||||||
|
list_for_each_entry_safe(chan, _chan, &fsl_edma3->dma_dev.channels,
|
||||||
|
device_node) {
|
||||||
|
if (chan->client_count)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
if (fsl_chan->hw_chanid == dma_spec->args[0]) {
|
||||||
|
chan = dma_get_slave_channel(chan);
|
||||||
|
chan->device->privatecnt++;
|
||||||
|
fsl_chan->priority = dma_spec->args[1];
|
||||||
|
fsl_chan->is_rxchan = dma_spec->args[2];
|
||||||
|
mutex_unlock(&fsl_edma3->fsl_edma3_mutex);
|
||||||
|
return chan;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
mutex_unlock(&fsl_edma3->fsl_edma3_mutex);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_alloc_chan_resources(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
|
||||||
|
fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
|
||||||
|
sizeof(struct fsl_edma3_hw_tcd),
|
||||||
|
32, 0);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_edma3_free_chan_resources(struct dma_chan *chan)
|
||||||
|
{
|
||||||
|
struct fsl_edma3_chan *fsl_chan = to_fsl_edma3_chan(chan);
|
||||||
|
unsigned long flags;
|
||||||
|
LIST_HEAD(head);
|
||||||
|
|
||||||
|
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||||
|
fsl_edma3_disable_request(fsl_chan);
|
||||||
|
fsl_chan->edesc = NULL;
|
||||||
|
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
||||||
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||||
|
|
||||||
|
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||||
|
dma_pool_destroy(fsl_chan->tcd_pool);
|
||||||
|
fsl_chan->tcd_pool = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct device_node *np = pdev->dev.of_node;
|
||||||
|
struct fsl_edma3_engine *fsl_edma3;
|
||||||
|
struct fsl_edma3_chan *fsl_chan;
|
||||||
|
struct resource *res;
|
||||||
|
int len, chans;
|
||||||
|
int ret, i;
|
||||||
|
unsigned long irqflag = 0;
|
||||||
|
|
||||||
|
ret = of_property_read_u32(np, "dma-channels", &chans);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Can't get dma-channels.\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans;
|
||||||
|
fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
|
||||||
|
if (!fsl_edma3)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
/* Audio edma rx/tx channel shared interrupt */
|
||||||
|
if (of_property_read_bool(np, "shared-interrupt"))
|
||||||
|
irqflag = IRQF_SHARED;
|
||||||
|
|
||||||
|
fsl_edma3->swap = of_device_is_compatible(np, "fsl,imx8qm-adma");
|
||||||
|
fsl_edma3->n_chans = chans;
|
||||||
|
|
||||||
|
INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels);
|
||||||
|
for (i = 0; i < fsl_edma3->n_chans; i++) {
|
||||||
|
struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i];
|
||||||
|
char *txirq_name = fsl_chan->txirq_name;
|
||||||
|
|
||||||
|
fsl_chan->edma3 = fsl_edma3;
|
||||||
|
/* Get per channel membase */
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||||
|
fsl_chan->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
if (IS_ERR(fsl_chan->membase))
|
||||||
|
return PTR_ERR(fsl_chan->membase);
|
||||||
|
|
||||||
|
/* Get the hardware chanel id by the channel membase
|
||||||
|
* channel0:0x10000, channel1:0x20000... total 32 channels
|
||||||
|
*/
|
||||||
|
fsl_chan->hw_chanid = (res->start >> 16) & 0x1f;
|
||||||
|
sprintf(txirq_name, "edma-chan%d-tx", fsl_chan->hw_chanid);
|
||||||
|
|
||||||
|
/* request channel irq */
|
||||||
|
fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name);
|
||||||
|
if (fsl_chan->txirq < 0) {
|
||||||
|
dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name);
|
||||||
|
return fsl_chan->txirq;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
|
||||||
|
fsl_edma3_tx_handler, irqflag, txirq_name,
|
||||||
|
fsl_chan);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Can't register %s IRQ.\n",
|
||||||
|
txirq_name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
fsl_chan->vchan.desc_free = fsl_edma3_free_desc;
|
||||||
|
vchan_init(&fsl_chan->vchan, &fsl_edma3->dma_dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_init(&fsl_edma3->fsl_edma3_mutex);
|
||||||
|
|
||||||
|
dma_cap_set(DMA_PRIVATE, fsl_edma3->dma_dev.cap_mask);
|
||||||
|
dma_cap_set(DMA_SLAVE, fsl_edma3->dma_dev.cap_mask);
|
||||||
|
dma_cap_set(DMA_CYCLIC, fsl_edma3->dma_dev.cap_mask);
|
||||||
|
|
||||||
|
fsl_edma3->dma_dev.dev = &pdev->dev;
|
||||||
|
fsl_edma3->dma_dev.device_alloc_chan_resources
|
||||||
|
= fsl_edma3_alloc_chan_resources;
|
||||||
|
fsl_edma3->dma_dev.device_free_chan_resources
|
||||||
|
= fsl_edma3_free_chan_resources;
|
||||||
|
fsl_edma3->dma_dev.device_tx_status = fsl_edma3_tx_status;
|
||||||
|
fsl_edma3->dma_dev.device_prep_slave_sg = fsl_edma3_prep_slave_sg;
|
||||||
|
fsl_edma3->dma_dev.device_prep_dma_cyclic = fsl_edma3_prep_dma_cyclic;
|
||||||
|
fsl_edma3->dma_dev.device_config = fsl_edma3_slave_config;
|
||||||
|
fsl_edma3->dma_dev.device_pause = fsl_edma3_pause;
|
||||||
|
fsl_edma3->dma_dev.device_resume = fsl_edma3_resume;
|
||||||
|
fsl_edma3->dma_dev.device_terminate_all = fsl_edma3_terminate_all;
|
||||||
|
fsl_edma3->dma_dev.device_issue_pending = fsl_edma3_issue_pending;
|
||||||
|
|
||||||
|
fsl_edma3->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
|
||||||
|
fsl_edma3->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
|
||||||
|
fsl_edma3->dma_dev.directions = BIT(DMA_DEV_TO_MEM) |
|
||||||
|
BIT(DMA_MEM_TO_DEV) |
|
||||||
|
BIT(DMA_DEV_TO_DEV);
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, fsl_edma3);
|
||||||
|
|
||||||
|
ret = dma_async_device_register(&fsl_edma3->dma_dev);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma3);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n");
|
||||||
|
dma_async_device_unregister(&fsl_edma3->dma_dev);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_edma3_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct device_node *np = pdev->dev.of_node;
|
||||||
|
struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
of_dma_controller_free(np);
|
||||||
|
dma_async_device_unregister(&fsl_edma3->dma_dev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id fsl_edma3_dt_ids[] = {
|
||||||
|
{ .compatible = "fsl,imx8qm-edma", },
|
||||||
|
{ .compatible = "fsl,imx8qm-adma", },
|
||||||
|
{ /* sentinel */ }
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids);
|
||||||
|
|
||||||
|
static struct platform_driver fsl_edma3_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "fsl-edma-v3",
|
||||||
|
.of_match_table = fsl_edma3_dt_ids,
|
||||||
|
},
|
||||||
|
.probe = fsl_edma3_probe,
|
||||||
|
.remove = fsl_edma3_remove,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init fsl_edma3_init(void)
|
||||||
|
{
|
||||||
|
return platform_driver_register(&fsl_edma3_driver);
|
||||||
|
}
|
||||||
|
subsys_initcall(fsl_edma3_init);
|
||||||
|
|
||||||
|
static void __exit fsl_edma3_exit(void)
|
||||||
|
{
|
||||||
|
platform_driver_unregister(&fsl_edma3_driver);
|
||||||
|
}
|
||||||
|
module_exit(fsl_edma3_exit);
|
||||||
|
|
||||||
|
MODULE_ALIAS("platform:fsl-edma3");
|
||||||
|
MODULE_DESCRIPTION("Freescale eDMA-V3 engine driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
Loading…
Reference in New Issue