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@ -1,5 +1,5 @@
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -103,7 +103,8 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
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* Returns:
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* 0 on success or a negative error code on failure.
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*/
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int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
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int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
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struct vm_area_struct *vma)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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@ -137,6 +138,235 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma
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return ret;
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}
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static int
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__reservation_object_make_exclusive(struct reservation_object *obj)
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{
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struct dma_fence **fences;
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unsigned int count;
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int r;
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if (!reservation_object_get_list(obj)) /* no shared fences to convert */
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return 0;
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r = reservation_object_get_fences_rcu(obj, NULL, &count, &fences);
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if (r)
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return r;
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if (count == 0) {
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/* Now that was unexpected. */
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} else if (count == 1) {
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reservation_object_add_excl_fence(obj, fences[0]);
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dma_fence_put(fences[0]);
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kfree(fences);
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} else {
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struct dma_fence_array *array;
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array = dma_fence_array_create(count, fences,
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dma_fence_context_alloc(1), 0,
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false);
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if (!array)
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goto err_fences_put;
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reservation_object_add_excl_fence(obj, &array->base);
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dma_fence_put(&array->base);
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}
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return 0;
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err_fences_put:
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while (count--)
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dma_fence_put(fences[count]);
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kfree(fences);
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return -ENOMEM;
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}
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/**
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* amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation
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* @dma_buf: Shared DMA buffer
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* @attach: DMA-buf attachment
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*
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* Makes sure that the shared DMA buffer can be accessed by the target device.
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* For now, simply pins it to the GTT domain, where it should be accessible by
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* all DMA devices.
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*
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* Returns:
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* 0 on success or a negative error code on failure.
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*/
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static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf,
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struct dma_buf_attachment *attach)
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{
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struct drm_gem_object *obj = dma_buf->priv;
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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long r;
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r = drm_gem_map_attach(dma_buf, attach);
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if (r)
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return r;
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r = amdgpu_bo_reserve(bo, false);
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if (unlikely(r != 0))
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goto error_detach;
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if (attach->dev->driver != adev->dev->driver) {
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/*
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* We only create shared fences for internal use, but importers
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* of the dmabuf rely on exclusive fences for implicitly
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* tracking write hazards. As any of the current fences may
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* correspond to a write, we need to convert all existing
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* fences on the reservation object into a single exclusive
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* fence.
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*/
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r = __reservation_object_make_exclusive(bo->tbo.resv);
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if (r)
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goto error_unreserve;
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}
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/* pin buffer into GTT */
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r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
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if (r)
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goto error_unreserve;
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if (attach->dev->driver != adev->dev->driver)
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bo->prime_shared_count++;
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error_unreserve:
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amdgpu_bo_unreserve(bo);
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error_detach:
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if (r)
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drm_gem_map_detach(dma_buf, attach);
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return r;
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}
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/**
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* amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation
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* @dma_buf: Shared DMA buffer
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* @attach: DMA-buf attachment
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*
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* This is called when a shared DMA buffer no longer needs to be accessible by
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* another device. For now, simply unpins the buffer from GTT.
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*/
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static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf,
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struct dma_buf_attachment *attach)
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{
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struct drm_gem_object *obj = dma_buf->priv;
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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int ret = 0;
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ret = amdgpu_bo_reserve(bo, true);
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if (unlikely(ret != 0))
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goto error;
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amdgpu_bo_unpin(bo);
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if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
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bo->prime_shared_count--;
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amdgpu_bo_unreserve(bo);
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error:
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drm_gem_map_detach(dma_buf, attach);
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}
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/**
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* amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation
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* @obj: GEM BO
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*
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* Returns:
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* The BO's reservation object.
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*/
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struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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return bo->tbo.resv;
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}
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/**
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* amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
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* @dma_buf: Shared DMA buffer
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* @direction: Direction of DMA transfer
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*
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* This is called before CPU access to the shared DMA buffer's memory. If it's
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* a read access, the buffer is moved to the GTT domain if possible, for optimal
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* CPU read performance.
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*
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* Returns:
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* 0 on success or a negative error code on failure.
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*/
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static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
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enum dma_data_direction direction)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct ttm_operation_ctx ctx = { true, false };
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u32 domain = amdgpu_display_supported_domains(adev);
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int ret;
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bool reads = (direction == DMA_BIDIRECTIONAL ||
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direction == DMA_FROM_DEVICE);
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if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
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return 0;
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/* move to gtt */
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ret = amdgpu_bo_reserve(bo, false);
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if (unlikely(ret != 0))
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return ret;
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if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
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amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
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ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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}
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amdgpu_bo_unreserve(bo);
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return ret;
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}
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const struct dma_buf_ops amdgpu_dmabuf_ops = {
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.attach = amdgpu_dma_buf_map_attach,
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.detach = amdgpu_dma_buf_map_detach,
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.map_dma_buf = drm_gem_map_dma_buf,
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.unmap_dma_buf = drm_gem_unmap_dma_buf,
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.release = drm_gem_dmabuf_release,
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.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
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.mmap = drm_gem_dmabuf_mmap,
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.vmap = drm_gem_dmabuf_vmap,
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.vunmap = drm_gem_dmabuf_vunmap,
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};
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/**
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* amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
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* @dev: DRM device
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* @gobj: GEM BO
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* @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
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*
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* The main work is done by the &drm_gem_prime_export helper, which in turn
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* uses &amdgpu_gem_prime_res_obj.
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*
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* Returns:
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* Shared DMA buffer representing the GEM BO from the given device.
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*/
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struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
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struct drm_gem_object *gobj,
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int flags)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
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struct dma_buf *buf;
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
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bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
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return ERR_PTR(-EPERM);
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buf = drm_gem_prime_export(dev, gobj, flags);
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if (!IS_ERR(buf)) {
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buf->file->f_mapping = dev->anon_inode->i_mapping;
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buf->ops = &amdgpu_dmabuf_ops;
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}
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return buf;
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}
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/**
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* amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
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* implementation
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@ -188,235 +418,6 @@ error:
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return ERR_PTR(ret);
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}
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static int
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__reservation_object_make_exclusive(struct reservation_object *obj)
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{
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struct dma_fence **fences;
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unsigned int count;
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int r;
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if (!reservation_object_get_list(obj)) /* no shared fences to convert */
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return 0;
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r = reservation_object_get_fences_rcu(obj, NULL, &count, &fences);
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if (r)
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return r;
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if (count == 0) {
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/* Now that was unexpected. */
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} else if (count == 1) {
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reservation_object_add_excl_fence(obj, fences[0]);
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dma_fence_put(fences[0]);
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kfree(fences);
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} else {
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struct dma_fence_array *array;
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array = dma_fence_array_create(count, fences,
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dma_fence_context_alloc(1), 0,
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false);
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if (!array)
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goto err_fences_put;
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reservation_object_add_excl_fence(obj, &array->base);
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dma_fence_put(&array->base);
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}
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return 0;
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err_fences_put:
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while (count--)
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dma_fence_put(fences[count]);
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kfree(fences);
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return -ENOMEM;
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}
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/**
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* amdgpu_gem_map_attach - &dma_buf_ops.attach implementation
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* @dma_buf: Shared DMA buffer
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* @attach: DMA-buf attachment
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*
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* Makes sure that the shared DMA buffer can be accessed by the target device.
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* For now, simply pins it to the GTT domain, where it should be accessible by
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* all DMA devices.
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*
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* Returns:
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* 0 on success or a negative error code on failure.
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*/
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static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
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struct dma_buf_attachment *attach)
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{
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struct drm_gem_object *obj = dma_buf->priv;
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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long r;
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r = drm_gem_map_attach(dma_buf, attach);
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|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
|
|
|
|
|
r = amdgpu_bo_reserve(bo, false);
|
|
|
|
|
if (unlikely(r != 0))
|
|
|
|
|
goto error_detach;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (attach->dev->driver != adev->dev->driver) {
|
|
|
|
|
/*
|
|
|
|
|
* We only create shared fences for internal use, but importers
|
|
|
|
|
* of the dmabuf rely on exclusive fences for implicitly
|
|
|
|
|
* tracking write hazards. As any of the current fences may
|
|
|
|
|
* correspond to a write, we need to convert all existing
|
|
|
|
|
* fences on the reservation object into a single exclusive
|
|
|
|
|
* fence.
|
|
|
|
|
*/
|
|
|
|
|
r = __reservation_object_make_exclusive(bo->tbo.resv);
|
|
|
|
|
if (r)
|
|
|
|
|
goto error_unreserve;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* pin buffer into GTT */
|
|
|
|
|
r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
|
|
|
|
|
if (r)
|
|
|
|
|
goto error_unreserve;
|
|
|
|
|
|
|
|
|
|
if (attach->dev->driver != adev->dev->driver)
|
|
|
|
|
bo->prime_shared_count++;
|
|
|
|
|
|
|
|
|
|
error_unreserve:
|
|
|
|
|
amdgpu_bo_unreserve(bo);
|
|
|
|
|
|
|
|
|
|
error_detach:
|
|
|
|
|
if (r)
|
|
|
|
|
drm_gem_map_detach(dma_buf, attach);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* amdgpu_gem_map_detach - &dma_buf_ops.detach implementation
|
|
|
|
|
* @dma_buf: Shared DMA buffer
|
|
|
|
|
* @attach: DMA-buf attachment
|
|
|
|
|
*
|
|
|
|
|
* This is called when a shared DMA buffer no longer needs to be accessible by
|
|
|
|
|
* another device. For now, simply unpins the buffer from GTT.
|
|
|
|
|
*/
|
|
|
|
|
static void amdgpu_gem_map_detach(struct dma_buf *dma_buf,
|
|
|
|
|
struct dma_buf_attachment *attach)
|
|
|
|
|
{
|
|
|
|
|
struct drm_gem_object *obj = dma_buf->priv;
|
|
|
|
|
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
|
|
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
ret = amdgpu_bo_reserve(bo, true);
|
|
|
|
|
if (unlikely(ret != 0))
|
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
|
|
amdgpu_bo_unpin(bo);
|
|
|
|
|
if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
|
|
|
|
|
bo->prime_shared_count--;
|
|
|
|
|
amdgpu_bo_unreserve(bo);
|
|
|
|
|
|
|
|
|
|
error:
|
|
|
|
|
drm_gem_map_detach(dma_buf, attach);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation
|
|
|
|
|
* @obj: GEM BO
|
|
|
|
|
*
|
|
|
|
|
* Returns:
|
|
|
|
|
* The BO's reservation object.
|
|
|
|
|
*/
|
|
|
|
|
struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
|
|
|
|
|
{
|
|
|
|
|
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
|
|
|
|
|
|
|
|
|
|
return bo->tbo.resv;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* amdgpu_gem_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
|
|
|
|
|
* @dma_buf: Shared DMA buffer
|
|
|
|
|
* @direction: Direction of DMA transfer
|
|
|
|
|
*
|
|
|
|
|
* This is called before CPU access to the shared DMA buffer's memory. If it's
|
|
|
|
|
* a read access, the buffer is moved to the GTT domain if possible, for optimal
|
|
|
|
|
* CPU read performance.
|
|
|
|
|
*
|
|
|
|
|
* Returns:
|
|
|
|
|
* 0 on success or a negative error code on failure.
|
|
|
|
|
*/
|
|
|
|
|
static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,
|
|
|
|
|
enum dma_data_direction direction)
|
|
|
|
|
{
|
|
|
|
|
struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
|
|
|
|
|
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
|
|
|
|
|
struct ttm_operation_ctx ctx = { true, false };
|
|
|
|
|
u32 domain = amdgpu_display_supported_domains(adev);
|
|
|
|
|
int ret;
|
|
|
|
|
bool reads = (direction == DMA_BIDIRECTIONAL ||
|
|
|
|
|
direction == DMA_FROM_DEVICE);
|
|
|
|
|
|
|
|
|
|
if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* move to gtt */
|
|
|
|
|
ret = amdgpu_bo_reserve(bo, false);
|
|
|
|
|
if (unlikely(ret != 0))
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
|
|
|
|
|
amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
|
|
|
|
|
ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
amdgpu_bo_unreserve(bo);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const struct dma_buf_ops amdgpu_dmabuf_ops = {
|
|
|
|
|
.attach = amdgpu_gem_map_attach,
|
|
|
|
|
.detach = amdgpu_gem_map_detach,
|
|
|
|
|
.map_dma_buf = drm_gem_map_dma_buf,
|
|
|
|
|
.unmap_dma_buf = drm_gem_unmap_dma_buf,
|
|
|
|
|
.release = drm_gem_dmabuf_release,
|
|
|
|
|
.begin_cpu_access = amdgpu_gem_begin_cpu_access,
|
|
|
|
|
.mmap = drm_gem_dmabuf_mmap,
|
|
|
|
|
.vmap = drm_gem_dmabuf_vmap,
|
|
|
|
|
.vunmap = drm_gem_dmabuf_vunmap,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
|
|
|
|
|
* @dev: DRM device
|
|
|
|
|
* @gobj: GEM BO
|
|
|
|
|
* @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
|
|
|
|
|
*
|
|
|
|
|
* The main work is done by the &drm_gem_prime_export helper, which in turn
|
|
|
|
|
* uses &amdgpu_gem_prime_res_obj.
|
|
|
|
|
*
|
|
|
|
|
* Returns:
|
|
|
|
|
* Shared DMA buffer representing the GEM BO from the given device.
|
|
|
|
|
*/
|
|
|
|
|
struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
|
|
|
|
|
struct drm_gem_object *gobj,
|
|
|
|
|
int flags)
|
|
|
|
|
{
|
|
|
|
|
struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
|
|
|
|
|
struct dma_buf *buf;
|
|
|
|
|
|
|
|
|
|
if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
|
|
|
|
|
bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
|
|
|
|
|
return ERR_PTR(-EPERM);
|
|
|
|
|
|
|
|
|
|
buf = drm_gem_prime_export(dev, gobj, flags);
|
|
|
|
|
if (!IS_ERR(buf)) {
|
|
|
|
|
buf->file->f_mapping = dev->anon_inode->i_mapping;
|
|
|
|
|
buf->ops = &amdgpu_dmabuf_ops;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return buf;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
|
|
|
|
|
* @dev: DRM device
|