drivers/mtd: Add deep sleep support for IFC
Add support of suspend, resume function to support deep sleep. Also make sure of SRAM initialization during resume. Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>5.4-rM2-2.2.x-imx-squashed
Prabhakar Kushwaha
Dong Aisheng
parent
219d54332a
commit
2fe2372125
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@ -11,6 +11,7 @@
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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@ -24,6 +25,8 @@
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struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
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EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
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#define FSL_IFC_V1_3_0 0x01030000
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#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
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/*
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* convert_ifc_address - convert the base address
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@ -298,6 +301,261 @@ err:
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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/* save ifc registers */
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static int fsl_ifc_suspend(struct device *dev)
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{
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struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
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struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
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struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
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__be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
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gpcm_evter_intr_en;
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uint32_t ifc_bank, i;
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ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
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if (!ctrl->saved_gregs)
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return -ENOMEM;
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ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
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if (!ctrl->saved_rregs)
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return -ENOMEM;
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cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
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nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
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nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
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gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
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/* IFC interrupts disabled */
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ifc_out32(0x0, &fcm->cm_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
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if (ctrl->saved_gregs) {
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for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
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ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
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ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
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ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
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ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
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ctrl->saved_gregs->amask_cs[ifc_bank].amask =
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ifc_in32(&fcm->amask_cs[ifc_bank].amask);
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ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
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ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
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ctrl->saved_gregs->csor_cs[ifc_bank].csor =
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ifc_in32(&fcm->csor_cs[ifc_bank].csor);
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for (i = 0; i < 4; i++) {
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ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
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ifc_in32(
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&fcm->ftim_cs[ifc_bank].ftim[i]);
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}
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}
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ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
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ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
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ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
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ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
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ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
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}
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if (ctrl->saved_rregs) {
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/* IFC controller NAND machine registers */
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ctrl->saved_rregs->ifc_nand.ncfgr =
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ifc_in32(&runtime->ifc_nand.ncfgr);
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ctrl->saved_rregs->ifc_nand.nand_fcr0 =
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ifc_in32(&runtime->ifc_nand.nand_fcr0);
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ctrl->saved_rregs->ifc_nand.nand_fcr1 =
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ifc_in32(&runtime->ifc_nand.nand_fcr1);
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ctrl->saved_rregs->ifc_nand.row0 =
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ifc_in32(&runtime->ifc_nand.row0);
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ctrl->saved_rregs->ifc_nand.row1 =
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ifc_in32(&runtime->ifc_nand.row1);
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ctrl->saved_rregs->ifc_nand.col0 =
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ifc_in32(&runtime->ifc_nand.col0);
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ctrl->saved_rregs->ifc_nand.col1 =
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ifc_in32(&runtime->ifc_nand.col1);
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ctrl->saved_rregs->ifc_nand.row2 =
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ifc_in32(&runtime->ifc_nand.row2);
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ctrl->saved_rregs->ifc_nand.col2 =
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ifc_in32(&runtime->ifc_nand.col2);
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ctrl->saved_rregs->ifc_nand.row3 =
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ifc_in32(&runtime->ifc_nand.row3);
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ctrl->saved_rregs->ifc_nand.col3 =
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ifc_in32(&runtime->ifc_nand.col3);
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ctrl->saved_rregs->ifc_nand.nand_fbcr =
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ifc_in32(&runtime->ifc_nand.nand_fbcr);
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ctrl->saved_rregs->ifc_nand.nand_fir0 =
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ifc_in32(&runtime->ifc_nand.nand_fir0);
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ctrl->saved_rregs->ifc_nand.nand_fir1 =
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ifc_in32(&runtime->ifc_nand.nand_fir1);
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ctrl->saved_rregs->ifc_nand.nand_fir2 =
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ifc_in32(&runtime->ifc_nand.nand_fir2);
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ctrl->saved_rregs->ifc_nand.nand_csel =
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ifc_in32(&runtime->ifc_nand.nand_csel);
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ctrl->saved_rregs->ifc_nand.nandseq_strt =
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ifc_in32(
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&runtime->ifc_nand.nandseq_strt);
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ctrl->saved_rregs->ifc_nand.nand_evter_en =
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ifc_in32(
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&runtime->ifc_nand.nand_evter_en);
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ctrl->saved_rregs->ifc_nand.nanndcr =
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ifc_in32(&runtime->ifc_nand.nanndcr);
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ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
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ifc_in32(
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&runtime->ifc_nand.nand_dll_lowcfg0);
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ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
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ifc_in32(
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&runtime->ifc_nand.nand_dll_lowcfg1);
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/* IFC controller NOR machine registers */
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ctrl->saved_rregs->ifc_nor.nor_evter_en =
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ifc_in32(
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&runtime->ifc_nor.nor_evter_en);
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ctrl->saved_rregs->ifc_nor.norcr =
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ifc_in32(&runtime->ifc_nor.norcr);
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/* IFC controller GPCM Machine registers */
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ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
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ifc_in32(
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&runtime->ifc_gpcm.gpcm_evter_en);
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}
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/* save the interrupt values */
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ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
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ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
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ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
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ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
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return 0;
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}
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/* restore ifc registers */
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static int fsl_ifc_resume(struct device *dev)
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{
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struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
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struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
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struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
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struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
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struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
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uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
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/*
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* IFC interrupts disabled
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*/
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ifc_out32(0x0, &fcm->cm_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
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if (ctrl->saved_gregs) {
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for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
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ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
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&fcm->cspr_cs[ifc_bank].cspr_ext);
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ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
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&fcm->cspr_cs[ifc_bank].cspr);
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ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
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&fcm->amask_cs[ifc_bank].amask);
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ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
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&fcm->csor_cs[ifc_bank].csor_ext);
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ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
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&fcm->csor_cs[ifc_bank].csor);
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for (i = 0; i < 4; i++) {
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ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
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&fcm->ftim_cs[ifc_bank].ftim[i]);
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}
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}
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ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
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ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
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ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
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ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
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ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
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}
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if (ctrl->saved_rregs) {
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/* IFC controller NAND machine registers */
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ifc_out32(savd_rregs->ifc_nand.ncfgr,
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&runtime->ifc_nand.ncfgr);
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ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
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&runtime->ifc_nand.nand_fcr0);
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ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
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&runtime->ifc_nand.nand_fcr1);
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ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
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ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
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ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
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ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
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ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
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ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
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ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
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ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
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ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
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&runtime->ifc_nand.nand_fbcr);
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ifc_out32(savd_rregs->ifc_nand.nand_fir0,
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&runtime->ifc_nand.nand_fir0);
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ifc_out32(savd_rregs->ifc_nand.nand_fir1,
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&runtime->ifc_nand.nand_fir1);
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ifc_out32(savd_rregs->ifc_nand.nand_fir2,
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&runtime->ifc_nand.nand_fir2);
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ifc_out32(savd_rregs->ifc_nand.nand_csel,
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&runtime->ifc_nand.nand_csel);
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ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
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&runtime->ifc_nand.nandseq_strt);
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ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
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&runtime->ifc_nand.nand_evter_en);
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ifc_out32(savd_rregs->ifc_nand.nanndcr,
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&runtime->ifc_nand.nanndcr);
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ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
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&runtime->ifc_nand.nand_dll_lowcfg0);
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ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
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&runtime->ifc_nand.nand_dll_lowcfg1);
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/* IFC controller NOR machine registers */
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ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
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&runtime->ifc_nor.nor_evter_en);
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ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
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/* IFC controller GPCM Machine registers */
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ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
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&runtime->ifc_gpcm.gpcm_evter_en);
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/* IFC interrupts enabled */
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ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
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&fcm->cm_evter_intr_en);
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ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
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&runtime->ifc_nand.nand_evter_intr_en);
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ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
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&runtime->ifc_nor.nor_evter_intr_en);
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ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
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&runtime->ifc_gpcm.gpcm_evter_intr_en);
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kfree(ctrl->saved_gregs);
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kfree(ctrl->saved_rregs);
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ctrl->saved_gregs = NULL;
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ctrl->saved_rregs = NULL;
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}
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ver = ifc_in32(&fcm->ifc_rev);
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ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
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if (ver >= FSL_IFC_V1_3_0) {
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ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN,
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&runtime->ifc_nand.ncfgr);
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/* wait for SRAM_INIT bit to be clear or timeout */
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timeout = 10;
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while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
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IFC_NAND_NCFGR_SRAM_INIT_EN) && timeout) {
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mdelay(IFC_TIMEOUT_MSECS);
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timeout--;
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}
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if (!timeout)
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dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
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}
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct of_device_id fsl_ifc_match[] = {
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{
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.compatible = "fsl,ifc",
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@ -305,10 +563,15 @@ static const struct of_device_id fsl_ifc_match[] = {
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{},
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};
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static const struct dev_pm_ops ifc_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
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};
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static struct platform_driver fsl_ifc_ctrl_driver = {
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.driver = {
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.name = "fsl-ifc",
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.of_match_table = fsl_ifc_match,
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.pm = &ifc_pm_ops,
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},
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.probe = fsl_ifc_ctrl_probe,
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.remove = fsl_ifc_ctrl_remove,
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@ -846,6 +846,11 @@ struct fsl_ifc_ctrl {
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u32 nand_stat;
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wait_queue_head_t nand_wait;
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bool little_endian;
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#ifdef CONFIG_PM_SLEEP
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/*save regs when system goes to deep sleep*/
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struct fsl_ifc_global *saved_gregs;
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struct fsl_ifc_runtime *saved_rregs;
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#endif
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};
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extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
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