From 2fe889b77c7cb344996f42bd596d714538858eb9 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 6 Aug 2019 18:35:23 +0300 Subject: [PATCH] irqchip: irq-imx-gpcv2: Disable cpuidle if no GPC_CORE_WAKE in EL3 Not all EL3 have the FSL_SIP_CONFIG_GPC_CORE_WAKE, therefore disable the cpuidle to avoid all the cores going to sleep ending up with a hang. This allows all the EL3 implementations to work with i.MX8MQ even if they do not support core wake-up through GPC as a workaround. Signed-off-by: Abel Vesa --- drivers/irqchip/irq-imx-gpcv2.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index 23b47c7053af..4f6de871b220 100644 --- a/drivers/irqchip/irq-imx-gpcv2.c +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -13,6 +13,7 @@ #include #include #include +#include #define FSL_SIP_GPC 0xC2000000 #define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05 @@ -96,6 +97,16 @@ static void imx_gpcv2_raise_softirq(const struct cpumask *mask, static void imx_gpcv2_wake_request_fixup(void) { struct regmap *iomux_gpr; + struct arm_smccc_res res; + + arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_CORE_WAKE, + 0, 0, 0, 0, 0, 0, &res); + + if (res.a0) { + pr_warn("irq-imx-gpcv2: EL3 does not support FSL_SIP_CONFIG_GPC_CORE_WAKE, disabling cpuidle.\n"); + disable_cpuidle(); + return; + } /* hijack the already registered smp cross call handler */ __gic_v3_smp_cross_call = __smp_cross_call;