ASoC: davinci: fix codec start and stop functions
According to DM365 voice codec data sheet at [1], before starting recording or playback, ADC/DAC modules should follow a reset and enable cycle. Writing a 1 to the ADC/DAC bit in the register resets the module and clearing the bit to 0 will enable the module. But the driver seems to be doing the reverse of it. [1] http://focus.ti.com/lit/ug/sprufi9b/sprufi9b.pdf Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org
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@ -62,9 +62,9 @@ static void davinci_vcif_start(struct snd_pcm_substream *substream)
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w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
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w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
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else
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else
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
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writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
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writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
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}
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}
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@ -80,9 +80,9 @@ static void davinci_vcif_stop(struct snd_pcm_substream *substream)
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/* Reset transmitter/receiver and sample rate/frame sync generators */
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/* Reset transmitter/receiver and sample rate/frame sync generators */
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w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
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w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
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else
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else
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
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MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
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writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
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writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
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}
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}
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