soc: xilinx: vcu: use vcu-settings syscon registers
Switch the "logicoreip" registers to the new xlnx,vcu-settings binding to be able to read the settings if the settings are specified in a separate device tree node that is shared with other drivers. If the driver is not able to find a node with the new binding, fall back to check for the logicore register bank to be backwards compatible. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Link: https://lore.kernel.org/r/20201109134818.4159342-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>zero-sugar-mainline-defconfig
Michael Tretter
Michal Simek
parent
a3857f89dd
commit
30b79eb1f9
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@ -4,6 +4,7 @@ menu "Xilinx SoC drivers"
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config XILINX_VCU
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tristate "Xilinx VCU logicoreIP Init"
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depends on HAS_IOMEM
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select REGMAP_MMIO
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help
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Provides the driver to enable and disable the isolation between the
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processing system and programmable logic part by using the logicoreIP
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@ -10,39 +10,12 @@
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/xlnx-vcu.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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/* Address map for different registers implemented in the VCU LogiCORE IP. */
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#define VCU_ECODER_ENABLE 0x00
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#define VCU_DECODER_ENABLE 0x04
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#define VCU_MEMORY_DEPTH 0x08
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#define VCU_ENC_COLOR_DEPTH 0x0c
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#define VCU_ENC_VERTICAL_RANGE 0x10
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#define VCU_ENC_FRAME_SIZE_X 0x14
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#define VCU_ENC_FRAME_SIZE_Y 0x18
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#define VCU_ENC_COLOR_FORMAT 0x1c
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#define VCU_ENC_FPS 0x20
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#define VCU_MCU_CLK 0x24
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#define VCU_CORE_CLK 0x28
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#define VCU_PLL_BYPASS 0x2c
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#define VCU_ENC_CLK 0x30
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#define VCU_PLL_CLK 0x34
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#define VCU_ENC_VIDEO_STANDARD 0x38
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#define VCU_STATUS 0x3c
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#define VCU_AXI_ENC_CLK 0x40
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#define VCU_AXI_DEC_CLK 0x44
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#define VCU_AXI_MCU_CLK 0x48
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#define VCU_DEC_VIDEO_STANDARD 0x4c
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#define VCU_DEC_FRAME_SIZE_X 0x50
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#define VCU_DEC_FRAME_SIZE_Y 0x54
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#define VCU_DEC_FPS 0x58
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#define VCU_BUFFER_B_FRAME 0x5c
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#define VCU_WPP_EN 0x60
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#define VCU_PLL_CLK_DEC 0x64
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#define VCU_GASKET_INIT 0x74
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#define VCU_GASKET_VALUE 0x03
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#include <linux/regmap.h>
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/* vcu slcr registers, bitmask and shift */
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#define VCU_PLL_CTRL 0x24
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@ -106,11 +79,20 @@ struct xvcu_device {
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struct device *dev;
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struct clk *pll_ref;
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struct clk *aclk;
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void __iomem *logicore_reg_ba;
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struct regmap *logicore_reg_ba;
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void __iomem *vcu_slcr_ba;
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u32 coreclk;
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};
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static struct regmap_config vcu_settings_regmap_config = {
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.name = "regmap",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0xfff,
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.cache_type = REGCACHE_NONE,
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};
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/**
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* struct xvcu_pll_cfg - Helper data
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* @fbdiv: The integer portion of the feedback divider to the PLL
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@ -300,10 +282,12 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu)
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int ret, i;
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const struct xvcu_pll_cfg *found = NULL;
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inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK);
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deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC);
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coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ;
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mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ;
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regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK, &inte);
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regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC, &deci);
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regmap_read(xvcu->logicore_reg_ba, VCU_CORE_CLK, &coreclk);
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coreclk *= MHZ;
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regmap_read(xvcu->logicore_reg_ba, VCU_MCU_CLK, &mcuclk);
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mcuclk *= MHZ;
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if (!mcuclk || !coreclk) {
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dev_err(xvcu->dev, "Invalid mcu and core clock data\n");
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return -EINVAL;
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@ -498,6 +482,7 @@ static int xvcu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct xvcu_device *xvcu;
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void __iomem *regs;
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int ret;
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xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL);
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@ -518,17 +503,32 @@ static int xvcu_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "logicore");
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if (!res) {
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dev_err(&pdev->dev, "get logicore memory resource failed.\n");
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return -ENODEV;
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}
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xvcu->logicore_reg_ba =
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syscon_regmap_lookup_by_compatible("xlnx,vcu-settings");
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if (IS_ERR(xvcu->logicore_reg_ba)) {
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dev_info(&pdev->dev,
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"could not find xlnx,vcu-settings: trying direct register access\n");
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xvcu->logicore_reg_ba = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!xvcu->logicore_reg_ba) {
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dev_err(&pdev->dev, "logicore register mapping failed.\n");
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return -ENOMEM;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, "logicore");
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if (!res) {
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dev_err(&pdev->dev, "get logicore memory resource failed.\n");
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return -ENODEV;
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}
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regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!regs) {
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dev_err(&pdev->dev, "logicore register mapping failed.\n");
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return -ENOMEM;
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}
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xvcu->logicore_reg_ba =
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devm_regmap_init_mmio(&pdev->dev, regs,
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&vcu_settings_regmap_config);
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if (IS_ERR(xvcu->logicore_reg_ba)) {
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dev_err(&pdev->dev, "failed to init regmap\n");
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return PTR_ERR(xvcu->logicore_reg_ba);
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}
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}
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xvcu->aclk = devm_clk_get(&pdev->dev, "aclk");
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@ -560,7 +560,7 @@ static int xvcu_probe(struct platform_device *pdev)
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* Bit 0 : Gasket isolation
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* Bit 1 : put VCU out of reset
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*/
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xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE);
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regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE);
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/* Do the PLL Settings based on the ref clk,core and mcu clk freq */
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ret = xvcu_set_pll(xvcu);
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@ -597,7 +597,7 @@ static int xvcu_remove(struct platform_device *pdev)
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return -ENODEV;
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/* Add the the Gasket isolation and put the VCU in reset. */
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xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0);
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regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0);
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clk_disable_unprepare(xvcu->pll_ref);
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clk_disable_unprepare(xvcu->aclk);
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@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 Pengutronix, Michael Tretter <kernel@pengutronix.de>
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*/
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#ifndef __XLNX_VCU_H
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#define __XLNX_VCU_H
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#define VCU_ECODER_ENABLE 0x00
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#define VCU_DECODER_ENABLE 0x04
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#define VCU_MEMORY_DEPTH 0x08
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#define VCU_ENC_COLOR_DEPTH 0x0c
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#define VCU_ENC_VERTICAL_RANGE 0x10
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#define VCU_ENC_FRAME_SIZE_X 0x14
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#define VCU_ENC_FRAME_SIZE_Y 0x18
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#define VCU_ENC_COLOR_FORMAT 0x1c
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#define VCU_ENC_FPS 0x20
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#define VCU_MCU_CLK 0x24
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#define VCU_CORE_CLK 0x28
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#define VCU_PLL_BYPASS 0x2c
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#define VCU_ENC_CLK 0x30
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#define VCU_PLL_CLK 0x34
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#define VCU_ENC_VIDEO_STANDARD 0x38
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#define VCU_STATUS 0x3c
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#define VCU_AXI_ENC_CLK 0x40
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#define VCU_AXI_DEC_CLK 0x44
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#define VCU_AXI_MCU_CLK 0x48
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#define VCU_DEC_VIDEO_STANDARD 0x4c
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#define VCU_DEC_FRAME_SIZE_X 0x50
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#define VCU_DEC_FRAME_SIZE_Y 0x54
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#define VCU_DEC_FPS 0x58
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#define VCU_BUFFER_B_FRAME 0x5c
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#define VCU_WPP_EN 0x60
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#define VCU_PLL_CLK_DEC 0x64
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#define VCU_GASKET_INIT 0x74
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#define VCU_GASKET_VALUE 0x03
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#endif /* __XLNX_VCU_H */
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