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drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

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Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Rodrigo Vivi 2013-05-06 19:37:34 -03:00 committed by Daniel Vetter
parent abe959c7e0
commit 30ca7c6f97
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -268,6 +268,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
IVB_DPFC_CTL_FENCE_EN |
intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
/* WaFbcAsynchFlipDisableFbcQueue */
I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
I915_WRITE(SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | obj->fence_reg);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);