[ARM] 3215/1: Iomega NAS 100d (MACH_NAS100D) machine support
Patch from Rod Whitby This patch adds support for a new arm/ixp4xx machine - the Iomega NAS 100d network attached storage product. The NAS100D is a consumer device containing a 266MHz Intel IXP420 processor, 16MB of flash, 64MB of RAM, a 160Gb internal IDE hard disk, and 802.11b/g wireless on an Atheros mini-PCI card. Work on porting the latest 2.6.x kernel to this device is being done by the NSLU2-Linux project (the same team who maintains the port to the Linksys NSLU2 device). In particular, the majority of this patch was authored by Alessandro Zummo, based on the work done for MACH_NSLU2 support by the NSLU2-Linux core team of developers. MACH_NAS100D (as implemented by this patch) can be enabled in jumbo ixp4xx kernels without any affect on the other machines supported by that kernel. This patch applies cleanly against 2.6.15-rc7 and should be trivial to apply to later kernel versions. It does not depend upon any other patches. Modified files (and number of lines inserted): arch/arm/mach-ixp4xx/Kconfig | 8 arch/arm/mach-ixp4xx/Makefile | 1 include/asm-arm/arch-ixp4xx/hardware.h | 1 include/asm-arm/arch-ixp4xx/irqs.h | 9 include/asm-arm/arch-ixp4xx/nas100d.h | 75 arch/arm/mach-ixp4xx/nas100d-pci.c | 77 arch/arm/mach-ixp4xx/nas100d-power.c | 69 arch/arm/mach-ixp4xx/nas100d-setup.c | 133 -- Rod Whitby (NSLU2-Linux project lead) Signed-off-by: Rod Whitby <rod@whitby.id.au> Signed-off-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Rod Whitby
Russell King
parent
f7e8bbb820
commit
3145d8a6cc
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@ -71,6 +71,14 @@ config ARCH_PRPMC1100
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PrPCM1100 Processor Mezanine Module. For more information on
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this platform, see <file:Documentation/arm/IXP4xx>.
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config MACH_NAS100D
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bool
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prompt "NAS100D"
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help
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Say 'Y' here if you want your kernel to support Iomega's
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NAS 100d device. For more information on this platform,
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see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
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#
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# Avila and IXDP share the same source for now. Will change in future
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#
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@ -9,4 +9,5 @@ obj-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o coyote-setup.o
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obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o
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obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o gtwx5715-setup.o
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obj-$(CONFIG_MACH_NSLU2) += nslu2-pci.o nslu2-setup.o nslu2-power.o
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obj-$(CONFIG_MACH_NAS100D) += nas100d-pci.o nas100d-setup.o nas100d-power.o
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@ -0,0 +1,77 @@
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/*
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* arch/arm/mach-ixp4xx/nas100d-pci.c
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*
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* NAS 100d board-level PCI initialization
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*
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* based on ixdp425-pci.c:
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* Maintainer: http://www.nslu2-linux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/config.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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void __init nas100d_pci_preinit(void)
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{
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set_irq_type(IRQ_NAS100D_PCI_INTA, IRQT_LOW);
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set_irq_type(IRQ_NAS100D_PCI_INTB, IRQT_LOW);
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set_irq_type(IRQ_NAS100D_PCI_INTC, IRQT_LOW);
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set_irq_type(IRQ_NAS100D_PCI_INTD, IRQT_LOW);
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set_irq_type(IRQ_NAS100D_PCI_INTE, IRQT_LOW);
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gpio_line_isr_clear(NAS100D_PCI_INTA_PIN);
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gpio_line_isr_clear(NAS100D_PCI_INTB_PIN);
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gpio_line_isr_clear(NAS100D_PCI_INTC_PIN);
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gpio_line_isr_clear(NAS100D_PCI_INTD_PIN);
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gpio_line_isr_clear(NAS100D_PCI_INTE_PIN);
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ixp4xx_pci_preinit();
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}
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static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] =
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{
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{ IRQ_NAS100D_PCI_INTA, -1, -1 },
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{ IRQ_NAS100D_PCI_INTB, -1, -1 },
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{ IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE },
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};
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int irq = -1;
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if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV &&
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pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES)
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irq = pci_irq_table[slot-1][pin-1];
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return irq;
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}
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struct hw_pci __initdata nas100d_pci = {
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.nr_controllers = 1,
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.preinit = nas100d_pci_preinit,
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.swizzle = pci_std_swizzle,
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.setup = ixp4xx_setup,
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.scan = ixp4xx_scan_bus,
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.map_irq = nas100d_map_irq,
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};
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int __init nas100d_pci_init(void)
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{
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if (machine_is_nas100d())
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pci_common_init(&nas100d_pci);
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return 0;
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}
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subsys_initcall(nas100d_pci_init);
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@ -0,0 +1,69 @@
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/*
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* arch/arm/mach-ixp4xx/nas100d-power.c
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*
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* NAS 100d Power/Reset driver
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*
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* Copyright (C) 2005 Tower Technologies
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*
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* based on nas100d-io.c
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* Copyright (C) 2004 Karen Spearel
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*
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* Author: Alessandro Zummo <a.zummo@towertech.it>
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* Maintainers: http://www.nslu2-linux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <asm/mach-types.h>
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extern void ctrl_alt_del(void);
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static irqreturn_t nas100d_reset_handler(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* Signal init to do the ctrlaltdel action, this will bypass init if
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* it hasn't started and do a kernel_restart.
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*/
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ctrl_alt_del();
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return IRQ_HANDLED;
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}
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static int __init nas100d_power_init(void)
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{
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if (!(machine_is_nas100d()))
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return 0;
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set_irq_type(NAS100D_RB_IRQ, IRQT_LOW);
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gpio_line_isr_clear(NAS100D_RB_GPIO);
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if (request_irq(NAS100D_RB_IRQ, &nas100d_reset_handler,
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SA_INTERRUPT, "NAS100D reset button", NULL) < 0) {
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printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
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NAS100D_RB_IRQ);
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return -EIO;
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}
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return 0;
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}
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static void __exit nas100d_power_exit(void)
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{
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free_irq(NAS100D_RB_IRQ, NULL);
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}
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module_init(nas100d_power_init);
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module_exit(nas100d_power_exit);
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MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
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MODULE_DESCRIPTION("NAS100D Power/Reset driver");
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MODULE_LICENSE("GPL");
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@ -0,0 +1,133 @@
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/*
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* arch/arm/mach-ixp4xx/nas100d-setup.c
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*
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* NAS 100d board-setup
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*
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* based ixdp425-setup.c:
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* Author: Alessandro Zummo <a.zummo@towertech.it>
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* Author: Rod Whitby <rod@whitby.id.au>
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* Maintainers: http://www.nslu2-linux.org/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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static struct flash_platform_data nas100d_flash_data = {
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.map_name = "cfi_probe",
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.width = 2,
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};
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static struct resource nas100d_flash_resource = {
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.start = NAS100D_FLASH_BASE,
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.end = NAS100D_FLASH_BASE + NAS100D_FLASH_SIZE,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device nas100d_flash = {
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.name = "IXP4XX-Flash",
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.id = 0,
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.dev.platform_data = &nas100d_flash_data,
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.num_resources = 1,
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.resource = &nas100d_flash_resource,
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};
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static struct ixp4xx_i2c_pins nas100d_i2c_gpio_pins = {
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.sda_pin = NAS100D_SDA_PIN,
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.scl_pin = NAS100D_SCL_PIN,
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};
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static struct platform_device nas100d_i2c_controller = {
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.name = "IXP4XX-I2C",
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.id = 0,
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.dev.platform_data = &nas100d_i2c_gpio_pins,
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.num_resources = 0,
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};
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static struct resource nas100d_uart_resources[] = {
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{
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.start = IXP4XX_UART1_BASE_PHYS,
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.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IXP4XX_UART2_BASE_PHYS,
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.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct plat_serial8250_port nas100d_uart_data[] = {
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{
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.mapbase = IXP4XX_UART1_BASE_PHYS,
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.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART1,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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{
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.mapbase = IXP4XX_UART2_BASE_PHYS,
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.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART2,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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{ }
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};
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static struct platform_device nas100d_uart = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev.platform_data = nas100d_uart_data,
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.num_resources = 2,
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.resource = nas100d_uart_resources,
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};
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static struct platform_device *nas100d_devices[] __initdata = {
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&nas100d_i2c_controller,
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&nas100d_flash,
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&nas100d_uart,
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};
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static void nas100d_power_off(void)
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{
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/* This causes the box to drop the power and go dead. */
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/* enable the pwr cntl gpio */
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gpio_line_config(NAS100D_PO_GPIO, IXP4XX_GPIO_OUT);
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/* do the deed */
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gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH);
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}
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static void __init nas100d_init(void)
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{
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ixp4xx_sys_init();
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pm_power_off = nas100d_power_off;
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platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));
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}
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MACHINE_START(NAS100D, "Iomega NAS 100d")
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/* Maintainer: www.nslu2-linux.org */
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.phys_ram = PHYS_OFFSET,
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.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
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.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.map_io = ixp4xx_map_io,
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.init_irq = ixp4xx_init_irq,
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.timer = &ixp4xx_timer,
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.init_machine = nas100d_init,
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MACHINE_END
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@ -45,5 +45,6 @@ extern unsigned int processor_id;
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#include "coyote.h"
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#include "prpmc1100.h"
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#include "nslu2.h"
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#include "nas100d.h"
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#endif /* _ASM_ARCH_HARDWARE_H */
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@ -100,4 +100,13 @@
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#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
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/*
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* NAS100D board IRQs
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*/
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#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
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#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
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#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
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#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
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#endif
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@ -0,0 +1,75 @@
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/*
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* include/asm-arm/arch-ixp4xx/nas100d.h
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*
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* NAS100D platform specific definitions
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*
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* Copyright (c) 2005 Tower Technologies
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*
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* Author: Alessandro Zummo <a.zummo@towertech.it>
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*
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* based on ixdp425.h:
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* Copyright 2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#error "Do not include this directly, instead #include <asm/hardware.h>"
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#endif
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#define NAS100D_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
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#define NAS100D_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
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#define NAS100D_SDA_PIN 6
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#define NAS100D_SCL_PIN 5
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/*
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* NAS100D PCI IRQs
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*/
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#define NAS100D_PCI_MAX_DEV 3
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#define NAS100D_PCI_IRQ_LINES 3
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/* PCI controller GPIO to IRQ pin mappings */
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#define NAS100D_PCI_INTA_PIN 11
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#define NAS100D_PCI_INTB_PIN 10
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#define NAS100D_PCI_INTC_PIN 9
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#define NAS100D_PCI_INTD_PIN 8
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#define NAS100D_PCI_INTE_PIN 7
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/* GPIO */
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#define NAS100D_GPIO0 0
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#define NAS100D_GPIO1 1
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#define NAS100D_GPIO2 2
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#define NAS100D_GPIO3 3
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#define NAS100D_GPIO4 4
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#define NAS100D_GPIO5 5
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#define NAS100D_GPIO6 6
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#define NAS100D_GPIO7 7
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#define NAS100D_GPIO8 8
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#define NAS100D_GPIO9 9
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#define NAS100D_GPIO10 10
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#define NAS100D_GPIO11 11
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#define NAS100D_GPIO12 12
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#define NAS100D_GPIO13 13
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#define NAS100D_GPIO14 14
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#define NAS100D_GPIO15 15
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/* Buttons */
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#define NAS100D_PB_GPIO NAS100D_GPIO14
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#define NAS100D_RB_GPIO NAS100D_GPIO4
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#define NAS100D_PO_GPIO NAS100D_GPIO12 /* power off */
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#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14
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#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4
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/*
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#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO)
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#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO)
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#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO)
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*/
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Reference in New Issue