Merge branch 'x86/uv' into x86/core
Ingo Molnar
commit
31bbed527e
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@ -379,6 +379,7 @@ static inline u32 safe_apic_wait_icr_idle(void)
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static inline void ack_APIC_irq(void)
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{
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction
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* ... yummie.
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@ -386,6 +387,7 @@ static inline void ack_APIC_irq(void)
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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#endif
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}
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static inline unsigned default_get_apic_id(unsigned long x)
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@ -33,6 +33,8 @@ BUILD_INTERRUPT3(invalidate_interrupt7,INVALIDATE_TLB_VECTOR_START+7,
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smp_invalidate_interrupt)
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#endif
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BUILD_INTERRUPT(generic_interrupt, GENERIC_INTERRUPT_VECTOR)
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/*
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* every pentium local APIC has two 'local interrupts', with a
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* soft-definable vector attached to both interrupts, one of
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@ -12,6 +12,7 @@ typedef struct {
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unsigned int apic_timer_irqs; /* arch dependent */
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unsigned int irq_spurious_count;
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#endif
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unsigned int generic_irqs; /* arch dependent */
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#ifdef CONFIG_SMP
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unsigned int irq_resched_count;
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unsigned int irq_call_count;
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@ -27,6 +27,7 @@
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/* Interrupt handlers registered during init_IRQ */
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extern void apic_timer_interrupt(void);
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extern void generic_interrupt(void);
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extern void error_interrupt(void);
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extern void spurious_interrupt(void);
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extern void thermal_interrupt(void);
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@ -36,6 +36,7 @@ static inline int irq_canonicalize(int irq)
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extern void fixup_irqs(void);
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#endif
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extern void (*generic_interrupt_extension)(void);
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extern void init_IRQ(void);
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extern void native_init_IRQ(void);
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extern bool handle_irq(unsigned irq, struct pt_regs *regs);
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@ -111,6 +111,11 @@
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*/
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#define LOCAL_PERF_VECTOR 0xee
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/*
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* Generic system vector for platform specific use
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*/
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#define GENERIC_INTERRUPT_VECTOR 0xed
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/*
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* First APIC vector available to drivers: (vectors 0x30-0xee) we
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* start at 0x31(0x41) to spread out vectors evenly between priority
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@ -199,6 +199,10 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
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#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
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/* Loop through all installed blades */
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#define for_each_possible_blade(bid) \
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for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
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/*
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* Macros for converting between kernel virtual addresses, socket local physical
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* addresses, and UV global physical addresses.
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@ -111,7 +111,7 @@ obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o # NB rename without _64
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###
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# 64 bit specific files
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ifeq ($(CONFIG_X86_64),y)
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obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o
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obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
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obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o
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obj-$(CONFIG_AUDIT) += audit_64.o
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@ -984,6 +984,8 @@ apicinterrupt UV_BAU_MESSAGE \
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#endif
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apicinterrupt LOCAL_TIMER_VECTOR \
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apic_timer_interrupt smp_apic_timer_interrupt
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apicinterrupt GENERIC_INTERRUPT_VECTOR \
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generic_interrupt smp_generic_interrupt
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#ifdef CONFIG_SMP
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apicinterrupt INVALIDATE_TLB_VECTOR_START+0 \
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@ -15,6 +15,9 @@
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atomic_t irq_err_count;
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/* Function pointer for generic interrupt vector handling */
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void (*generic_interrupt_extension)(void) = NULL;
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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@ -56,6 +59,12 @@ static int show_other_interrupts(struct seq_file *p)
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seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
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seq_printf(p, " Local timer interrupts\n");
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#endif
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if (generic_interrupt_extension) {
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seq_printf(p, "PLT: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->generic_irqs);
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seq_printf(p, " Platform interrupts\n");
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}
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#ifdef CONFIG_SMP
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seq_printf(p, "RES: ");
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for_each_online_cpu(j)
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@ -163,6 +172,8 @@ u64 arch_irq_stat_cpu(unsigned int cpu)
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#ifdef CONFIG_X86_LOCAL_APIC
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sum += irq_stats(cpu)->apic_timer_irqs;
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#endif
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if (generic_interrupt_extension)
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sum += irq_stats(cpu)->generic_irqs;
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#ifdef CONFIG_SMP
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sum += irq_stats(cpu)->irq_resched_count;
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sum += irq_stats(cpu)->irq_call_count;
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@ -226,4 +237,27 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
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return 1;
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}
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/*
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* Handler for GENERIC_INTERRUPT_VECTOR.
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*/
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void smp_generic_interrupt(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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ack_APIC_irq();
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exit_idle();
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irq_enter();
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inc_irq_stat(generic_irqs);
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if (generic_interrupt_extension)
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generic_interrupt_extension();
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irq_exit();
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set_irq_regs(old_regs);
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}
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EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
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@ -175,6 +175,9 @@ void __init native_init_IRQ(void)
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* generic IPI for platform specific use */
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alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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@ -147,6 +147,9 @@ static void __init apic_intr_init(void)
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* generic IPI for platform specific use */
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alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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@ -0,0 +1,393 @@
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/*
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* SGI RTC clock/timer routines.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (c) Dimitri Sivanich
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*/
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#include <linux/clockchips.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/bios.h>
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#include <asm/uv/uv.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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#define RTC_NAME "sgi_rtc"
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static cycle_t uv_read_rtc(void);
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static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
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static void uv_rtc_timer_setup(enum clock_event_mode,
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struct clock_event_device *);
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static struct clocksource clocksource_uv = {
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.name = RTC_NAME,
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.rating = 400,
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.read = uv_read_rtc,
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.mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
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.shift = 10,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static struct clock_event_device clock_event_device_uv = {
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.name = RTC_NAME,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 20,
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.rating = 400,
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.irq = -1,
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.set_next_event = uv_rtc_next_event,
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.set_mode = uv_rtc_timer_setup,
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.event_handler = NULL,
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};
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static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
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/* There is one of these allocated per node */
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struct uv_rtc_timer_head {
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spinlock_t lock;
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/* next cpu waiting for timer, local node relative: */
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int next_cpu;
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/* number of cpus on this node: */
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int ncpus;
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struct {
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int lcpu; /* systemwide logical cpu number */
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u64 expires; /* next timer expiration for this cpu */
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} cpu[1];
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};
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/*
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* Access to uv_rtc_timer_head via blade id.
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*/
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static struct uv_rtc_timer_head **blade_info __read_mostly;
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static int uv_rtc_enable;
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/*
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* Hardware interface routines
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*/
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/* Send IPIs to another node */
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static void uv_rtc_send_IPI(int cpu)
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{
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unsigned long apicid, val;
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int pnode;
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apicid = cpu_physical_id(cpu);
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pnode = uv_apicid_to_pnode(apicid);
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val = (1UL << UVH_IPI_INT_SEND_SHFT) |
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(apicid << UVH_IPI_INT_APIC_ID_SHFT) |
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(GENERIC_INTERRUPT_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
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uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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}
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/* Check for an RTC interrupt pending */
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static int uv_intr_pending(int pnode)
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{
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return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
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UVH_EVENT_OCCURRED0_RTC1_MASK;
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}
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/* Setup interrupt and return non-zero if early expiration occurred. */
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static int uv_setup_intr(int cpu, u64 expires)
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{
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u64 val;
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int pnode = uv_cpu_to_pnode(cpu);
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
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UVH_RTC1_INT_CONFIG_M_MASK);
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uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
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uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
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UVH_EVENT_OCCURRED0_RTC1_MASK);
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val = (GENERIC_INTERRUPT_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
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((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
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/* Set configuration */
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
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/* Initialize comparator value */
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uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
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return (expires < uv_read_rtc() && !uv_intr_pending(pnode));
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}
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/*
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* Per-cpu timer tracking routines
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*/
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static __init void uv_rtc_deallocate_timers(void)
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{
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int bid;
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for_each_possible_blade(bid) {
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kfree(blade_info[bid]);
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}
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kfree(blade_info);
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}
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/* Allocate per-node list of cpu timer expiration times. */
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static __init int uv_rtc_allocate_timers(void)
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{
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int cpu;
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blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
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if (!blade_info)
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return -ENOMEM;
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memset(blade_info, 0, uv_possible_blades * sizeof(void *));
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for_each_present_cpu(cpu) {
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int nid = cpu_to_node(cpu);
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int bid = uv_cpu_to_blade_id(cpu);
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int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
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struct uv_rtc_timer_head *head = blade_info[bid];
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if (!head) {
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head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
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(uv_blade_nr_possible_cpus(bid) *
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2 * sizeof(u64)),
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GFP_KERNEL, nid);
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if (!head) {
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uv_rtc_deallocate_timers();
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return -ENOMEM;
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}
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spin_lock_init(&head->lock);
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head->ncpus = uv_blade_nr_possible_cpus(bid);
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head->next_cpu = -1;
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blade_info[bid] = head;
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}
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head->cpu[bcpu].lcpu = cpu;
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head->cpu[bcpu].expires = ULLONG_MAX;
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}
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return 0;
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}
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/* Find and set the next expiring timer. */
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static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
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{
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u64 lowest = ULLONG_MAX;
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int c, bcpu = -1;
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head->next_cpu = -1;
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for (c = 0; c < head->ncpus; c++) {
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u64 exp = head->cpu[c].expires;
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if (exp < lowest) {
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bcpu = c;
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lowest = exp;
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}
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}
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if (bcpu >= 0) {
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head->next_cpu = bcpu;
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c = head->cpu[bcpu].lcpu;
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if (uv_setup_intr(c, lowest))
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/* If we didn't set it up in time, trigger */
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uv_rtc_send_IPI(c);
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} else {
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uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
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UVH_RTC1_INT_CONFIG_M_MASK);
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}
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}
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/*
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* Set expiration time for current cpu.
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*
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* Returns 1 if we missed the expiration time.
|
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*/
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static int uv_rtc_set_timer(int cpu, u64 expires)
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{
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int pnode = uv_cpu_to_pnode(cpu);
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int bid = uv_cpu_to_blade_id(cpu);
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struct uv_rtc_timer_head *head = blade_info[bid];
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int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
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u64 *t = &head->cpu[bcpu].expires;
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unsigned long flags;
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int next_cpu;
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spin_lock_irqsave(&head->lock, flags);
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next_cpu = head->next_cpu;
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*t = expires;
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/* Will this one be next to go off? */
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if (next_cpu < 0 || bcpu == next_cpu ||
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expires < head->cpu[next_cpu].expires) {
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head->next_cpu = bcpu;
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if (uv_setup_intr(cpu, expires)) {
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*t = ULLONG_MAX;
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uv_rtc_find_next_timer(head, pnode);
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spin_unlock_irqrestore(&head->lock, flags);
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return 1;
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}
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}
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spin_unlock_irqrestore(&head->lock, flags);
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return 0;
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||||
}
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||||
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/*
|
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* Unset expiration time for current cpu.
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*
|
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* Returns 1 if this timer was pending.
|
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*/
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static int uv_rtc_unset_timer(int cpu)
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{
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int pnode = uv_cpu_to_pnode(cpu);
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int bid = uv_cpu_to_blade_id(cpu);
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struct uv_rtc_timer_head *head = blade_info[bid];
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int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
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u64 *t = &head->cpu[bcpu].expires;
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unsigned long flags;
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int rc = 0;
|
||||
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spin_lock_irqsave(&head->lock, flags);
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if (head->next_cpu == bcpu && uv_read_rtc() >= *t)
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rc = 1;
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||||
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||||
*t = ULLONG_MAX;
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|
||||
/* Was the hardware setup for this timer? */
|
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if (head->next_cpu == bcpu)
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uv_rtc_find_next_timer(head, pnode);
|
||||
|
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spin_unlock_irqrestore(&head->lock, flags);
|
||||
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return rc;
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||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Kernel interface routines.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Read the RTC.
|
||||
*/
|
||||
static cycle_t uv_read_rtc(void)
|
||||
{
|
||||
return (cycle_t)uv_read_local_mmr(UVH_RTC);
|
||||
}
|
||||
|
||||
/*
|
||||
* Program the next event, relative to now
|
||||
*/
|
||||
static int uv_rtc_next_event(unsigned long delta,
|
||||
struct clock_event_device *ced)
|
||||
{
|
||||
int ced_cpu = cpumask_first(ced->cpumask);
|
||||
|
||||
return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc());
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the RTC timer in oneshot mode
|
||||
*/
|
||||
static void uv_rtc_timer_setup(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
int ced_cpu = cpumask_first(evt->cpumask);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
/* Nothing to do here yet */
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
uv_rtc_unset_timer(ced_cpu);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void uv_rtc_interrupt(void)
|
||||
{
|
||||
struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
if (!ced || !ced->event_handler)
|
||||
return;
|
||||
|
||||
if (uv_rtc_unset_timer(cpu) != 1)
|
||||
return;
|
||||
|
||||
ced->event_handler(ced);
|
||||
}
|
||||
|
||||
static int __init uv_enable_rtc(char *str)
|
||||
{
|
||||
uv_rtc_enable = 1;
|
||||
|
||||
return 1;
|
||||
}
|
||||
__setup("uvrtc", uv_enable_rtc);
|
||||
|
||||
static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
|
||||
{
|
||||
struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
|
||||
|
||||
*ced = clock_event_device_uv;
|
||||
ced->cpumask = cpumask_of(smp_processor_id());
|
||||
clockevents_register_device(ced);
|
||||
}
|
||||
|
||||
static __init int uv_rtc_setup_clock(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!uv_rtc_enable || !is_uv_system() || generic_interrupt_extension)
|
||||
return -ENODEV;
|
||||
|
||||
generic_interrupt_extension = uv_rtc_interrupt;
|
||||
|
||||
clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
|
||||
clocksource_uv.shift);
|
||||
|
||||
rc = clocksource_register(&clocksource_uv);
|
||||
if (rc) {
|
||||
generic_interrupt_extension = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Setup and register clockevents */
|
||||
rc = uv_rtc_allocate_timers();
|
||||
if (rc) {
|
||||
clocksource_unregister(&clocksource_uv);
|
||||
generic_interrupt_extension = NULL;
|
||||
return rc;
|
||||
}
|
||||
|
||||
clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
|
||||
NSEC_PER_SEC, clock_event_device_uv.shift);
|
||||
|
||||
clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
|
||||
sn_rtc_cycles_per_second;
|
||||
|
||||
clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
|
||||
(NSEC_PER_SEC / sn_rtc_cycles_per_second);
|
||||
|
||||
rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
|
||||
if (rc) {
|
||||
clocksource_unregister(&clocksource_uv);
|
||||
generic_interrupt_extension = NULL;
|
||||
uv_rtc_deallocate_timers();
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
arch_initcall(uv_rtc_setup_clock);
|
||||
Loading…
Reference in New Issue