sh: support SIU sourcing from external clock on sh7722
Implement .set_rate() for all SH "div4 clocks," .enable(), .disable(), and .set_parent() for those, that support them. This allows, among other uses, reparenting of SIU clocks to the external source, and enabling and disabling of the IrDA clock on sh7722. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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14965f16b4
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@ -148,6 +148,10 @@ int sh_clk_mstp32_register(struct clk *clks, int nr);
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int sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table);
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int sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table);
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int sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table);
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#define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
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{ \
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@ -160,13 +160,81 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = clk->priv;
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u32 value;
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int ret;
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if (!strcmp("pll_clk", parent->name))
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value = __raw_readl(clk->enable_reg) & ~(1 << 7);
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else
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value = __raw_readl(clk->enable_reg) | (1 << 7);
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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__raw_writel(value, clk->enable_reg);
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/* Rebiuld the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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return 0;
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}
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static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
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{
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unsigned long value;
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int idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~0xf;
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value |= idx;
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__raw_writel(value, clk->enable_reg);
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return 0;
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}
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static int sh_clk_div4_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
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return 0;
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}
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static void sh_clk_div4_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
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}
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static struct clk_ops sh_clk_div4_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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};
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int __init sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table)
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static struct clk_ops sh_clk_div4_enable_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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};
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static struct clk_ops sh_clk_div4_reparent_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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.set_parent = sh_clk_div4_set_parent,
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};
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static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
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struct clk_div_mult_table *table, struct clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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@ -185,7 +253,7 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &sh_clk_div4_clk_ops;
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clkp->ops = ops;
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clkp->id = -1;
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clkp->priv = table;
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@ -198,6 +266,26 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
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return ret;
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}
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int __init sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
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}
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int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_enable_clk_ops);
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}
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int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div_mult_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_reparent_clk_ops);
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}
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#ifdef CONFIG_SH_CLK_CPG_LEGACY
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static struct clk master_clk = {
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.name = "master_clk",
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@ -117,12 +117,11 @@ static struct clk_div_mult_table div4_table = {
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.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
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DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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@ -130,9 +129,19 @@ struct clk div4_clks[DIV4_NR] = {
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
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};
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enum { DIV4_IRDA, DIV4_ENABLE_NR };
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struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
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[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
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};
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enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
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struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
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[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
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};
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struct clk div6_clks[] = {
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@ -188,6 +197,14 @@ int __init arch_clk_init(void)
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_enable_register(div4_enable_clks,
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DIV4_ENABLE_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_reparent_register(div4_reparent_clks,
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DIV4_REPARENT_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
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