RDMA/ocrdma: Query and initalize the PFC SL
This patch implements routine to query the PFC priority from the adapter port. Following are the changes implemented: * A new FW command is implemented to query the operational/admin DCBX configuration from the FW and obtain active priority(service level). * Adds support for the async event reported by FW when the PFC priority changes. Service level is re-initialized during modify_qp or create_ah, based on this event. * Maintain SL value in ocrdma_dev structure and refer that as and when needed. Signed-off-by: Devesh Sharma <devesh.sharma@emulex.com> Signed-off-by: Selvin Xavier <selvin.xavier@emulex.com> Signed-off-by: Roland Dreier <roland@purestorage.com>hifive-unleashed-5.1
Selvin Xavier
Roland Dreier
parent
f50f31e42f
commit
31dbdd9af5
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@ -236,6 +236,9 @@ struct ocrdma_dev {
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struct rcu_head rcu;
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int id;
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u64 stag_arr[OCRDMA_MAX_STAG];
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u8 sl; /* service level */
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bool pfc_state;
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atomic_t update_sl;
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u16 pvid;
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u32 asic_id;
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@ -518,4 +521,22 @@ static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
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OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
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}
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static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
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{
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return *(pfc + prio);
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}
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static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
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{
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return *(app_prio + prio);
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}
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static inline u8 ocrdma_is_enabled_and_synced(u32 state)
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{ /* May also be used to interpret TC-state, QCN-state
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* Appl-state and Logical-link-state in future.
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*/
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return (state & OCRDMA_STATE_FLAG_ENABLED) &&
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(state & OCRDMA_STATE_FLAG_SYNC);
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}
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#endif
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@ -100,6 +100,8 @@ struct ib_ah *ocrdma_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr)
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if (!(attr->ah_flags & IB_AH_GRH))
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return ERR_PTR(-EINVAL);
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if (atomic_cmpxchg(&dev->update_sl, 1, 0))
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ocrdma_init_service_level(dev);
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ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
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if (!ah)
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return ERR_PTR(-ENOMEM);
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@ -771,6 +771,10 @@ static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
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OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
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OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
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break;
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case OCRDMA_ASYNC_EVENT_COS_VALUE:
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atomic_set(&dev->update_sl, 1);
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break;
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default:
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/* Not interested evts. */
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break;
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@ -2265,6 +2269,8 @@ static int ocrdma_set_av_params(struct ocrdma_qp *qp,
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if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
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return -EINVAL;
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if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
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ocrdma_init_service_level(qp->dev);
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cmd->params.tclass_sq_psn |=
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(ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
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cmd->params.rnt_rc_sl_fl |=
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@ -2298,6 +2304,10 @@ static int ocrdma_set_av_params(struct ocrdma_qp *qp,
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cmd->params.vlan_dmac_b4_to_b5 |=
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vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
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cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
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/* override the sl with default priority if 0 */
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cmd->params.rnt_rc_sl_fl |=
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(ah_attr->sl ? ah_attr->sl :
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qp->dev->sl) << OCRDMA_QP_PARAMS_SL_SHIFT;
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}
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return 0;
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}
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@ -2605,6 +2615,168 @@ int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
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return status;
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}
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static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
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struct ocrdma_dcbx_cfg *dcbxcfg)
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{
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int status = 0;
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dma_addr_t pa;
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struct ocrdma_mqe cmd;
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struct ocrdma_get_dcbx_cfg_req *req = NULL;
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struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
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struct pci_dev *pdev = dev->nic_info.pdev;
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struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
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memset(&cmd, 0, sizeof(struct ocrdma_mqe));
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cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
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sizeof(struct ocrdma_get_dcbx_cfg_req));
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req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
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if (!req) {
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status = -ENOMEM;
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goto mem_err;
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}
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cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
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OCRDMA_MQE_HDR_SGE_CNT_MASK;
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mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
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mqe_sge->pa_hi = (u32) upper_32_bits(pa);
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mqe_sge->len = cmd.hdr.pyld_len;
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memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
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ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
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OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
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req->param_type = ptype;
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status = ocrdma_mbx_cmd(dev, &cmd);
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if (status)
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goto mbx_err;
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rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
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ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
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memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
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mbx_err:
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dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
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mem_err:
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return status;
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}
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#define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
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#define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
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static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
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struct ocrdma_dcbx_cfg *dcbxcfg,
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u8 *srvc_lvl)
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{
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int status = -EINVAL, indx, slindx;
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int ventry_cnt;
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struct ocrdma_app_parameter *app_param;
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u8 valid, proto_sel;
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u8 app_prio, pfc_prio;
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u16 proto;
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if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
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pr_info("%s ocrdma%d DCBX is disabled\n",
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dev_name(&dev->nic_info.pdev->dev), dev->id);
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goto out;
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}
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if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
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pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
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dev_name(&dev->nic_info.pdev->dev), dev->id,
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(ptype > 0 ? "operational" : "admin"),
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(dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
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"enabled" : "disabled",
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(dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
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"" : ", not sync'ed");
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goto out;
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} else {
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pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
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dev_name(&dev->nic_info.pdev->dev), dev->id);
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}
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ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
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OCRDMA_DCBX_APP_ENTRY_SHIFT)
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& OCRDMA_DCBX_STATE_MASK;
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for (indx = 0; indx < ventry_cnt; indx++) {
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app_param = &dcbxcfg->app_param[indx];
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valid = (app_param->valid_proto_app >>
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OCRDMA_APP_PARAM_VALID_SHIFT)
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& OCRDMA_APP_PARAM_VALID_MASK;
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proto_sel = (app_param->valid_proto_app
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>> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
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& OCRDMA_APP_PARAM_PROTO_SEL_MASK;
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proto = app_param->valid_proto_app &
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OCRDMA_APP_PARAM_APP_PROTO_MASK;
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if (
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valid && proto == OCRDMA_APP_PROTO_ROCE &&
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proto_sel == OCRDMA_PROTO_SELECT_L2) {
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for (slindx = 0; slindx <
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OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
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app_prio = ocrdma_get_app_prio(
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(u8 *)app_param->app_prio,
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slindx);
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pfc_prio = ocrdma_get_pfc_prio(
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(u8 *)dcbxcfg->pfc_prio,
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slindx);
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if (app_prio && pfc_prio) {
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*srvc_lvl = slindx;
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status = 0;
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goto out;
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}
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}
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if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
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pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
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dev_name(&dev->nic_info.pdev->dev),
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dev->id, proto);
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}
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}
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}
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out:
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return status;
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}
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void ocrdma_init_service_level(struct ocrdma_dev *dev)
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{
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int status = 0, indx;
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struct ocrdma_dcbx_cfg dcbxcfg;
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u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
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int ptype = OCRDMA_PARAMETER_TYPE_OPER;
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for (indx = 0; indx < 2; indx++) {
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status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
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if (status) {
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pr_err("%s(): status=%d\n", __func__, status);
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ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
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continue;
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}
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status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
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&dcbxcfg, &srvc_lvl);
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if (status) {
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ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
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continue;
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}
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break;
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}
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if (status)
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pr_info("%s ocrdma%d service level default\n",
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dev_name(&dev->nic_info.pdev->dev), dev->id);
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else
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pr_info("%s ocrdma%d service level %d\n",
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dev_name(&dev->nic_info.pdev->dev), dev->id,
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srvc_lvl);
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dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
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dev->sl = srvc_lvl;
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}
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int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
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{
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int i;
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@ -135,4 +135,6 @@ int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq);
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int ocrdma_mbx_rdma_stats(struct ocrdma_dev *, bool reset);
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char *port_speed_string(struct ocrdma_dev *dev);
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void ocrdma_init_service_level(struct ocrdma_dev *);
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#endif /* __OCRDMA_HW_H__ */
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@ -399,6 +399,7 @@ static struct ocrdma_dev *ocrdma_add(struct be_dev_info *dev_info)
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if (status)
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goto alloc_err;
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ocrdma_init_service_level(dev);
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status = ocrdma_register_device(dev);
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if (status)
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goto alloc_err;
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@ -422,7 +422,12 @@ struct ocrdma_ae_qp_mcqe {
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#define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
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#define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
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#define OCRDMA_ASYNC_EVENT_PVID_STATE 0x3
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enum ocrdma_async_grp5_events {
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OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01,
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OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02,
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OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03
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};
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enum OCRDMA_ASYNC_EVENT_TYPE {
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OCRDMA_CQ_ERROR = 0x00,
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@ -1949,5 +1954,79 @@ struct ocrdma_get_ctrl_attribs_rsp {
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struct mgmt_controller_attrib ctrl_attribs;
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};
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#define OCRDMA_SUBSYS_DCBX 0x10
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enum OCRDMA_DCBX_OPCODE {
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OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
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};
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enum OCRDMA_DCBX_PARAM_TYPE {
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OCRDMA_PARAMETER_TYPE_ADMIN = 0x00,
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OCRDMA_PARAMETER_TYPE_OPER = 0x01,
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OCRDMA_PARAMETER_TYPE_PEER = 0x02
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};
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enum OCRDMA_DCBX_APP_PROTO {
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OCRDMA_APP_PROTO_ROCE = 0x8915
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};
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enum OCRDMA_DCBX_PROTO {
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OCRDMA_PROTO_SELECT_L2 = 0x00,
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OCRDMA_PROTO_SELECT_L4 = 0x01
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};
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enum OCRDMA_DCBX_APP_PARAM {
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OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
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OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
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OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
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OCRDMA_APP_PARAM_VALID_MASK = 0xFF,
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OCRDMA_APP_PARAM_VALID_SHIFT = 0x18
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};
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enum OCRDMA_DCBX_STATE_FLAGS {
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OCRDMA_STATE_FLAG_ENABLED = 0x01,
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OCRDMA_STATE_FLAG_ADDVERTISED = 0x02,
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OCRDMA_STATE_FLAG_WILLING = 0x04,
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OCRDMA_STATE_FLAG_SYNC = 0x08,
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OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000,
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OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000
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};
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enum OCRDMA_TCV_AEV_OPV_ST {
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OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF,
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OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18,
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OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10,
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OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08,
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OCRDMA_DCBX_STATE_MASK = 0xFF
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};
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struct ocrdma_app_parameter {
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u32 valid_proto_app;
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u32 oui;
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u32 app_prio[2];
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};
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struct ocrdma_dcbx_cfg {
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u32 tcv_aev_opv_st;
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u32 tc_state;
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u32 pfc_state;
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u32 qcn_state;
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u32 appl_state;
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u32 ll_state;
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u32 tc_bw[2];
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u32 tc_prio[8];
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u32 pfc_prio[2];
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struct ocrdma_app_parameter app_param[15];
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};
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struct ocrdma_get_dcbx_cfg_req {
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struct ocrdma_mbx_hdr hdr;
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u32 param_type;
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} __packed;
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struct ocrdma_get_dcbx_cfg_rsp {
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struct ocrdma_mbx_rsp hdr;
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struct ocrdma_dcbx_cfg cfg;
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} __packed;
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#endif /* __OCRDMA_SLI_H__ */
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