clocksource: sh_cmt: Drop support for legacy platform data
Now that all platforms have switched to the new-style platform data, drop support for the legacy version. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Simon Horman <horms+renesas@verge.net.au>hifive-unleashed-5.1
parent
4c834452aa
commit
31e912f598
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@ -114,9 +114,7 @@ struct sh_cmt_device {
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struct platform_device *pdev;
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struct platform_device *pdev;
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const struct sh_cmt_info *info;
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const struct sh_cmt_info *info;
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bool legacy;
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void __iomem *mapbase_ch;
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void __iomem *mapbase;
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void __iomem *mapbase;
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struct clk *clk;
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struct clk *clk;
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@ -792,7 +790,7 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
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int irq;
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int irq;
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int ret;
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int ret;
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irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index);
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irq = platform_get_irq(ch->cmt->pdev, ch->index);
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if (irq < 0) {
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if (irq < 0) {
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dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
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dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
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ch->index);
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ch->index);
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@ -863,33 +861,26 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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* Compute the address of the channel control register block. For the
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* Compute the address of the channel control register block. For the
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* timers with a per-channel start/stop register, compute its address
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* timers with a per-channel start/stop register, compute its address
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* as well.
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* as well.
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*
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* For legacy configuration the address has been mapped explicitly.
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*/
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*/
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if (cmt->legacy) {
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switch (cmt->info->model) {
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ch->ioctrl = cmt->mapbase_ch;
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case SH_CMT_16BIT:
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} else {
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ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
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switch (cmt->info->model) {
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break;
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case SH_CMT_16BIT:
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case SH_CMT_32BIT:
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ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
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case SH_CMT_48BIT:
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break;
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ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
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case SH_CMT_32BIT:
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break;
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case SH_CMT_48BIT:
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case SH_CMT_32BIT_FAST:
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ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
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/*
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break;
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* The 32-bit "fast" timer has a single channel at hwidx 5 but
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case SH_CMT_32BIT_FAST:
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* is located at offset 0x40 instead of 0x60 for some reason.
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/*
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*/
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* The 32-bit "fast" timer has a single channel at hwidx
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ch->ioctrl = cmt->mapbase + 0x40;
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* 5 but is located at offset 0x40 instead of 0x60 for
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break;
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* some reason.
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case SH_CMT_48BIT_GEN2:
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*/
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ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
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ch->ioctrl = cmt->mapbase + 0x40;
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ch->ioctrl = ch->iostart + 0x10;
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break;
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break;
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case SH_CMT_48BIT_GEN2:
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ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
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ch->ioctrl = ch->iostart + 0x10;
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break;
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}
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}
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}
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if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
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if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
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@ -900,12 +891,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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ch->match_value = ch->max_match_value;
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ch->match_value = ch->max_match_value;
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raw_spin_lock_init(&ch->lock);
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raw_spin_lock_init(&ch->lock);
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if (cmt->legacy) {
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ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
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ch->timer_bit = ch->hwidx;
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} else {
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ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2
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? 0 : ch->hwidx;
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}
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ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
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ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
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clockevent, clocksource);
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clockevent, clocksource);
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@ -938,60 +924,12 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
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return 0;
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return 0;
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}
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}
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static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt)
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{
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struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
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struct resource *res, *res2;
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/* map memory, let mapbase_ch point to our channel */
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res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
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return -ENXIO;
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}
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cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res));
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if (cmt->mapbase_ch == NULL) {
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dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
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return -ENXIO;
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}
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/* optional resource for the shared timer start/stop register */
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res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
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/* map second resource for CMSTR */
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cmt->mapbase = ioremap_nocache(res2 ? res2->start :
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res->start - cfg->channel_offset,
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res2 ? resource_size(res2) : 2);
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if (cmt->mapbase == NULL) {
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dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
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iounmap(cmt->mapbase_ch);
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return -ENXIO;
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}
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/* identify the model based on the resources */
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if (resource_size(res) == 6)
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cmt->info = &sh_cmt_info[SH_CMT_16BIT];
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else if (res2 && (resource_size(res2) == 4))
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cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
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else
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cmt->info = &sh_cmt_info[SH_CMT_32BIT];
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return 0;
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}
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static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt)
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{
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iounmap(cmt->mapbase);
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if (cmt->mapbase_ch)
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iounmap(cmt->mapbase_ch);
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}
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static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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{
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{
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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const struct platform_device_id *id = pdev->id_entry;
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const struct platform_device_id *id = pdev->id_entry;
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unsigned int hw_channels;
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unsigned int mask;
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unsigned int i;
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int ret;
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int ret;
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memset(cmt, 0, sizeof(*cmt));
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memset(cmt, 0, sizeof(*cmt));
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@ -1003,10 +941,9 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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}
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}
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cmt->info = (const struct sh_cmt_info *)id->driver_data;
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cmt->info = (const struct sh_cmt_info *)id->driver_data;
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cmt->legacy = cmt->info ? false : true;
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/* Get hold of clock. */
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/* Get hold of clock. */
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cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck");
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cmt->clk = clk_get(&cmt->pdev->dev, "fck");
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if (IS_ERR(cmt->clk)) {
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if (IS_ERR(cmt->clk)) {
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dev_err(&cmt->pdev->dev, "cannot get clock\n");
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dev_err(&cmt->pdev->dev, "cannot get clock\n");
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return PTR_ERR(cmt->clk);
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return PTR_ERR(cmt->clk);
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@ -1016,27 +953,13 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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if (ret < 0)
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if (ret < 0)
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goto err_clk_put;
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goto err_clk_put;
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/*
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/* Map the memory resource(s). */
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* Map the memory resource(s). We need to support both the legacy
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ret = sh_cmt_map_memory(cmt);
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* platform device configuration (with one device per channel) and the
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* new version (with multiple channels per device).
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*/
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if (cmt->legacy)
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ret = sh_cmt_map_memory_legacy(cmt);
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else
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ret = sh_cmt_map_memory(cmt);
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if (ret < 0)
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if (ret < 0)
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goto err_clk_unprepare;
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goto err_clk_unprepare;
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/* Allocate and setup the channels. */
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/* Allocate and setup the channels. */
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if (cmt->legacy) {
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cmt->num_channels = hweight8(cfg->channels_mask);
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cmt->num_channels = 1;
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hw_channels = 0;
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} else {
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cmt->num_channels = hweight8(cfg->channels_mask);
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hw_channels = cfg->channels_mask;
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}
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cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
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cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
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GFP_KERNEL);
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GFP_KERNEL);
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@ -1045,35 +968,21 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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goto err_unmap;
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goto err_unmap;
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}
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}
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if (cmt->legacy) {
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/*
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ret = sh_cmt_setup_channel(&cmt->channels[0],
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* Use the first channel as a clock event device and the second channel
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cfg->timer_bit, cfg->timer_bit,
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* as a clock source. If only one channel is available use it for both.
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cfg->clockevent_rating != 0,
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*/
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cfg->clocksource_rating != 0, cmt);
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for (i = 0, mask = cfg->channels_mask; i < cmt->num_channels; ++i) {
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unsigned int hwidx = ffs(mask) - 1;
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bool clocksource = i == 1 || cmt->num_channels == 1;
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bool clockevent = i == 0;
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ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
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clockevent, clocksource, cmt);
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if (ret < 0)
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if (ret < 0)
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goto err_unmap;
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goto err_unmap;
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} else {
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unsigned int mask = hw_channels;
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unsigned int i;
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/*
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mask &= ~(1 << hwidx);
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* Use the first channel as a clock event device and the second
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* channel as a clock source. If only one channel is available
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* use it for both.
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*/
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for (i = 0; i < cmt->num_channels; ++i) {
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unsigned int hwidx = ffs(mask) - 1;
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bool clocksource = i == 1 || cmt->num_channels == 1;
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bool clockevent = i == 0;
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ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
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clockevent, clocksource,
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cmt);
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if (ret < 0)
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goto err_unmap;
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mask &= ~(1 << hwidx);
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}
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}
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}
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platform_set_drvdata(pdev, cmt);
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platform_set_drvdata(pdev, cmt);
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@ -1082,7 +991,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
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err_unmap:
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err_unmap:
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kfree(cmt->channels);
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kfree(cmt->channels);
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sh_cmt_unmap_memory(cmt);
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iounmap(cmt->mapbase);
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err_clk_unprepare:
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err_clk_unprepare:
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clk_unprepare(cmt->clk);
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clk_unprepare(cmt->clk);
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err_clk_put:
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err_clk_put:
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@ -1133,7 +1042,6 @@ static int sh_cmt_remove(struct platform_device *pdev)
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}
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}
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static const struct platform_device_id sh_cmt_id_table[] = {
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static const struct platform_device_id sh_cmt_id_table[] = {
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{ "sh_cmt", 0 },
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{ "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
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{ "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
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{ "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
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{ "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
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{ "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
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{ "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
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