Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge because: - Maarten needs latest atomic patches from drm-misc. - Lionel needs the color manager core patch from drm-misc. - Ander extracted intel_dpll_mgr.c, we need a backmerge to avoid git losing track of things too often (right now it seems ok due to cherry-picks). - Tvrtko needs a stable baseline to apply some large-scale renaming patches to i915 GEM code. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
commit
31fa684096
|
@ -229,6 +229,7 @@ X!Isound/sound_firmware.c
|
|||
!Iinclude/media/v4l2-dv-timings.h
|
||||
!Iinclude/media/v4l2-event.h
|
||||
!Iinclude/media/v4l2-flash-led-class.h
|
||||
!Iinclude/media/v4l2-mc.h
|
||||
!Iinclude/media/v4l2-mediabus.h
|
||||
!Iinclude/media/v4l2-mem2mem.h
|
||||
!Iinclude/media/v4l2-of.h
|
||||
|
|
|
@ -1816,7 +1816,7 @@ void intel_crt_init(struct drm_device *dev)
|
|||
<td valign="top" >Description/Restrictions</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td rowspan="37" valign="top" >DRM</td>
|
||||
<td rowspan="42" valign="top" >DRM</td>
|
||||
<td valign="top" >Generic</td>
|
||||
<td valign="top" >“rotation”</td>
|
||||
<td valign="top" >BITMASK</td>
|
||||
|
@ -2068,7 +2068,7 @@ void intel_crt_init(struct drm_device *dev)
|
|||
<td valign="top" >property to suggest an Y offset for a connector</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td rowspan="3" valign="top" >Optional</td>
|
||||
<td rowspan="8" valign="top" >Optional</td>
|
||||
<td valign="top" >“scaling mode”</td>
|
||||
<td valign="top" >ENUM</td>
|
||||
<td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td>
|
||||
|
@ -2092,6 +2092,61 @@ void intel_crt_init(struct drm_device *dev)
|
|||
<td valign="top" >TBD</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top" >“DEGAMMA_LUT”</td>
|
||||
<td valign="top" >BLOB</td>
|
||||
<td valign="top" >0</td>
|
||||
<td valign="top" >CRTC</td>
|
||||
<td valign="top" >DRM property to set the degamma lookup table
|
||||
(LUT) mapping pixel data from the framebuffer before it is
|
||||
given to the transformation matrix. The data is an interpreted
|
||||
as an array of struct drm_color_lut elements. Hardware might
|
||||
choose not to use the full precision of the LUT elements nor
|
||||
use all the elements of the LUT (for example the hardware
|
||||
might choose to interpolate between LUT[0] and LUT[4]). </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top" >“DEGAMMA_LUT_SIZE”</td>
|
||||
<td valign="top" >RANGE | IMMUTABLE</td>
|
||||
<td valign="top" >Min=0, Max=UINT_MAX</td>
|
||||
<td valign="top" >CRTC</td>
|
||||
<td valign="top" >DRM property to gives the size of the lookup
|
||||
table to be set on the DEGAMMA_LUT property (the size depends
|
||||
on the underlying hardware).</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top" >“CTM”</td>
|
||||
<td valign="top" >BLOB</td>
|
||||
<td valign="top" >0</td>
|
||||
<td valign="top" >CRTC</td>
|
||||
<td valign="top" >DRM property to set the current
|
||||
transformation matrix (CTM) apply to pixel data after the
|
||||
lookup through the degamma LUT and before the lookup through
|
||||
the gamma LUT. The data is an interpreted as a struct
|
||||
drm_color_ctm.</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top" >“GAMMA_LUT”</td>
|
||||
<td valign="top" >BLOB</td>
|
||||
<td valign="top" >0</td>
|
||||
<td valign="top" >CRTC</td>
|
||||
<td valign="top" >DRM property to set the gamma lookup table
|
||||
(LUT) mapping pixel data after to the transformation matrix to
|
||||
data sent to the connector. The data is an interpreted as an
|
||||
array of struct drm_color_lut elements. Hardware might choose
|
||||
not to use the full precision of the LUT elements nor use all
|
||||
the elements of the LUT (for example the hardware might choose
|
||||
to interpolate between LUT[0] and LUT[4]).</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top" >“GAMMA_LUT_SIZE”</td>
|
||||
<td valign="top" >RANGE | IMMUTABLE</td>
|
||||
<td valign="top" >Min=0, Max=UINT_MAX</td>
|
||||
<td valign="top" >CRTC</td>
|
||||
<td valign="top" >DRM property to gives the size of the lookup
|
||||
table to be set on the GAMMA_LUT property (the size depends on
|
||||
the underlying hardware).</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td rowspan="20" valign="top" >i915</td>
|
||||
<td rowspan="2" valign="top" >Generic</td>
|
||||
<td valign="top" >"Broadcast RGB"</td>
|
||||
|
|
|
@ -2329,6 +2329,14 @@ to search and match for the present Macroblock (MB) in the reference picture. Th
|
|||
vertical search range for motion estimation module in video encoder.</entry>
|
||||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row id="v4l2-mpeg-video-force-key-frame">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME</constant> </entry>
|
||||
<entry>button</entry>
|
||||
</row><row><entry spanname="descr">Force a key frame for the next queued buffer. Applicable to encoders.
|
||||
This is a general, codec-agnostic keyframe control.</entry>
|
||||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant> </entry>
|
||||
|
@ -5069,6 +5077,46 @@ interface and may change in the future.</para>
|
|||
This control is applicable to VGA, DVI-A/D, HDMI and DisplayPort connectors.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_DV_TX_IT_CONTENT_TYPE</constant></entry>
|
||||
<entry id="v4l2-dv-content-type">enum v4l2_dv_it_content_type</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Configures the IT Content Type
|
||||
of the transmitted video. This information is sent over HDMI and DisplayPort connectors
|
||||
as part of the AVI InfoFrame. The term 'IT Content' is used for content that originates
|
||||
from a computer as opposed to content from a TV broadcast or an analog source. The
|
||||
enum v4l2_dv_it_content_type defines the possible content types:</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entrytbl spanname="descr" cols="2">
|
||||
<tbody valign="top">
|
||||
<row>
|
||||
<entry><constant>V4L2_DV_IT_CONTENT_TYPE_GRAPHICS</constant> </entry>
|
||||
<entry>Graphics content. Pixel data should be passed unfiltered and without
|
||||
analog reconstruction.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>V4L2_DV_IT_CONTENT_TYPE_PHOTO</constant> </entry>
|
||||
<entry>Photo content. The content is derived from digital still pictures.
|
||||
The content should be passed through with minimal scaling and picture
|
||||
enhancements.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>V4L2_DV_IT_CONTENT_TYPE_CINEMA</constant> </entry>
|
||||
<entry>Cinema content.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>V4L2_DV_IT_CONTENT_TYPE_GAME</constant> </entry>
|
||||
<entry>Game content. Audio and video latency should be minimized.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>V4L2_DV_IT_CONTENT_TYPE_NO_ITC</constant> </entry>
|
||||
<entry>No IT Content information is available and the ITC bit in the AVI
|
||||
InfoFrame is set to 0.</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</entrytbl>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_DV_RX_POWER_PRESENT</constant></entry>
|
||||
<entry>bitmask</entry>
|
||||
|
@ -5098,6 +5146,16 @@ interface and may change in the future.</para>
|
|||
This control is applicable to VGA, DVI-A/D, HDMI and DisplayPort connectors.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry spanname="id"><constant>V4L2_CID_DV_RX_IT_CONTENT_TYPE</constant></entry>
|
||||
<entry>enum v4l2_dv_it_content_type</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Reads the IT Content Type
|
||||
of the received video. This information is sent over HDMI and DisplayPort connectors
|
||||
as part of the AVI InfoFrame. The term 'IT Content' is used for content that originates
|
||||
from a computer as opposed to content from a TV broadcast or an analog source. See
|
||||
<constant>V4L2_CID_DV_TX_IT_CONTENT_TYPE</constant> for the available content types.</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
|
|
|
@ -48,9 +48,6 @@
|
|||
|
||||
<refsect1>
|
||||
<title>Description</title>
|
||||
|
||||
<para><emphasis role="bold">NOTE:</emphasis> This new ioctl is programmed to be added on Kernel 4.6. Its definition/arguments may change until its final version.</para>
|
||||
|
||||
<para>The typical usage of this ioctl is to call it twice.
|
||||
On the first call, the structure defined at &media-v2-topology; should
|
||||
be zeroed. At return, if no errors happen, this ioctl will return the
|
||||
|
|
|
@ -56,10 +56,6 @@
|
|||
<entry><constant>MEDIA_ENT_F_CONN_COMPOSITE</constant></entry>
|
||||
<entry>Connector for a RGB composite signal.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>MEDIA_ENT_F_CONN_TEST</constant></entry>
|
||||
<entry>Connector for a test generator.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>MEDIA_ENT_F_CAM_SENSOR</constant></entry>
|
||||
<entry>Camera video sensor entity.</entry>
|
||||
|
@ -84,7 +80,34 @@
|
|||
</row>
|
||||
<row>
|
||||
<entry><constant>MEDIA_ENT_F_TUNER</constant></entry>
|
||||
<entry>Digital TV, analog TV, radio and/or software radio tuner.</entry>
|
||||
<entry>Digital TV, analog TV, radio and/or software radio tuner,
|
||||
with consists on a PLL tuning stage that converts radio
|
||||
frequency (RF) signal into an Intermediate Frequency (IF).
|
||||
Modern tuners have internally IF-PLL decoders for audio
|
||||
and video, but older models have those stages implemented
|
||||
on separate entities.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>MEDIA_ENT_F_IF_VID_DECODER</constant></entry>
|
||||
<entry>IF-PLL video decoder. It receives the IF from a PLL
|
||||
and decodes the analog TV video signal. This is commonly
|
||||
found on some very old analog tuners, like Philips MK3
|
||||
designs. They all contain a tda9887 (or some software
|
||||
compatible similar chip, like tda9885). Those devices
|
||||
use a different I2C address than the tuner PLL.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry><constant>MEDIA_ENT_F_IF_AUD_DECODER</constant></entry>
|
||||
<entry>IF-PLL sound decoder. It receives the IF from a PLL
|
||||
and decodes the analog TV audio signal. This is commonly
|
||||
found on some very old analog hardware, like Micronas
|
||||
msp3400, Philips tda9840, tda985x, etc. Those devices
|
||||
use a different I2C address than the tuner PLL and
|
||||
should be controlled together with the IF-PLL video
|
||||
decoder.
|
||||
</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
|
|
|
@ -1,35 +1,43 @@
|
|||
<refentry id="V4L2-PIX-FMT-YUV420M">
|
||||
<refentry>
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YM12')</refentrytitle>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YM12'), V4L2_PIX_FMT_YVU420M ('YM21')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
<refname> <constant>V4L2_PIX_FMT_YUV420M</constant></refname>
|
||||
<refpurpose>Variation of <constant>V4L2_PIX_FMT_YUV420</constant>
|
||||
with planes non contiguous in memory. </refpurpose>
|
||||
<refname id="V4L2-PIX-FMT-YUV420M"><constant>V4L2_PIX_FMT_YUV420M</constant></refname>
|
||||
<refname id="V4L2-PIX-FMT-YVU420M"><constant>V4L2_PIX_FMT_YVU420M</constant></refname>
|
||||
<refpurpose>Variation of <constant>V4L2_PIX_FMT_YUV420</constant> and
|
||||
<constant>V4L2_PIX_FMT_YVU420</constant> with planes non contiguous
|
||||
in memory.</refpurpose>
|
||||
</refnamediv>
|
||||
|
||||
<refsect1>
|
||||
<title>Description</title>
|
||||
|
||||
<para>This is a multi-planar format, as opposed to a packed format.
|
||||
The three components are separated into three sub- images or planes.
|
||||
The three components are separated into three sub-images or planes.</para>
|
||||
|
||||
The Y plane is first. The Y plane has one byte per pixel. The Cb data
|
||||
<para>The Y plane is first. The Y plane has one byte per pixel.
|
||||
For <constant>V4L2_PIX_FMT_YUV420M</constant> the Cb data
|
||||
constitutes the second plane which is half the width and half
|
||||
the height of the Y plane (and of the image). Each Cb belongs to four
|
||||
pixels, a two-by-two square of the image. For example,
|
||||
Cb<subscript>0</subscript> belongs to Y'<subscript>00</subscript>,
|
||||
Y'<subscript>01</subscript>, Y'<subscript>10</subscript>, and
|
||||
Y'<subscript>11</subscript>. The Cr data, just like the Cb plane, is
|
||||
in the third plane. </para>
|
||||
in the third plane.</para>
|
||||
|
||||
<para><constant>V4L2_PIX_FMT_YVU420M</constant> is the same except
|
||||
the Cr data is stored in the second plane and the Cb data in the third plane.
|
||||
</para>
|
||||
|
||||
<para>If the Y plane has pad bytes after each row, then the Cb
|
||||
and Cr planes have half as many pad bytes after their rows. In other
|
||||
words, two Cx rows (including padding) is exactly as long as one Y row
|
||||
(including padding).</para>
|
||||
|
||||
<para><constant>V4L2_PIX_FMT_YUV420M</constant> is intended to be
|
||||
<para><constant>V4L2_PIX_FMT_YUV420M</constant> and
|
||||
<constant>V4L2_PIX_FMT_YVU420M</constant> are intended to be
|
||||
used only in drivers and applications that support the multi-planar API,
|
||||
described in <xref linkend="planar-apis"/>. </para>
|
||||
|
||||
|
|
|
@ -1,40 +1,45 @@
|
|||
<refentry id="V4L2-PIX-FMT-YVU420M">
|
||||
<refentry>
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_YVU420M ('YM21')</refentrytitle>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV422M ('YM16'), V4L2_PIX_FMT_YVU422M ('YM61')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
<refname> <constant>V4L2_PIX_FMT_YVU420M</constant></refname>
|
||||
<refpurpose>Variation of <constant>V4L2_PIX_FMT_YVU420</constant>
|
||||
with planes non contiguous in memory. </refpurpose>
|
||||
<refname id="V4L2-PIX-FMT-YUV422M"><constant>V4L2_PIX_FMT_YUV422M</constant></refname>
|
||||
<refname id="V4L2-PIX-FMT-YVU422M"><constant>V4L2_PIX_FMT_YVU422M</constant></refname>
|
||||
<refpurpose>Planar formats with ½ horizontal resolution, also
|
||||
known as YUV and YVU 4:2:2</refpurpose>
|
||||
</refnamediv>
|
||||
|
||||
<refsect1>
|
||||
<title>Description</title>
|
||||
|
||||
<para>This is a multi-planar format, as opposed to a packed format.
|
||||
The three components are separated into three sub-images or planes.
|
||||
The three components are separated into three sub-images or planes.</para>
|
||||
|
||||
The Y plane is first. The Y plane has one byte per pixel. The Cr data
|
||||
constitutes the second plane which is half the width and half
|
||||
the height of the Y plane (and of the image). Each Cr belongs to four
|
||||
pixels, a two-by-two square of the image. For example,
|
||||
Cr<subscript>0</subscript> belongs to Y'<subscript>00</subscript>,
|
||||
Y'<subscript>01</subscript>, Y'<subscript>10</subscript>, and
|
||||
Y'<subscript>11</subscript>. The Cb data, just like the Cr plane, constitutes
|
||||
the third plane. </para>
|
||||
<para>The Y plane is first. The Y plane has one byte per pixel.
|
||||
For <constant>V4L2_PIX_FMT_YUV422M</constant> the Cb data
|
||||
constitutes the second plane which is half the width of the Y plane (and of the
|
||||
image). Each Cb belongs to two pixels. For example,
|
||||
Cb<subscript>0</subscript> belongs to Y'<subscript>00</subscript>,
|
||||
Y'<subscript>01</subscript>. The Cr data, just like the Cb plane, is
|
||||
in the third plane. </para>
|
||||
|
||||
<para>If the Y plane has pad bytes after each row, then the Cr
|
||||
and Cb planes have half as many pad bytes after their rows. In other
|
||||
<para><constant>V4L2_PIX_FMT_YVU422M</constant> is the same except
|
||||
the Cr data is stored in the second plane and the Cb data in the third plane.
|
||||
</para>
|
||||
|
||||
<para>If the Y plane has pad bytes after each row, then the Cb
|
||||
and Cr planes have half as many pad bytes after their rows. In other
|
||||
words, two Cx rows (including padding) is exactly as long as one Y row
|
||||
(including padding).</para>
|
||||
|
||||
<para><constant>V4L2_PIX_FMT_YVU420M</constant> is intended to be
|
||||
<para><constant>V4L2_PIX_FMT_YUV422M</constant> and
|
||||
<constant>V4L2_PIX_FMT_YVU422M</constant> are intended to be
|
||||
used only in drivers and applications that support the multi-planar API,
|
||||
described in <xref linkend="planar-apis"/>. </para>
|
||||
|
||||
<example>
|
||||
<title><constant>V4L2_PIX_FMT_YVU420M</constant> 4 × 4
|
||||
<title><constant>V4L2_PIX_FMT_YUV422M</constant> 4 × 4
|
||||
pixel image</title>
|
||||
|
||||
<formalpara>
|
||||
|
@ -75,25 +80,45 @@ pixel image</title>
|
|||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry>start1 + 0:</entry>
|
||||
<entry>Cr<subscript>00</subscript></entry>
|
||||
<entry>Cr<subscript>01</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 2:</entry>
|
||||
<entry>Cr<subscript>10</subscript></entry>
|
||||
<entry>Cr<subscript>11</subscript></entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry>start2 + 0:</entry>
|
||||
<entry>Cb<subscript>00</subscript></entry>
|
||||
<entry>Cb<subscript>01</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 2:</entry>
|
||||
<entry>start1 + 2:</entry>
|
||||
<entry>Cb<subscript>10</subscript></entry>
|
||||
<entry>Cb<subscript>11</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 4:</entry>
|
||||
<entry>Cb<subscript>20</subscript></entry>
|
||||
<entry>Cb<subscript>21</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 6:</entry>
|
||||
<entry>Cb<subscript>30</subscript></entry>
|
||||
<entry>Cb<subscript>31</subscript></entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry>start2 + 0:</entry>
|
||||
<entry>Cr<subscript>00</subscript></entry>
|
||||
<entry>Cr<subscript>01</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 2:</entry>
|
||||
<entry>Cr<subscript>10</subscript></entry>
|
||||
<entry>Cr<subscript>11</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 4:</entry>
|
||||
<entry>Cr<subscript>20</subscript></entry>
|
||||
<entry>Cr<subscript>21</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 6:</entry>
|
||||
<entry>Cr<subscript>30</subscript></entry>
|
||||
<entry>Cr<subscript>31</subscript></entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</informaltable>
|
||||
|
@ -113,36 +138,23 @@ pixel image</title>
|
|||
</row>
|
||||
<row>
|
||||
<entry>0</entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry></entry><entry>C</entry><entry></entry><entry></entry>
|
||||
<entry></entry><entry>C</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>1</entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>2</entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry></entry><entry>C</entry><entry></entry><entry></entry>
|
||||
<entry></entry><entry>C</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>3</entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry></entry><entry>Y</entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry><entry></entry>
|
||||
<entry>Y</entry><entry>C</entry><entry>Y</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
177
Documentation/DocBook/media/v4l/pixfmt-yuv444m.xml
Normal file
177
Documentation/DocBook/media/v4l/pixfmt-yuv444m.xml
Normal file
|
@ -0,0 +1,177 @@
|
|||
<refentry>
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV444M ('YM24'), V4L2_PIX_FMT_YVU444M ('YM42')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
<refname id="V4L2-PIX-FMT-YUV444M"><constant>V4L2_PIX_FMT_YUV444M</constant></refname>
|
||||
<refname id="V4L2-PIX-FMT-YVU444M"><constant>V4L2_PIX_FMT_YVU444M</constant></refname>
|
||||
<refpurpose>Planar formats with full horizontal resolution, also
|
||||
known as YUV and YVU 4:4:4</refpurpose>
|
||||
</refnamediv>
|
||||
|
||||
<refsect1>
|
||||
<title>Description</title>
|
||||
|
||||
<para>This is a multi-planar format, as opposed to a packed format.
|
||||
The three components are separated into three sub-images or planes.</para>
|
||||
|
||||
<para>The Y plane is first. The Y plane has one byte per pixel.
|
||||
For <constant>V4L2_PIX_FMT_YUV444M</constant> the Cb data
|
||||
constitutes the second plane which is the same width and height as the Y plane
|
||||
(and as the image). The Cr data, just like the Cb plane, is in the third plane.
|
||||
</para>
|
||||
|
||||
<para><constant>V4L2_PIX_FMT_YVU444M</constant> is the same except
|
||||
the Cr data is stored in the second plane and the Cb data in the third plane.
|
||||
</para>
|
||||
<para>If the Y plane has pad bytes after each row, then the Cb
|
||||
and Cr planes have the same number of pad bytes after their rows.</para>
|
||||
|
||||
<para><constant>V4L2_PIX_FMT_YUV444M</constant> and
|
||||
<constant>V4L2_PIX_FMT_YUV444M</constant> are intended to be
|
||||
used only in drivers and applications that support the multi-planar API,
|
||||
described in <xref linkend="planar-apis"/>. </para>
|
||||
|
||||
<example>
|
||||
<title><constant>V4L2_PIX_FMT_YUV444M</constant> 4 × 4
|
||||
pixel image</title>
|
||||
|
||||
<formalpara>
|
||||
<title>Byte Order.</title>
|
||||
<para>Each cell is one byte.
|
||||
<informaltable frame="none">
|
||||
<tgroup cols="5" align="center">
|
||||
<colspec align="left" colwidth="2*" />
|
||||
<tbody valign="top">
|
||||
<row>
|
||||
<entry>start0 + 0:</entry>
|
||||
<entry>Y'<subscript>00</subscript></entry>
|
||||
<entry>Y'<subscript>01</subscript></entry>
|
||||
<entry>Y'<subscript>02</subscript></entry>
|
||||
<entry>Y'<subscript>03</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start0 + 4:</entry>
|
||||
<entry>Y'<subscript>10</subscript></entry>
|
||||
<entry>Y'<subscript>11</subscript></entry>
|
||||
<entry>Y'<subscript>12</subscript></entry>
|
||||
<entry>Y'<subscript>13</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start0 + 8:</entry>
|
||||
<entry>Y'<subscript>20</subscript></entry>
|
||||
<entry>Y'<subscript>21</subscript></entry>
|
||||
<entry>Y'<subscript>22</subscript></entry>
|
||||
<entry>Y'<subscript>23</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start0 + 12:</entry>
|
||||
<entry>Y'<subscript>30</subscript></entry>
|
||||
<entry>Y'<subscript>31</subscript></entry>
|
||||
<entry>Y'<subscript>32</subscript></entry>
|
||||
<entry>Y'<subscript>33</subscript></entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry>start1 + 0:</entry>
|
||||
<entry>Cb<subscript>00</subscript></entry>
|
||||
<entry>Cb<subscript>01</subscript></entry>
|
||||
<entry>Cb<subscript>02</subscript></entry>
|
||||
<entry>Cb<subscript>03</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 4:</entry>
|
||||
<entry>Cb<subscript>10</subscript></entry>
|
||||
<entry>Cb<subscript>11</subscript></entry>
|
||||
<entry>Cb<subscript>12</subscript></entry>
|
||||
<entry>Cb<subscript>13</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 8:</entry>
|
||||
<entry>Cb<subscript>20</subscript></entry>
|
||||
<entry>Cb<subscript>21</subscript></entry>
|
||||
<entry>Cb<subscript>22</subscript></entry>
|
||||
<entry>Cb<subscript>23</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start1 + 12:</entry>
|
||||
<entry>Cb<subscript>20</subscript></entry>
|
||||
<entry>Cb<subscript>21</subscript></entry>
|
||||
<entry>Cb<subscript>32</subscript></entry>
|
||||
<entry>Cb<subscript>33</subscript></entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<entry>start2 + 0:</entry>
|
||||
<entry>Cr<subscript>00</subscript></entry>
|
||||
<entry>Cr<subscript>01</subscript></entry>
|
||||
<entry>Cr<subscript>02</subscript></entry>
|
||||
<entry>Cr<subscript>03</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 4:</entry>
|
||||
<entry>Cr<subscript>10</subscript></entry>
|
||||
<entry>Cr<subscript>11</subscript></entry>
|
||||
<entry>Cr<subscript>12</subscript></entry>
|
||||
<entry>Cr<subscript>13</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 8:</entry>
|
||||
<entry>Cr<subscript>20</subscript></entry>
|
||||
<entry>Cr<subscript>21</subscript></entry>
|
||||
<entry>Cr<subscript>22</subscript></entry>
|
||||
<entry>Cr<subscript>23</subscript></entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>start2 + 12:</entry>
|
||||
<entry>Cr<subscript>30</subscript></entry>
|
||||
<entry>Cr<subscript>31</subscript></entry>
|
||||
<entry>Cr<subscript>32</subscript></entry>
|
||||
<entry>Cr<subscript>33</subscript></entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</informaltable>
|
||||
</para>
|
||||
</formalpara>
|
||||
|
||||
<formalpara>
|
||||
<title>Color Sample Location.</title>
|
||||
<para>
|
||||
<informaltable frame="none">
|
||||
<tgroup cols="7" align="center">
|
||||
<tbody valign="top">
|
||||
<row>
|
||||
<entry></entry>
|
||||
<entry>0</entry><entry></entry><entry>1</entry><entry></entry>
|
||||
<entry>2</entry><entry></entry><entry>3</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>0</entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry><entry></entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>1</entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry><entry></entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>2</entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry><entry></entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>3</entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry><entry></entry>
|
||||
<entry>YC</entry><entry></entry><entry>YC</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</informaltable>
|
||||
</para>
|
||||
</formalpara>
|
||||
</example>
|
||||
</refsect1>
|
||||
</refentry>
|
|
@ -1628,7 +1628,8 @@ information.</para>
|
|||
&sub-y41p;
|
||||
&sub-yuv420;
|
||||
&sub-yuv420m;
|
||||
&sub-yvu420m;
|
||||
&sub-yuv422m;
|
||||
&sub-yuv444m;
|
||||
&sub-yuv410;
|
||||
&sub-yuv422p;
|
||||
&sub-yuv411p;
|
||||
|
|
|
@ -60,9 +60,19 @@ input</refpurpose>
|
|||
automatically, similar to sensing the video standard. To do so, applications
|
||||
call <constant>VIDIOC_QUERY_DV_TIMINGS</constant> with a pointer to a
|
||||
&v4l2-dv-timings;. Once the hardware detects the timings, it will fill in the
|
||||
timings structure.
|
||||
timings structure.</para>
|
||||
|
||||
If the timings could not be detected because there was no signal, then
|
||||
<para>Please note that drivers shall <emphasis>not</emphasis> switch timings automatically
|
||||
if new timings are detected. Instead, drivers should send the
|
||||
<constant>V4L2_EVENT_SOURCE_CHANGE</constant> event (if they support this) and expect
|
||||
that userspace will take action by calling <constant>VIDIOC_QUERY_DV_TIMINGS</constant>.
|
||||
The reason is that new timings usually mean different buffer sizes as well, and you
|
||||
cannot change buffer sizes on the fly. In general, applications that receive the
|
||||
Source Change event will have to call <constant>VIDIOC_QUERY_DV_TIMINGS</constant>,
|
||||
and if the detected timings are valid they will have to stop streaming, set the new
|
||||
timings, allocate new buffers and start streaming again.</para>
|
||||
|
||||
<para>If the timings could not be detected because there was no signal, then
|
||||
<errorcode>ENOLINK</errorcode> is returned. If a signal was detected, but
|
||||
it was unstable and the receiver could not lock to the signal, then
|
||||
<errorcode>ENOLCK</errorcode> is returned. If the receiver could lock to the signal,
|
||||
|
|
|
@ -59,6 +59,16 @@ then the driver will return V4L2_STD_UNKNOWN. When detection is not
|
|||
possible or fails, the set must contain all standards supported by the
|
||||
current video input or output.</para>
|
||||
|
||||
<para>Please note that drivers shall <emphasis>not</emphasis> switch the video standard
|
||||
automatically if a new video standard is detected. Instead, drivers should send the
|
||||
<constant>V4L2_EVENT_SOURCE_CHANGE</constant> event (if they support this) and expect
|
||||
that userspace will take action by calling <constant>VIDIOC_QUERYSTD</constant>.
|
||||
The reason is that a new video standard can mean different buffer sizes as well, and you
|
||||
cannot change buffer sizes on the fly. In general, applications that receive the
|
||||
Source Change event will have to call <constant>VIDIOC_QUERYSTD</constant>,
|
||||
and if the detected video standard is valid they will have to stop streaming, set the new
|
||||
standard, allocate new buffers and start streaming again.</para>
|
||||
|
||||
</refsect1>
|
||||
|
||||
<refsect1>
|
||||
|
|
|
@ -7,7 +7,7 @@ This is the authoritative documentation on the design, interface and
|
|||
conventions of cgroup v2. It describes all userland-visible aspects
|
||||
of cgroup including core and specific controller behaviors. All
|
||||
future changes must be reflected in this document. Documentation for
|
||||
v1 is available under Documentation/cgroup-legacy/.
|
||||
v1 is available under Documentation/cgroup-v1/.
|
||||
|
||||
CONTENTS
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@ Optional properties:
|
|||
during suspend.
|
||||
- ti,no-reset-on-init: When present, the module should not be reset at init
|
||||
- ti,no-idle-on-init: When present, the module should not be idled at init
|
||||
- ti,no-idle: When present, the module is never allowed to idle.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following
|
|||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
|
|
|
@ -35,6 +35,12 @@ Optional properties for HDMI:
|
|||
as an interrupt/status bit in the HDMI controller
|
||||
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
|
||||
|
||||
Required properties for V3D:
|
||||
- compatible: Should be "brcm,bcm2835-v3d"
|
||||
- reg: Physical base address and length of the V3D's registers
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
Example:
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
|
@ -60,6 +66,12 @@ hdmi: hdmi@7e902000 {
|
|||
clock-names = "pixel", "hdmi";
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
|
|
|
@ -6,6 +6,7 @@ Required properties:
|
|||
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
|
||||
"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
|
||||
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
|
||||
"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
|
||||
"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
|
||||
- reg: physical base address and length of the registers set for the device
|
||||
- interrupts: should contain DSI interrupt
|
||||
|
|
|
@ -12,7 +12,8 @@ Required properties:
|
|||
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
|
||||
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
|
||||
"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
|
||||
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
|
||||
"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
|
||||
"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
|
||||
|
||||
- reg: physical base address and length of the FIMD registers set.
|
||||
|
||||
|
|
|
@ -44,9 +44,34 @@ Optional properties:
|
|||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- port: DSI controller output port. This contains one endpoint subnode, with its
|
||||
remote-endpoint set to the phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- port: DSI controller output port, containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: set to phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
|
||||
to the physical lanes on the given platform. The value contained in
|
||||
index n describes what logical data lane is mapped to the physical data
|
||||
lane n (DATAn, where n lies between 0 and 3).
|
||||
|
||||
For example:
|
||||
|
||||
qcom,data-lane-map = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA3 is mapped to
|
||||
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
|
||||
to phys DATA2 and logic DATA2 to phys DATA3.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
|
||||
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
|
||||
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
|
||||
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
|
||||
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
|
||||
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
|
||||
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
|
||||
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
|
||||
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
|
@ -131,6 +156,7 @@ Example:
|
|||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -11,6 +11,7 @@ Required properties:
|
|||
- reg: Physical base address and length of the controller's registers
|
||||
- reg-names: "core_physical"
|
||||
- interrupts: The interrupt signal from the hdmi block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
|
||||
|
@ -18,6 +19,8 @@ Required properties:
|
|||
- qcom,hdmi-tx-hpd-gpio: hpd pin
|
||||
- core-vdda-supply: phandle to supply regulator
|
||||
- hdmi-mux-supply: phandle to mux regulator
|
||||
- phys: the phandle for the HDMI PHY device
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
|
||||
Optional properties:
|
||||
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
|
||||
|
@ -27,15 +30,38 @@ Optional properties:
|
|||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-1: the "sleep" pinctrl state
|
||||
|
||||
HDMI PHY:
|
||||
Required properties:
|
||||
- compatible: Could be the following
|
||||
* "qcom,hdmi-phy-8660"
|
||||
* "qcom,hdmi-phy-8960"
|
||||
* "qcom,hdmi-phy-8974"
|
||||
* "qcom,hdmi-phy-8084"
|
||||
* "qcom,hdmi-phy-8996"
|
||||
- #phy-cells: Number of cells in a PHY specifier; Should be 0.
|
||||
- reg: Physical base address and length of the registers of the PHY sub blocks.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "hdmi_phy"
|
||||
* "hdmi_pll"
|
||||
For HDMI PHY on msm8996, these additional register regions are required:
|
||||
* "hdmi_tx_l0"
|
||||
* "hdmi_tx_l1"
|
||||
* "hdmi_tx_l3"
|
||||
* "hdmi_tx_l4"
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- core-vdda-supply: phandle to vdda regulator device node
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: qcom,hdmi-tx-8960@4a00000 {
|
||||
hdmi: hdmi@4a00000 {
|
||||
compatible = "qcom,hdmi-tx-8960";
|
||||
reg-names = "core_physical";
|
||||
reg = <0x04a00000 0x1000>;
|
||||
reg = <0x04a00000 0x2f0>;
|
||||
interrupts = <GIC_SPI 79 0>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names =
|
||||
|
@ -54,5 +80,21 @@ Example:
|
|||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
|
||||
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
|
||||
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi_phy";
|
||||
};
|
||||
|
||||
hdmi_phy: phy@4a00400 {
|
||||
compatible = "qcom,hdmi-phy-8960";
|
||||
reg-names = "hdmi_phy",
|
||||
"hdmi_pll";
|
||||
reg = <0x4a00400 0x60>,
|
||||
<0x4a00500 0x100>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names = "slave_iface_clk";
|
||||
clocks = <&mmcc HDMI_S_AHB_CLK>;
|
||||
core-vdda-supply = <&pm8921_hdmi_mvs>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -8,6 +8,7 @@ Required Properties:
|
|||
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
|
||||
- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
|
||||
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
|
||||
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
|
||||
|
||||
- reg: A list of base address and length of each memory resource, one for
|
||||
each entry in the reg-names property.
|
||||
|
@ -24,7 +25,7 @@ Required Properties:
|
|||
- clock-names: Name of the clocks. This property is model-dependent.
|
||||
- R8A7779 uses a single functional clock. The clock doesn't need to be
|
||||
named.
|
||||
- R8A779[0134] use one functional clock per channel and one clock per LVDS
|
||||
- R8A779[01345] use one functional clock per channel and one clock per LVDS
|
||||
encoder (if available). The functional clocks must be named "du.x" with
|
||||
"x" being the channel numerical index. The LVDS clocks must be named
|
||||
"lvds.x" with "x" being the LVDS encoder numerical index.
|
||||
|
@ -41,13 +42,14 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
|
|||
The following table lists for each supported model the port number
|
||||
corresponding to each DU output.
|
||||
|
||||
Port 0 Port1 Port2
|
||||
Port 0 Port1 Port2 Port3
|
||||
-----------------------------------------------------------------------------
|
||||
R8A7779 (H1) DPAD 0 DPAD 1 -
|
||||
R8A7790 (H2) DPAD LVDS 0 LVDS 1
|
||||
R8A7791 (M2-W) DPAD LVDS 0 -
|
||||
R8A7793 (M2-N) DPAD LVDS 0 -
|
||||
R8A7794 (E2) DPAD 0 DPAD 1 -
|
||||
R8A7779 (H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
|
||||
R8A7791 (M2-W) DPAD LVDS 0 - -
|
||||
R8A7793 (M2-N) DPAD LVDS 0 - -
|
||||
R8A7794 (E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) DU
|
||||
|
|
|
@ -0,0 +1,50 @@
|
|||
Rockchip specific extensions to the Innosilicon HDMI
|
||||
================================
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
"rockchip,rk3036-inno-hdmi";
|
||||
- reg:
|
||||
Physical base address and length of the controller's registers.
|
||||
- clocks, clock-names:
|
||||
Phandle to hdmi controller clock, name should be "pclk"
|
||||
- interrupts:
|
||||
HDMI interrupt number
|
||||
- ports:
|
||||
Contain one port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/graph.txt.
|
||||
- pinctrl-0, pinctrl-name:
|
||||
Switch the iomux of HPD/CEC pins to HDMI function.
|
||||
|
||||
Example:
|
||||
hdmi: hdmi@20034000 {
|
||||
compatible = "rockchip,rk3036-inno-hdmi";
|
||||
reg = <0x20034000 0x4000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_HDMI>;
|
||||
clock-names = "pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_ctl>;
|
||||
status = "disabled";
|
||||
|
||||
hdmi_in: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
hdmi_in_lcdc: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&lcdc_out_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi {
|
||||
hdmi_ctl: hdmi-ctl {
|
||||
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 9 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 10 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
|
@ -24,9 +24,8 @@ Main node required properties:
|
|||
1 = edge triggered
|
||||
4 = level triggered
|
||||
|
||||
Cells 4 and beyond are reserved for future use. When the 1st cell
|
||||
has a value of 0 or 1, cells 4 and beyond act as padding, and may be
|
||||
ignored. It is recommended that padding cells have a value of 0.
|
||||
Cells 4 and beyond are reserved for future use and must have a value
|
||||
of 0 if present.
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC
|
||||
registers, in the following order:
|
||||
|
|
|
@ -20,6 +20,8 @@ Optional Properties:
|
|||
|
||||
- link-frequencies: List of allowed link frequencies in Hz. Each frequency is
|
||||
expressed as a 64-bit big-endian integer.
|
||||
- reset-gpios: GPIO handle which is connected to the reset pin of the chip.
|
||||
- standby-gpios: GPIO handle which is connected to the standby pin of the chip.
|
||||
|
||||
For further reading on port node refer to
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
|
88
Documentation/devicetree/bindings/media/i2c/tvp5150.txt
Normal file
88
Documentation/devicetree/bindings/media/i2c/tvp5150.txt
Normal file
|
@ -0,0 +1,88 @@
|
|||
* Texas Instruments TVP5150 and TVP5151 video decoders
|
||||
|
||||
The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL
|
||||
(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
|
||||
with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats.
|
||||
|
||||
Required Properties:
|
||||
- compatible: value must be "ti,tvp5150"
|
||||
- reg: I2C slave address
|
||||
|
||||
Optional Properties:
|
||||
- pdn-gpios: phandle for the GPIO connected to the PDN pin, if any.
|
||||
- reset-gpios: phandle for the GPIO connected to the RESETB pin, if any.
|
||||
|
||||
Optional nodes:
|
||||
- connectors: The input connectors of tvp5150 have to be defined under
|
||||
a subnode name "connectors" using the following format:
|
||||
|
||||
input-connector-name {
|
||||
input connector properties
|
||||
};
|
||||
|
||||
Each input connector must contain the following properties:
|
||||
|
||||
- label: a name for the connector.
|
||||
- input: the input connector.
|
||||
|
||||
The possible values for the "input" property are:
|
||||
0: Composite0
|
||||
1: Composite1
|
||||
2: S-Video
|
||||
|
||||
and on a tvp5150am1 and tvp5151 there is another:
|
||||
4: Signal generator
|
||||
|
||||
The list of valid input connectors are defined in dt-bindings/media/tvp5150.h
|
||||
header file and can be included by device tree source files.
|
||||
|
||||
Each input connector can be defined only once.
|
||||
|
||||
The device node must contain one 'port' child node for its digital output
|
||||
video port, in accordance with the video interface bindings defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
||||
Required Endpoint Properties for parallel synchronization:
|
||||
|
||||
- hsync-active: active state of the HSYNC signal. Must be <1> (HIGH).
|
||||
- vsync-active: active state of the VSYNC signal. Must be <1> (HIGH).
|
||||
- field-even-active: field signal level during the even field data
|
||||
transmission. Must be <0>.
|
||||
|
||||
If none of hsync-active, vsync-active and field-even-active is specified,
|
||||
the endpoint is assumed to use embedded BT.656 synchronization.
|
||||
|
||||
Example:
|
||||
|
||||
&i2c2 {
|
||||
...
|
||||
tvp5150@5c {
|
||||
compatible = "ti,tvp5150";
|
||||
reg = <0x5c>;
|
||||
pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
connectors {
|
||||
composite0 {
|
||||
label = "Composite0";
|
||||
input = <TVP5150_COMPOSITE0>;
|
||||
};
|
||||
|
||||
composite1 {
|
||||
label = "Composite1";
|
||||
input = <TVP5150_COMPOSITE1>;
|
||||
};
|
||||
|
||||
s-video {
|
||||
label = "S-Video";
|
||||
input = <TVP5150_SVIDEO>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
tvp5150_1: endpoint {
|
||||
remote-endpoint = <&ccdc_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -6,6 +6,7 @@ family of devices. The current blocks are always slaves and suppot one input
|
|||
channel which can be either RGB, YUYV or BT656.
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,vin-r8a7795" for the R8A7795 device
|
||||
- "renesas,vin-r8a7794" for the R8A7794 device
|
||||
- "renesas,vin-r8a7793" for the R8A7793 device
|
||||
- "renesas,vin-r8a7791" for the R8A7791 device
|
||||
|
|
|
@ -5,11 +5,12 @@ and decoding function conforming to the JPEG baseline process, so that the JPU
|
|||
can encode image data and decode JPEG data quickly.
|
||||
|
||||
Required properties:
|
||||
- compatible: should containg one of the following:
|
||||
- "renesas,jpu-r8a7790" for R-Car H2
|
||||
- "renesas,jpu-r8a7791" for R-Car M2-W
|
||||
- "renesas,jpu-r8a7792" for R-Car V2H
|
||||
- "renesas,jpu-r8a7793" for R-Car M2-N
|
||||
- compatible: "renesas,jpu-<soctype>", "renesas,rcar-gen2-jpu" as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,jpu-r8a7790" for R-Car H2
|
||||
- "renesas,jpu-r8a7791" for R-Car M2-W
|
||||
- "renesas,jpu-r8a7792" for R-Car V2H
|
||||
- "renesas,jpu-r8a7793" for R-Car M2-N
|
||||
|
||||
- reg: Base address and length of the registers block for the JPU.
|
||||
- interrupts: JPU interrupt specifier.
|
||||
|
@ -17,7 +18,7 @@ Required properties:
|
|||
|
||||
Example: R8A7790 (R-Car H2) JPU node
|
||||
jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7790";
|
||||
compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
|
||||
|
|
|
@ -1,30 +1,18 @@
|
|||
* Renesas VSP1 Video Processing Engine
|
||||
* Renesas VSP Video Processing Engine
|
||||
|
||||
The VSP1 is a video processing engine that supports up-/down-scaling, alpha
|
||||
The VSP is a video processing engine that supports up-/down-scaling, alpha
|
||||
blending, color space conversion and various other image processing features.
|
||||
It can be found in the Renesas R-Car second generation SoCs.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must contain "renesas,vsp1"
|
||||
- compatible: Must contain one of the following values
|
||||
- "renesas,vsp1" for the R-Car Gen2 VSP1
|
||||
- "renesas,vsp2" for the R-Car Gen3 VSP2
|
||||
|
||||
- reg: Base address and length of the registers block for the VSP1.
|
||||
- interrupts: VSP1 interrupt specifier.
|
||||
- clocks: A phandle + clock-specifier pair for the VSP1 functional clock.
|
||||
|
||||
- renesas,#rpf: Number of Read Pixel Formatter (RPF) modules in the VSP1.
|
||||
- renesas,#uds: Number of Up Down Scaler (UDS) modules in the VSP1.
|
||||
- renesas,#wpf: Number of Write Pixel Formatter (WPF) modules in the VSP1.
|
||||
|
||||
|
||||
Optional properties:
|
||||
|
||||
- renesas,has-lif: Boolean, indicates that the LCD Interface (LIF) module is
|
||||
available.
|
||||
- renesas,has-lut: Boolean, indicates that the Look Up Table (LUT) module is
|
||||
available.
|
||||
- renesas,has-sru: Boolean, indicates that the Super Resolution Unit (SRU)
|
||||
module is available.
|
||||
- reg: Base address and length of the registers block for the VSP.
|
||||
- interrupts: VSP interrupt specifier.
|
||||
- clocks: A phandle + clock-specifier pair for the VSP functional clock.
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) VSP1-S node
|
||||
|
@ -34,10 +22,4 @@ Example: R8A7790 (R-Car H2) VSP1-S node
|
|||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
renesas,#rpf = <5>;
|
||||
renesas,#uds = <3>;
|
||||
renesas,#wpf = <4>;
|
||||
};
|
||||
|
|
72
Documentation/devicetree/bindings/media/ti-cal.txt
Normal file
72
Documentation/devicetree/bindings/media/ti-cal.txt
Normal file
|
@ -0,0 +1,72 @@
|
|||
Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL)
|
||||
------------------------------------------------------
|
||||
|
||||
The Camera Adaptation Layer (CAL) is a key component for image capture
|
||||
applications. The capture module provides the system interface and the
|
||||
processing capability to connect CSI2 image-sensor modules to the
|
||||
DRA72x device.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "ti,dra72-cal"
|
||||
- reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX
|
||||
control address space
|
||||
- reg-names: cal_top, cal_rx_core0, cal_rx_core1, and camerrx_control
|
||||
registers
|
||||
- interrupts: should contain IRQ line for the CAL;
|
||||
|
||||
CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes
|
||||
should contain a 'port' child node with child 'endpoint' node. Please
|
||||
refer to the bindings defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
|
||||
Example:
|
||||
cal: cal@4845b000 {
|
||||
compatible = "ti,dra72-cal";
|
||||
ti,hwmods = "cal";
|
||||
reg = <0x4845B000 0x400>,
|
||||
<0x4845B800 0x40>,
|
||||
<0x4845B900 0x40>,
|
||||
<0x4A002e94 0x4>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0",
|
||||
"cal_rx_core1",
|
||||
"camerrx_control";
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&ar0330_1>;
|
||||
};
|
||||
};
|
||||
csi2_1: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c5: i2c@4807c000 {
|
||||
ar0330@10 {
|
||||
compatible = "ti,ar0330";
|
||||
reg = <0x10>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ar0330_1: endpoint {
|
||||
reg = <0>;
|
||||
clock-lanes = <1>;
|
||||
data-lanes = <0 2 3 4>;
|
||||
remote-endpoint = <&csi2_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -82,8 +82,8 @@ Example:
|
|||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&mstp8_clks R8A7795_CLK_ETHERAVB>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&cpg>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
|
|
|
@ -8,6 +8,7 @@ OHCI and EHCI controllers.
|
|||
Required properties:
|
||||
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pci-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pci-r8a7793" for the R8A7793 SoC;
|
||||
"renesas,pci-r8a7794" for the R8A7794 SoC;
|
||||
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
|
||||
|
||||
|
|
|
@ -4,6 +4,7 @@ Required properties:
|
|||
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
|
||||
"renesas,pcie-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pcie-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pcie-r8a7793" for the R8A7793 SoC;
|
||||
"renesas,pcie-r8a7795" for the R8A7795 SoC;
|
||||
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
|
||||
|
||||
|
|
|
@ -26,11 +26,7 @@ Example:
|
|||
ti,pmic-shutdown-controller;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: dcdc1 {
|
||||
reg = <0>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
|
@ -38,7 +34,6 @@ Example:
|
|||
};
|
||||
|
||||
dcdc2_reg: dcdc2 {
|
||||
reg = <1>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
@ -46,7 +41,6 @@ Example:
|
|||
};
|
||||
|
||||
dcdc3_reg: dcc3 {
|
||||
reg = <2>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
|
@ -54,7 +48,6 @@ Example:
|
|||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
reg = <3>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
@ -62,7 +55,6 @@ Example:
|
|||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
reg = <4>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
@ -70,7 +62,6 @@ Example:
|
|||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
reg = <5>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
@ -78,7 +69,6 @@ Example:
|
|||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
reg = <6>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
|
|
@ -14,6 +14,10 @@ Required properties:
|
|||
interrupt number is the rtc alarm interrupt and second interrupt number
|
||||
is the rtc tick interrupt. The number of cells representing a interrupt
|
||||
depends on the parent interrupt controller.
|
||||
- clocks: Must contain a list of phandle and clock specifier for the rtc
|
||||
and source clocks.
|
||||
- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the
|
||||
same order as the clocks property.
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -21,4 +25,6 @@ Example:
|
|||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <44 0 45 0>;
|
||||
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
|
||||
clock-names = "rtc", "rtc_src";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@ Optional properties:
|
|||
- fsl,uart-has-rtscts : Indicate the uart has rts and cts
|
||||
- fsl,irda-mode : Indicate the uart supports irda mode
|
||||
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
|
||||
is DCE mode by default.
|
||||
in DCE mode by default.
|
||||
|
||||
Note: Each uart controller should have an alias correctly numbered
|
||||
in "aliases" node.
|
||||
|
|
|
@ -30,6 +30,8 @@ The compatible list for this generic sound card currently:
|
|||
"fsl,imx-audio-sgtl5000"
|
||||
(compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
|
||||
|
||||
"fsl,imx-audio-wm8960"
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Contains one of entries in the compatible list.
|
||||
|
|
|
@ -1,8 +1,9 @@
|
|||
* Renesas R-Car Thermal
|
||||
|
||||
Required properties:
|
||||
- compatible : "renesas,thermal-<soctype>", "renesas,rcar-thermal"
|
||||
as fallback.
|
||||
- compatible : "renesas,thermal-<soctype>",
|
||||
"renesas,rcar-gen2-thermal" (with thermal-zone) or
|
||||
"renesas,rcar-thermal" (without thermal-zone) as fallback.
|
||||
Examples with soctypes are:
|
||||
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
|
||||
- "renesas,thermal-r8a7779" (R-Car H1)
|
||||
|
@ -36,3 +37,35 @@ thermal@e61f0000 {
|
|||
0xe61f0300 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
Example (with thermal-zone):
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
|
||||
thermal-sensors = <&thermal>;
|
||||
|
||||
trips {
|
||||
cpu-crit {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal: thermal@e61f0000 {
|
||||
compatible = "renesas,thermal-r8a7790",
|
||||
"renesas,rcar-gen2-thermal",
|
||||
"renesas,rcar-thermal";
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
|
|
@ -350,7 +350,26 @@ Being able to mmap an export dma-buf buffer object has 2 main use-cases:
|
|||
handles, too). So it's beneficial to support this in a similar fashion on
|
||||
dma-buf to have a good transition path for existing Android userspace.
|
||||
|
||||
No special interfaces, userspace simply calls mmap on the dma-buf fd.
|
||||
No special interfaces, userspace simply calls mmap on the dma-buf fd, making
|
||||
sure that the cache synchronization ioctl (DMA_BUF_IOCTL_SYNC) is *always*
|
||||
used when the access happens. This is discussed next paragraphs.
|
||||
|
||||
Some systems might need some sort of cache coherency management e.g. when
|
||||
CPU and GPU domains are being accessed through dma-buf at the same time. To
|
||||
circumvent this problem there are begin/end coherency markers, that forward
|
||||
directly to existing dma-buf device drivers vfunc hooks. Userspace can make
|
||||
use of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence
|
||||
would be used like following:
|
||||
- mmap dma-buf fd
|
||||
- for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
|
||||
to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
|
||||
want (with the new data being consumed by the GPU or say scanout device)
|
||||
- munmap once you don't need the buffer any more
|
||||
|
||||
Therefore, for correctness and optimal performance, systems with the memory
|
||||
cache shared by the GPU and CPU i.e. the "coherent" and also the
|
||||
"incoherent" are always required to use SYNC_START and SYNC_END before and
|
||||
after, respectively, when accessing the mapped address.
|
||||
|
||||
2. Supporting existing mmap interfaces in importers
|
||||
|
||||
|
|
|
@ -190,7 +190,7 @@ and watch another one.
|
|||
Patches, comments and suggestions are very very welcome.
|
||||
|
||||
3. Acknowledgements
|
||||
Amaury Demol (ademol@dibcom.fr) and Francois Kanounnikoff from DiBcom for
|
||||
Amaury Demol (Amaury.Demol@parrot.com) and Francois Kanounnikoff from DiBcom for
|
||||
providing specs, code and help, on which the dvb-dibusb, dib3000mb and
|
||||
dib3000mc are based.
|
||||
|
||||
|
|
|
@ -14,3 +14,10 @@ filesystem.
|
|||
efivarfs is typically mounted like this,
|
||||
|
||||
mount -t efivarfs none /sys/firmware/efi/efivars
|
||||
|
||||
Due to the presence of numerous firmware bugs where removing non-standard
|
||||
UEFI variables causes the system firmware to fail to POST, efivarfs
|
||||
files that are not well-known standardized variables are created
|
||||
as immutable files. This doesn't prevent removal - "chattr -i" will work -
|
||||
but it does prevent this kind of failure from being accomplished
|
||||
accidentally.
|
||||
|
|
|
@ -4235,6 +4235,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
The default value of this parameter is determined by
|
||||
the config option CONFIG_WQ_POWER_EFFICIENT_DEFAULT.
|
||||
|
||||
workqueue.debug_force_rr_cpu
|
||||
Workqueue used to implicitly guarantee that work
|
||||
items queued without explicit CPU specified are put
|
||||
on the local CPU. This guarantee is no longer true
|
||||
and while local CPU is still preferred work items
|
||||
may be put on foreign CPUs. This debug option
|
||||
forces round-robin CPU selection to flush out
|
||||
usages which depend on the now broken guarantee.
|
||||
When enabled, memory and cache locality will be
|
||||
impacted.
|
||||
|
||||
x2apic_phys [X86-64,APIC] Use x2apic physical mode instead of
|
||||
default x2apic cluster mode on platforms
|
||||
supporting x2apic.
|
||||
|
|
|
@ -1,9 +1,7 @@
|
|||
High Precision Event Timer Driver for Linux
|
||||
|
||||
The High Precision Event Timer (HPET) hardware follows a specification
|
||||
by Intel and Microsoft which can be found at
|
||||
|
||||
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
|
||||
by Intel and Microsoft, revision 1.
|
||||
|
||||
Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
|
||||
and up to 32 comparators. Normally three or more comparators are provided,
|
||||
|
|
|
@ -647,7 +647,6 @@ Or you can add specific controls to a handler:
|
|||
volume = v4l2_ctrl_new_std(&video_ctrl_handler, &ops, V4L2_CID_AUDIO_VOLUME, ...);
|
||||
v4l2_ctrl_new_std(&video_ctrl_handler, &ops, V4L2_CID_BRIGHTNESS, ...);
|
||||
v4l2_ctrl_new_std(&video_ctrl_handler, &ops, V4L2_CID_CONTRAST, ...);
|
||||
v4l2_ctrl_add_ctrl(&radio_ctrl_handler, volume);
|
||||
|
||||
What you should not do is make two identical controls for two handlers.
|
||||
For example:
|
||||
|
|
|
@ -358,7 +358,8 @@ In the first case there are two additional complications:
|
|||
- if CR4.SMEP is enabled: since we've turned the page into a kernel page,
|
||||
the kernel may now execute it. We handle this by also setting spte.nx.
|
||||
If we get a user fetch or read fault, we'll change spte.u=1 and
|
||||
spte.nx=gpte.nx back.
|
||||
spte.nx=gpte.nx back. For this to work, KVM forces EFER.NX to 1 when
|
||||
shadow paging is in use.
|
||||
- if CR4.SMAP is disabled: since the page has been changed to a kernel
|
||||
page, it can not be reused when CR4.SMAP is enabled. We set
|
||||
CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note,
|
||||
|
|
|
@ -400,3 +400,7 @@ wm8350_wdt:
|
|||
nowayout: Watchdog cannot be stopped once started
|
||||
(default=kernel config parameter)
|
||||
-------------------------------------------------
|
||||
sun4v_wdt:
|
||||
timeout_ms: Watchdog timeout in milliseconds 1..180000, default=60000)
|
||||
nowayout: Watchdog cannot be stopped once started
|
||||
-------------------------------------------------
|
||||
|
|
88
MAINTAINERS
88
MAINTAINERS
|
@ -827,6 +827,12 @@ S: Maintained
|
|||
F: drivers/net/arcnet/
|
||||
F: include/uapi/linux/if_arcnet.h
|
||||
|
||||
ARM HDLCD DRM DRIVER
|
||||
M: Liviu Dudau <liviu.dudau@arm.com>
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/arm/
|
||||
F: Documentation/devicetree/bindings/display/arm,hdlcd.txt
|
||||
|
||||
ARM MFM AND FLOPPY DRIVERS
|
||||
M: Ian Molton <spyro@f2s.com>
|
||||
S: Maintained
|
||||
|
@ -920,17 +926,24 @@ M: Emilio López <emilio@elopez.com.ar>
|
|||
S: Maintained
|
||||
F: drivers/clk/sunxi/
|
||||
|
||||
ARM/Amlogic MesonX SoC support
|
||||
ARM/Amlogic Meson SoC support
|
||||
M: Carlo Caione <carlo@caione.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-meson@googlegroups.com
|
||||
W: http://linux-meson.com/
|
||||
S: Maintained
|
||||
F: drivers/media/rc/meson-ir.c
|
||||
N: meson[x68]
|
||||
F: arch/arm/mach-meson/
|
||||
F: arch/arm/boot/dts/meson*
|
||||
N: meson
|
||||
|
||||
ARM/Annapurna Labs ALPINE ARCHITECTURE
|
||||
M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
|
||||
M: Antoine Tenart <antoine.tenart@free-electrons.com>
|
||||
S: Maintained
|
||||
F: arch/arm/mach-alpine/
|
||||
F: arch/arm/boot/dts/alpine*
|
||||
F: arch/arm64/boot/dts/al/
|
||||
F: drivers/*/*alpine*
|
||||
|
||||
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
|
||||
M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
|
@ -1442,8 +1455,8 @@ S: Maintained
|
|||
ARM/RENESAS ARM64 ARCHITECTURE
|
||||
M: Simon Horman <horms@verge.net.au>
|
||||
M: Magnus Damm <magnus.damm@gmail.com>
|
||||
L: linux-sh@vger.kernel.org
|
||||
Q: http://patchwork.kernel.org/project/linux-sh/list/
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
|
||||
S: Supported
|
||||
F: arch/arm64/boot/dts/renesas/
|
||||
|
@ -2362,14 +2375,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git
|
|||
S: Maintained
|
||||
N: bcm2835
|
||||
|
||||
BROADCOM BCM33XX MIPS ARCHITECTURE
|
||||
M: Kevin Cernekee <cernekee@gmail.com>
|
||||
L: linux-mips@linux-mips.org
|
||||
S: Maintained
|
||||
F: arch/mips/bcm3384/*
|
||||
F: arch/mips/include/asm/mach-bcm3384/*
|
||||
F: arch/mips/kernel/*bmips*
|
||||
|
||||
BROADCOM BCM47XX MIPS ARCHITECTURE
|
||||
M: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
M: Rafał Miłecki <zajec5@gmail.com>
|
||||
|
@ -3452,7 +3457,6 @@ F: drivers/usb/dwc2/
|
|||
DESIGNWARE USB3 DRD IP DRIVER
|
||||
M: Felipe Balbi <balbi@kernel.org>
|
||||
L: linux-usb@vger.kernel.org
|
||||
L: linux-omap@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
|
||||
S: Maintained
|
||||
F: drivers/usb/dwc3/
|
||||
|
@ -3758,7 +3762,7 @@ F: include/drm/exynos*
|
|||
F: include/uapi/drm/exynos*
|
||||
|
||||
DRM DRIVERS FOR FREESCALE DCU
|
||||
M: Jianwei Wang <jianwei.wang.chn@gmail.com>
|
||||
M: Stefan Agner <stefan@agner.ch>
|
||||
M: Alison Wang <alison.wang@freescale.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
|
@ -4520,6 +4524,12 @@ L: linuxppc-dev@lists.ozlabs.org
|
|||
S: Maintained
|
||||
F: drivers/dma/fsldma.*
|
||||
|
||||
FREESCALE GPMI NAND DRIVER
|
||||
M: Han Xu <han.xu@nxp.com>
|
||||
L: linux-mtd@lists.infradead.org
|
||||
S: Maintained
|
||||
F: drivers/mtd/nand/gpmi-nand/*
|
||||
|
||||
FREESCALE I2C CPM DRIVER
|
||||
M: Jochen Friedrich <jochen@scram.de>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
|
@ -4536,7 +4546,7 @@ F: include/linux/platform_data/video-imxfb.h
|
|||
F: drivers/video/fbdev/imxfb.c
|
||||
|
||||
FREESCALE QUAD SPI DRIVER
|
||||
M: Han Xu <han.xu@freescale.com>
|
||||
M: Han Xu <han.xu@nxp.com>
|
||||
L: linux-mtd@lists.infradead.org
|
||||
S: Maintained
|
||||
F: drivers/mtd/spi-nor/fsl-quadspi.c
|
||||
|
@ -4550,6 +4560,15 @@ S: Maintained
|
|||
F: drivers/net/ethernet/freescale/fs_enet/
|
||||
F: include/linux/fs_enet_pd.h
|
||||
|
||||
FREESCALE IMX / MXC FEC DRIVER
|
||||
M: Fugang Duan <fugang.duan@nxp.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/freescale/fec_main.c
|
||||
F: drivers/net/ethernet/freescale/fec_ptp.c
|
||||
F: drivers/net/ethernet/freescale/fec.h
|
||||
F: Documentation/devicetree/bindings/net/fsl-fec.txt
|
||||
|
||||
FREESCALE QUICC ENGINE LIBRARY
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
S: Orphan
|
||||
|
@ -6136,7 +6155,7 @@ F: include/uapi/linux/sunrpc/
|
|||
|
||||
KERNEL SELFTEST FRAMEWORK
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
L: linux-api@vger.kernel.org
|
||||
L: linux-kselftest@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/shuah/linux-kselftest
|
||||
S: Maintained
|
||||
F: tools/testing/selftests
|
||||
|
@ -6766,6 +6785,7 @@ S: Maintained
|
|||
F: Documentation/networking/mac80211-injection.txt
|
||||
F: include/net/mac80211.h
|
||||
F: net/mac80211/
|
||||
F: drivers/net/wireless/mac80211_hwsim.[ch]
|
||||
|
||||
MACVLAN DRIVER
|
||||
M: Patrick McHardy <kaber@trash.net>
|
||||
|
@ -7362,7 +7382,7 @@ F: drivers/tty/isicom.c
|
|||
F: include/linux/isicom.h
|
||||
|
||||
MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER
|
||||
M: Felipe Balbi <balbi@kernel.org>
|
||||
M: Bin Liu <b-liu@ti.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
|
||||
S: Maintained
|
||||
|
@ -7694,13 +7714,13 @@ S: Maintained
|
|||
F: arch/nios2/
|
||||
|
||||
NOKIA N900 POWER SUPPLY DRIVERS
|
||||
M: Pali Rohár <pali.rohar@gmail.com>
|
||||
S: Maintained
|
||||
R: Pali Rohár <pali.rohar@gmail.com>
|
||||
F: include/linux/power/bq2415x_charger.h
|
||||
F: include/linux/power/bq27xxx_battery.h
|
||||
F: include/linux/power/isp1704_charger.h
|
||||
F: drivers/power/bq2415x_charger.c
|
||||
F: drivers/power/bq27xxx_battery.c
|
||||
F: drivers/power/bq27xxx_battery_i2c.c
|
||||
F: drivers/power/isp1704_charger.c
|
||||
F: drivers/power/rx51_battery.c
|
||||
|
||||
|
@ -7931,11 +7951,9 @@ F: drivers/media/platform/omap3isp/
|
|||
F: drivers/staging/media/omap4iss/
|
||||
|
||||
OMAP USB SUPPORT
|
||||
M: Felipe Balbi <balbi@kernel.org>
|
||||
L: linux-usb@vger.kernel.org
|
||||
L: linux-omap@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
|
||||
S: Maintained
|
||||
S: Orphan
|
||||
F: drivers/usb/*/*omap*
|
||||
F: arch/arm/*omap*/usb*
|
||||
|
||||
|
@ -9566,6 +9584,12 @@ M: Andreas Noever <andreas.noever@gmail.com>
|
|||
S: Maintained
|
||||
F: drivers/thunderbolt/
|
||||
|
||||
TI BQ27XXX POWER SUPPLY DRIVER
|
||||
R: Andrew F. Davis <afd@ti.com>
|
||||
F: include/linux/power/bq27xxx_battery.h
|
||||
F: drivers/power/bq27xxx_battery.c
|
||||
F: drivers/power/bq27xxx_battery_i2c.c
|
||||
|
||||
TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
|
||||
M: John Stultz <john.stultz@linaro.org>
|
||||
M: Thomas Gleixner <tglx@linutronix.de>
|
||||
|
@ -9787,10 +9811,11 @@ S: Supported
|
|||
F: drivers/scsi/be2iscsi/
|
||||
|
||||
Emulex 10Gbps NIC BE2, BE3-R, Lancer, Skyhawk-R DRIVER
|
||||
M: Sathya Perla <sathya.perla@avagotech.com>
|
||||
M: Ajit Khaparde <ajit.khaparde@avagotech.com>
|
||||
M: Padmanabh Ratnakar <padmanabh.ratnakar@avagotech.com>
|
||||
M: Sriharsha Basavapatna <sriharsha.basavapatna@avagotech.com>
|
||||
M: Sathya Perla <sathya.perla@broadcom.com>
|
||||
M: Ajit Khaparde <ajit.khaparde@broadcom.com>
|
||||
M: Padmanabh Ratnakar <padmanabh.ratnakar@broadcom.com>
|
||||
M: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
|
||||
M: Somnath Kotur <somnath.kotur@broadcom.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.emulex.com
|
||||
S: Supported
|
||||
|
@ -10849,6 +10874,14 @@ L: linux-omap@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/thermal/ti-soc-thermal/
|
||||
|
||||
TI VPE/CAL DRIVERS
|
||||
M: Benoit Parrot <bparrot@ti.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: http://linuxtv.org/
|
||||
Q: http://patchwork.linuxtv.org/project/linux-media/list/
|
||||
S: Maintained
|
||||
F: drivers/media/platform/ti-vpe/
|
||||
|
||||
TI CDCE706 CLOCK DRIVER
|
||||
M: Max Filippov <jcmvbkbc@gmail.com>
|
||||
S: Maintained
|
||||
|
@ -12020,7 +12053,6 @@ F: arch/arm64/xen/
|
|||
F: arch/arm64/include/asm/xen/
|
||||
|
||||
XEN NETWORK BACKEND DRIVER
|
||||
M: Ian Campbell <ian.campbell@citrix.com>
|
||||
M: Wei Liu <wei.liu2@citrix.com>
|
||||
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
|
||||
L: netdev@vger.kernel.org
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 5
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Blurry Fish Butt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -12,8 +12,6 @@ config ARC
|
|||
select BUILDTIME_EXTABLE_SORT
|
||||
select COMMON_CLK
|
||||
select CLONE_BACKWARDS
|
||||
# ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
|
||||
select DEVTMPFS if !INITRAMFS_SOURCE=""
|
||||
select GENERIC_ATOMIC64
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_FIND_FIRST_BIT
|
||||
|
@ -275,14 +273,6 @@ config ARC_DCCM_BASE
|
|||
default "0xA0000000"
|
||||
depends on ARC_HAS_DCCM
|
||||
|
||||
config ARC_HAS_HW_MPY
|
||||
bool "Use Hardware Multiplier (Normal or Faster XMAC)"
|
||||
default y
|
||||
help
|
||||
Influences how gcc generates code for MPY operations.
|
||||
If enabled, MPYxx insns are generated, provided by Standard/XMAC
|
||||
Multipler. Otherwise software multipy lib is used
|
||||
|
||||
choice
|
||||
prompt "MMU Version"
|
||||
default ARC_MMU_V3 if ARC_CPU_770
|
||||
|
@ -338,6 +328,19 @@ config ARC_PAGE_SIZE_4K
|
|||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "MMU Super Page Size"
|
||||
depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
|
||||
default ARC_HUGEPAGE_2M
|
||||
|
||||
config ARC_HUGEPAGE_2M
|
||||
bool "2MB"
|
||||
|
||||
config ARC_HUGEPAGE_16M
|
||||
bool "16MB"
|
||||
|
||||
endchoice
|
||||
|
||||
if ISA_ARCOMPACT
|
||||
|
||||
config ARC_COMPACT_IRQ_LEVELS
|
||||
|
@ -410,7 +413,7 @@ config ARC_HAS_RTC
|
|||
default n
|
||||
depends on !SMP
|
||||
|
||||
config ARC_HAS_GRTC
|
||||
config ARC_HAS_GFRC
|
||||
bool "SMP synchronized 64-bit cycle counter"
|
||||
default y
|
||||
depends on SMP
|
||||
|
@ -529,14 +532,6 @@ config ARC_DBG_TLB_MISS_COUNT
|
|||
Counts number of I and D TLB Misses and exports them via Debugfs
|
||||
The counters can be cleared via Debugfs as well
|
||||
|
||||
if SMP
|
||||
|
||||
config ARC_IPI_DBG
|
||||
bool "Debug Inter Core interrupts"
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
config ARC_UBOOT_SUPPORT
|
||||
|
@ -566,6 +561,12 @@ endmenu
|
|||
endmenu # "ARC Architecture Configuration"
|
||||
|
||||
source "mm/Kconfig"
|
||||
|
||||
config FORCE_MAX_ZONEORDER
|
||||
int "Maximum zone order"
|
||||
default "12" if ARC_HUGEPAGE_16M
|
||||
default "11"
|
||||
|
||||
source "net/Kconfig"
|
||||
source "drivers/Kconfig"
|
||||
source "fs/Kconfig"
|
||||
|
|
|
@ -74,10 +74,6 @@ ldflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
|
|||
# --build-id w/o "-marclinux". Default arc-elf32-ld is OK
|
||||
ldflags-$(upto_gcc44) += -marclinux
|
||||
|
||||
ifndef CONFIG_ARC_HAS_HW_MPY
|
||||
cflags-y += -mno-mpy
|
||||
endif
|
||||
|
||||
LIBGCC := $(shell $(CC) $(cflags-y) --print-libgcc-file-name)
|
||||
|
||||
# Modules with short calls might break for calls into builtin-kernel
|
||||
|
|
|
@ -39,6 +39,7 @@ CONFIG_IP_PNP_RARP=y
|
|||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -73,7 +74,6 @@ CONFIG_I2C_CHARDEV=y
|
|||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
@ -91,12 +91,10 @@ CONFIG_MMC_SDHCI_PLTFM=y
|
|||
CONFIG_MMC_DW=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
|
|
|
@ -39,14 +39,10 @@ CONFIG_IP_PNP_RARP=y
|
|||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_AXS=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
@ -78,14 +74,12 @@ CONFIG_I2C_CHARDEV=y
|
|||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_LOGO_LINUX_MONO is not set
|
||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
|
@ -97,12 +91,10 @@ CONFIG_MMC_SDHCI_PLTFM=y
|
|||
CONFIG_MMC_DW=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
|
|
|
@ -40,14 +40,10 @@ CONFIG_IP_PNP_RARP=y
|
|||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_AXS=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
@ -79,14 +75,12 @@ CONFIG_I2C_CHARDEV=y
|
|||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_LOGO_LINUX_MONO is not set
|
||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
|
@ -98,12 +92,10 @@ CONFIG_MMC_SDHCI_PLTFM=y
|
|||
CONFIG_MMC_DW=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_DEFAULT_HOSTNAME="ARCLinux"
|
|||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
@ -26,7 +27,6 @@ CONFIG_ARC_PLAT_SIM=y
|
|||
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700"
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -34,6 +34,7 @@ CONFIG_UNIX_DIAG=y
|
|||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -51,7 +52,6 @@ CONFIG_SERIAL_ARC=y
|
|||
CONFIG_SERIAL_ARC_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
|
@ -63,4 +63,3 @@ CONFIG_NFS_FS=y
|
|||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_XZ_DEC=y
|
||||
|
|
|
@ -35,6 +35,7 @@ CONFIG_UNIX_DIAG=y
|
|||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -49,7 +50,6 @@ CONFIG_SERIAL_ARC=y
|
|||
CONFIG_SERIAL_ARC_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
|
@ -61,4 +61,3 @@ CONFIG_NFS_FS=y
|
|||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_XZ_DEC=y
|
||||
|
|
|
@ -2,6 +2,7 @@ CONFIG_CROSS_COMPILE="arc-linux-"
|
|||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_DEFAULT_HOSTNAME="ARCLinux"
|
||||
# CONFIG_SWAP is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
@ -21,13 +22,11 @@ CONFIG_MODULES=y
|
|||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARC_PLAT_SIM=y
|
||||
CONFIG_ARC_BOARD_ML509=y
|
||||
CONFIG_ISA_ARCV2=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu"
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -35,6 +34,7 @@ CONFIG_UNIX_DIAG=y
|
|||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -49,7 +49,6 @@ CONFIG_SERIAL_ARC=y
|
|||
CONFIG_SERIAL_ARC_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
|
@ -60,4 +59,3 @@ CONFIG_TMPFS=y
|
|||
CONFIG_NFS_FS=y
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_XZ_DEC=y
|
||||
|
|
|
@ -33,6 +33,7 @@ CONFIG_UNIX_DIAG=y
|
|||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -58,7 +59,6 @@ CONFIG_SERIAL_OF_PLATFORM=y
|
|||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_HID is not set
|
||||
|
|
|
@ -34,12 +34,12 @@ CONFIG_UNIX_DIAG=y
|
|||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_OSCI_LAN=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_MOUSE_PS2_ALPS is not set
|
||||
# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
|
||||
|
@ -58,7 +58,6 @@ CONFIG_SERIAL_OF_PLATFORM=y
|
|||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_HID is not set
|
||||
|
|
|
@ -2,6 +2,7 @@ CONFIG_CROSS_COMPILE="arc-linux-"
|
|||
CONFIG_DEFAULT_HOSTNAME="ARCLinux"
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
|
@ -18,15 +19,11 @@ CONFIG_MODULES=y
|
|||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARC_PLAT_SIM=y
|
||||
CONFIG_ARC_BOARD_ML509=y
|
||||
CONFIG_ISA_ARCV2=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_ARC_HAS_LL64=y
|
||||
# CONFIG_ARC_HAS_RTSC is not set
|
||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs_idu"
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
|
@ -40,6 +37,7 @@ CONFIG_INET=y
|
|||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
|
@ -56,14 +54,11 @@ CONFIG_NETDEVICES=y
|
|||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_NET_OSCI_LAN=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_MOUSE_PS2_TOUCHKIT=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIO_ARC_PS2=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
|
@ -75,9 +70,6 @@ CONFIG_SERIAL_OF_PLATFORM=y
|
|||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_ARCPGU_RGB888=y
|
||||
CONFIG_ARCPGU_DISPTYPE=0
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_HID is not set
|
||||
|
|
|
@ -3,6 +3,7 @@ CONFIG_CROSS_COMPILE="arc-linux-"
|
|||
CONFIG_DEFAULT_HOSTNAME="tb10x"
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
|
@ -26,12 +27,10 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_BLOCK is not set
|
||||
CONFIG_ARC_PLAT_TB10X=y
|
||||
CONFIG_ARC_CACHE_LINE_SHIFT=5
|
||||
CONFIG_ARC_STACK_NONEXEC=y
|
||||
CONFIG_HZ=250
|
||||
CONFIG_ARC_BUILTIN_DTB_NAME="abilis_tb100_dvk"
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -44,8 +43,8 @@ CONFIG_IP_MULTICAST=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
|
@ -55,9 +54,6 @@ CONFIG_NETDEVICES=y
|
|||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_DEBUG_FS=y
|
||||
CONFIG_STMMAC_DA=y
|
||||
CONFIG_STMMAC_CHAINED=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT is not set
|
||||
|
@ -91,7 +87,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
|||
CONFIG_LEDS_TRIGGER_TRANSIENT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DW_DMAC=y
|
||||
CONFIG_NET_DMA=y
|
||||
CONFIG_ASYNC_TX_DMA=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
|
@ -100,17 +95,16 @@ CONFIG_TMPFS=y
|
|||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_HEADERS_CHECK=y
|
||||
CONFIG_DEBUG_SECTION_MISMATCH=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_SCHEDSTATS=y
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
|
@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y
|
|||
CONFIG_AXS103=y
|
||||
CONFIG_ISA_ARCV2=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_ARC_HAS_GRTC is not set
|
||||
# CONFIG_ARC_HAS_GFRC is not set
|
||||
CONFIG_ARC_UBOOT_SUPPORT=y
|
||||
CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
|
||||
CONFIG_PREEMPT=y
|
||||
|
|
|
@ -10,7 +10,8 @@
|
|||
#define _ASM_ARC_ARCREGS_H
|
||||
|
||||
/* Build Configuration Registers */
|
||||
#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
|
||||
#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
|
||||
#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
|
||||
#define ARC_REG_CRC_BCR 0x62
|
||||
#define ARC_REG_VECBASE_BCR 0x68
|
||||
#define ARC_REG_PERIBASE_BCR 0x69
|
||||
|
@ -18,10 +19,10 @@
|
|||
#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
|
||||
#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
|
||||
#define ARC_REG_SLC_BCR 0xce
|
||||
#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
|
||||
#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
|
||||
#define ARC_REG_TIMERS_BCR 0x75
|
||||
#define ARC_REG_AP_BCR 0x76
|
||||
#define ARC_REG_ICCM_BCR 0x78
|
||||
#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
|
||||
#define ARC_REG_XY_MEM_BCR 0x79
|
||||
#define ARC_REG_MAC_BCR 0x7a
|
||||
#define ARC_REG_MUL_BCR 0x7b
|
||||
|
@ -36,6 +37,7 @@
|
|||
#define ARC_REG_IRQ_BCR 0xF3
|
||||
#define ARC_REG_SMART_BCR 0xFF
|
||||
#define ARC_REG_CLUSTER_BCR 0xcf
|
||||
#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
|
||||
|
||||
/* status32 Bits Positions */
|
||||
#define STATUS_AE_BIT 5 /* Exception active */
|
||||
|
@ -246,7 +248,7 @@ struct bcr_perip {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct bcr_iccm {
|
||||
struct bcr_iccm_arcompact {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int base:16, pad:5, sz:3, ver:8;
|
||||
#else
|
||||
|
@ -254,17 +256,15 @@ struct bcr_iccm {
|
|||
#endif
|
||||
};
|
||||
|
||||
/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
|
||||
struct bcr_dccm_base {
|
||||
struct bcr_iccm_arcv2 {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int addr:24, ver:8;
|
||||
unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, addr:24;
|
||||
unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
|
||||
struct bcr_dccm {
|
||||
struct bcr_dccm_arcompact {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int res:21, sz:3, ver:8;
|
||||
#else
|
||||
|
@ -272,6 +272,14 @@ struct bcr_dccm {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct bcr_dccm_arcv2 {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* ARCompact: Both SP and DP FPU BCRs have same format */
|
||||
struct bcr_fp_arcompact {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
|
@ -315,9 +323,9 @@ struct bcr_bpu_arcv2 {
|
|||
|
||||
struct bcr_generic {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:24, ver:8;
|
||||
unsigned int info:24, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, pad:24;
|
||||
unsigned int ver:8, info:24;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
@ -349,14 +357,13 @@ struct cpuinfo_arc {
|
|||
struct cpuinfo_arc_bpu bpu;
|
||||
struct bcr_identity core;
|
||||
struct bcr_isa isa;
|
||||
struct bcr_timer timers;
|
||||
unsigned int vec_base;
|
||||
struct cpuinfo_arc_ccm iccm, dccm;
|
||||
struct {
|
||||
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
|
||||
fpu_sp:1, fpu_dp:1, pad2:6,
|
||||
debug:1, ap:1, smart:1, rtt:1, pad3:4,
|
||||
pad4:8;
|
||||
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
|
||||
} extn;
|
||||
struct bcr_mpy extn_mpy;
|
||||
struct bcr_extn_xymem extn_xymem;
|
||||
|
|
|
@ -16,11 +16,9 @@
|
|||
#ifdef CONFIG_ISA_ARCOMPACT
|
||||
#define TIMER0_IRQ 3
|
||||
#define TIMER1_IRQ 4
|
||||
#define IPI_IRQ (NR_CPU_IRQS-1) /* dummy to enable SMP build for up hardware */
|
||||
#else
|
||||
#define TIMER0_IRQ 16
|
||||
#define TIMER1_IRQ 17
|
||||
#define IPI_IRQ 19
|
||||
#endif
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#define AUX_IRQ_CTRL 0x00E
|
||||
#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
|
||||
#define AUX_IRQ_LVL_PEND 0x200 /* Pending Intr across all levels */
|
||||
#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
|
||||
#define AUX_IRQ_PRIORITY 0x206
|
||||
#define ICAUSE 0x40a
|
||||
#define AUX_IRQ_SELECT 0x40b
|
||||
|
@ -30,8 +31,11 @@
|
|||
/* Was Intr taken in User Mode */
|
||||
#define AUX_IRQ_ACT_BIT_U 31
|
||||
|
||||
/* 0 is highest level, but taken by FIRQs, if present in design */
|
||||
#define ARCV2_IRQ_DEF_PRIO 0
|
||||
/*
|
||||
* User space should be interruptable even by lowest prio interrupt
|
||||
* Safe even if actual interrupt priorities is fewer or even one
|
||||
*/
|
||||
#define ARCV2_IRQ_DEF_PRIO 15
|
||||
|
||||
/* seed value for status register */
|
||||
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
|
||||
|
@ -112,6 +116,16 @@ static inline int arch_irqs_disabled(void)
|
|||
return arch_irqs_disabled_flags(arch_local_save_flags());
|
||||
}
|
||||
|
||||
static inline void arc_softirq_trigger(int irq)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_HINT, irq);
|
||||
}
|
||||
|
||||
static inline void arc_softirq_clear(int irq)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_HINT, 0);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
.macro IRQ_DISABLE scratch
|
||||
|
|
|
@ -39,8 +39,8 @@ struct mcip_cmd {
|
|||
#define CMD_DEBUG_SET_MASK 0x34
|
||||
#define CMD_DEBUG_SET_SELECT 0x36
|
||||
|
||||
#define CMD_GRTC_READ_LO 0x42
|
||||
#define CMD_GRTC_READ_HI 0x43
|
||||
#define CMD_GFRC_READ_LO 0x42
|
||||
#define CMD_GFRC_READ_HI 0x43
|
||||
|
||||
#define CMD_IDU_ENABLE 0x71
|
||||
#define CMD_IDU_DISABLE 0x72
|
||||
|
|
|
@ -179,37 +179,44 @@
|
|||
#define __S111 PAGE_U_X_W_R
|
||||
|
||||
/****************************************************************
|
||||
* Page Table Lookup split
|
||||
* 2 tier (PGD:PTE) software page walker
|
||||
*
|
||||
* We implement 2 tier paging and since this is all software, we are free
|
||||
* to customize the span of a PGD / PTE entry to suit us
|
||||
*
|
||||
* 32 bit virtual address
|
||||
* [31] 32 bit virtual address [0]
|
||||
* -------------------------------------------------------
|
||||
* | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE |
|
||||
* | | <------------ PGDIR_SHIFT ----------> |
|
||||
* | | |
|
||||
* | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
|
||||
* -------------------------------------------------------
|
||||
* | | |
|
||||
* | | --> off in page frame
|
||||
* | |
|
||||
* | ---> index into Page Table
|
||||
* |
|
||||
* ----> index into Page Directory
|
||||
*
|
||||
* In a single page size configuration, only PAGE_SHIFT is fixed
|
||||
* So both PGD and PTE sizing can be tweaked
|
||||
* e.g. 8K page (PAGE_SHIFT 13) can have
|
||||
* - PGDIR_SHIFT 21 -> 11:8:13 address split
|
||||
* - PGDIR_SHIFT 24 -> 8:11:13 address split
|
||||
*
|
||||
* If Super Page is configured, PGDIR_SHIFT becomes fixed too,
|
||||
* so the sizing flexibility is gone.
|
||||
*/
|
||||
|
||||
#define BITS_IN_PAGE PAGE_SHIFT
|
||||
|
||||
/* Optimal Sizing of Pg Tbl - based on MMU page size */
|
||||
#if defined(CONFIG_ARC_PAGE_SIZE_8K)
|
||||
#define BITS_FOR_PTE 8 /* 11:8:13 */
|
||||
#elif defined(CONFIG_ARC_PAGE_SIZE_16K)
|
||||
#define BITS_FOR_PTE 8 /* 10:8:14 */
|
||||
#elif defined(CONFIG_ARC_PAGE_SIZE_4K)
|
||||
#define BITS_FOR_PTE 9 /* 11:9:12 */
|
||||
#if defined(CONFIG_ARC_HUGEPAGE_16M)
|
||||
#define PGDIR_SHIFT 24
|
||||
#elif defined(CONFIG_ARC_HUGEPAGE_2M)
|
||||
#define PGDIR_SHIFT 21
|
||||
#else
|
||||
/*
|
||||
* Only Normal page support so "hackable" (see comment above)
|
||||
* Default value provides 11:8:13 (8K), 11:9:12 (4K)
|
||||
*/
|
||||
#define PGDIR_SHIFT 21
|
||||
#endif
|
||||
|
||||
#define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE)
|
||||
#define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
|
||||
#define BITS_FOR_PGD (32 - PGDIR_SHIFT)
|
||||
|
||||
#define PGDIR_SHIFT (32 - BITS_FOR_PGD)
|
||||
#define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */
|
||||
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
||||
|
||||
|
|
|
@ -45,11 +45,12 @@ VECTOR reserved ; Reserved slots
|
|||
VECTOR handle_interrupt ; (16) Timer0
|
||||
VECTOR handle_interrupt ; unused (Timer1)
|
||||
VECTOR handle_interrupt ; unused (WDT)
|
||||
VECTOR handle_interrupt ; (19) ICI (inter core interrupt)
|
||||
VECTOR handle_interrupt
|
||||
VECTOR handle_interrupt
|
||||
VECTOR handle_interrupt
|
||||
VECTOR handle_interrupt ; (23) End of fixed IRQs
|
||||
VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
|
||||
VECTOR handle_interrupt ; (20) perf Interrupt
|
||||
VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
|
||||
VECTOR handle_interrupt ; unused
|
||||
VECTOR handle_interrupt ; (23) unused
|
||||
# End of fixed IRQs
|
||||
|
||||
.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8
|
||||
VECTOR handle_interrupt
|
||||
|
@ -211,7 +212,11 @@ debug_marker_syscall:
|
|||
; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
|
||||
; entry was via Exception in DS which got preempted in kernel).
|
||||
;
|
||||
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling
|
||||
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
|
||||
;
|
||||
; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
|
||||
; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
|
||||
|
||||
.Lintr_ret_to_delay_slot:
|
||||
debug_marker_ds:
|
||||
|
||||
|
@ -222,18 +227,23 @@ debug_marker_ds:
|
|||
ld r2, [sp, PT_ret]
|
||||
ld r3, [sp, PT_status32]
|
||||
|
||||
; STAT32 for Int return created from scratch
|
||||
; (No delay dlot, disable Further intr in trampoline)
|
||||
|
||||
bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
|
||||
st r0, [sp, PT_status32]
|
||||
|
||||
mov r1, .Lintr_ret_to_delay_slot_2
|
||||
st r1, [sp, PT_ret]
|
||||
|
||||
; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
|
||||
st r2, [sp, 0]
|
||||
st r3, [sp, 4]
|
||||
|
||||
b .Lisr_ret_fast_path
|
||||
|
||||
.Lintr_ret_to_delay_slot_2:
|
||||
; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
|
||||
sub sp, sp, SZ_PT_REGS
|
||||
st r9, [sp, -4]
|
||||
|
||||
|
@ -243,11 +253,19 @@ debug_marker_ds:
|
|||
ld r9, [sp, 4]
|
||||
sr r9, [erstatus]
|
||||
|
||||
; restore AUX_USER_SP if returning to U mode
|
||||
bbit0 r9, STATUS_U_BIT, 1f
|
||||
ld r9, [sp, PT_sp]
|
||||
sr r9, [AUX_USER_SP]
|
||||
|
||||
1:
|
||||
ld r9, [sp, 8]
|
||||
sr r9, [erbta]
|
||||
|
||||
ld r9, [sp, -4]
|
||||
add sp, sp, SZ_PT_REGS
|
||||
|
||||
; return from pure kernel mode to delay slot
|
||||
rtie
|
||||
|
||||
END(ret_from_exception)
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
static int irq_prio;
|
||||
|
||||
/*
|
||||
* Early Hardware specific Interrupt setup
|
||||
* -Called very early (start_kernel -> setup_arch -> setup_processor)
|
||||
|
@ -24,6 +26,14 @@ void arc_init_IRQ(void)
|
|||
{
|
||||
unsigned int tmp;
|
||||
|
||||
struct irq_build {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
|
||||
#endif
|
||||
} irq_bcr;
|
||||
|
||||
struct aux_irq_ctrl {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int res3:18, save_idx_regs:1, res2:1,
|
||||
|
@ -46,28 +56,25 @@ void arc_init_IRQ(void)
|
|||
|
||||
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
|
||||
|
||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||
tmp = read_aux_reg(0xa);
|
||||
tmp |= ISA_INIT_STATUS_BITS;
|
||||
tmp &= ~STATUS_IE_MASK;
|
||||
asm volatile("flag %0 \n"::"r"(tmp));
|
||||
|
||||
/*
|
||||
* ARCv2 core intc provides multiple interrupt priorities (upto 16).
|
||||
* Typical builds though have only two levels (0-high, 1-low)
|
||||
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
|
||||
* NMI style interrupts in future (say perf)
|
||||
*
|
||||
* Read the intc BCR to confirm that Linux default priority is avail
|
||||
* in h/w
|
||||
*
|
||||
* Note:
|
||||
* IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
|
||||
* is 0 based.
|
||||
*/
|
||||
tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
|
||||
if (ARCV2_IRQ_DEF_PRIO > tmp)
|
||||
panic("Linux default irq prio incorrect\n");
|
||||
|
||||
READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
|
||||
|
||||
irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
|
||||
pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
|
||||
irq_prio + 1, irq_prio,
|
||||
irq_bcr.firq ? " FIRQ (not used)":"");
|
||||
|
||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||
tmp = read_aux_reg(0xa);
|
||||
tmp |= STATUS_AD_MASK | (irq_prio << 1);
|
||||
tmp &= ~STATUS_IE_MASK;
|
||||
asm volatile("flag %0 \n"::"r"(tmp));
|
||||
}
|
||||
|
||||
static void arcv2_irq_mask(struct irq_data *data)
|
||||
|
@ -86,7 +93,7 @@ void arcv2_irq_enable(struct irq_data *data)
|
|||
{
|
||||
/* set default priority */
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, irq_prio);
|
||||
|
||||
/*
|
||||
* hw auto enables (linux unmask) all by default
|
||||
|
|
|
@ -81,9 +81,6 @@ static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
|
|||
{
|
||||
switch (irq) {
|
||||
case TIMER0_IRQ:
|
||||
#ifdef CONFIG_SMP
|
||||
case IPI_IRQ:
|
||||
#endif
|
||||
irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -11,9 +11,13 @@
|
|||
#include <linux/smp.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/irqflags-arcv2.h>
|
||||
#include <asm/mcip.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#define IPI_IRQ 19
|
||||
#define SOFTIRQ_IRQ 21
|
||||
|
||||
static char smp_cpuinfo_buf[128];
|
||||
static int idu_detected;
|
||||
|
||||
|
@ -22,6 +26,7 @@ static DEFINE_RAW_SPINLOCK(mcip_lock);
|
|||
static void mcip_setup_per_cpu(int cpu)
|
||||
{
|
||||
smp_ipi_irq_setup(cpu, IPI_IRQ);
|
||||
smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
|
||||
}
|
||||
|
||||
static void mcip_ipi_send(int cpu)
|
||||
|
@ -29,46 +34,44 @@ static void mcip_ipi_send(int cpu)
|
|||
unsigned long flags;
|
||||
int ipi_was_pending;
|
||||
|
||||
/* ARConnect can only send IPI to others */
|
||||
if (unlikely(cpu == raw_smp_processor_id())) {
|
||||
arc_softirq_trigger(SOFTIRQ_IRQ);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
|
||||
/*
|
||||
* NOTE: We must spin here if the other cpu hasn't yet
|
||||
* serviced a previous message. This can burn lots
|
||||
* of time, but we MUST follows this protocol or
|
||||
* ipi messages can be lost!!!
|
||||
* Also, we must release the lock in this loop because
|
||||
* the other side may get to this same loop and not
|
||||
* be able to ack -- thus causing deadlock.
|
||||
* If receiver already has a pending interrupt, elide sending this one.
|
||||
* Linux cross core calling works well with concurrent IPIs
|
||||
* coalesced into one
|
||||
* see arch/arc/kernel/smp.c: ipi_send_msg_one()
|
||||
*/
|
||||
__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
|
||||
ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
if (!ipi_was_pending)
|
||||
__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
|
||||
|
||||
do {
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
|
||||
ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
if (ipi_was_pending == 0)
|
||||
break; /* break out but keep lock */
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
} while (1);
|
||||
|
||||
__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
|
||||
#ifdef CONFIG_ARC_IPI_DBG
|
||||
if (ipi_was_pending)
|
||||
pr_info("IPI ACK delayed from cpu %d\n", cpu);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void mcip_ipi_clear(int irq)
|
||||
{
|
||||
unsigned int cpu, c;
|
||||
unsigned long flags;
|
||||
unsigned int __maybe_unused copy;
|
||||
|
||||
if (unlikely(irq == SOFTIRQ_IRQ)) {
|
||||
arc_softirq_clear(irq);
|
||||
return;
|
||||
}
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
|
||||
/* Who sent the IPI */
|
||||
__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
|
||||
|
||||
copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
|
||||
cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
|
||||
|
||||
/*
|
||||
* In rare case, multiple concurrent IPIs sent to same target can
|
||||
|
@ -82,12 +85,6 @@ static void mcip_ipi_clear(int irq)
|
|||
} while (cpu);
|
||||
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
|
||||
#ifdef CONFIG_ARC_IPI_DBG
|
||||
if (c != __ffs(copy))
|
||||
pr_info("IPIs from %x coalesced to %x\n",
|
||||
copy, raw_smp_processor_id());
|
||||
#endif
|
||||
}
|
||||
|
||||
static void mcip_probe_n_setup(void)
|
||||
|
@ -96,13 +93,13 @@ static void mcip_probe_n_setup(void)
|
|||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad3:8,
|
||||
idu:1, llm:1, num_cores:6,
|
||||
iocoh:1, grtc:1, dbg:1, pad2:1,
|
||||
iocoh:1, gfrc:1, dbg:1, pad2:1,
|
||||
msg:1, sem:1, ipi:1, pad:1,
|
||||
ver:8;
|
||||
#else
|
||||
unsigned int ver:8,
|
||||
pad:1, ipi:1, sem:1, msg:1,
|
||||
pad2:1, dbg:1, grtc:1, iocoh:1,
|
||||
pad2:1, dbg:1, gfrc:1, iocoh:1,
|
||||
num_cores:6, llm:1, idu:1,
|
||||
pad3:8;
|
||||
#endif
|
||||
|
@ -111,12 +108,13 @@ static void mcip_probe_n_setup(void)
|
|||
READ_BCR(ARC_REG_MCIP_BCR, mp);
|
||||
|
||||
sprintf(smp_cpuinfo_buf,
|
||||
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
|
||||
"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n",
|
||||
mp.ver, mp.num_cores,
|
||||
IS_AVAIL1(mp.ipi, "IPI "),
|
||||
IS_AVAIL1(mp.idu, "IDU "),
|
||||
IS_AVAIL1(mp.llm, "LLM "),
|
||||
IS_AVAIL1(mp.dbg, "DEBUG "),
|
||||
IS_AVAIL1(mp.grtc, "GRTC"));
|
||||
IS_AVAIL1(mp.gfrc, "GFRC"));
|
||||
|
||||
idu_detected = mp.idu;
|
||||
|
||||
|
@ -125,8 +123,8 @@ static void mcip_probe_n_setup(void)
|
|||
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
|
||||
panic("kernel trying to use non-existent GRTC\n");
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
|
||||
panic("kernel trying to use non-existent GFRC\n");
|
||||
}
|
||||
|
||||
struct plat_smp_ops plat_smp_ops = {
|
||||
|
|
|
@ -42,9 +42,57 @@ struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
|
|||
|
||||
struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
|
||||
|
||||
static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
|
||||
{
|
||||
if (is_isa_arcompact()) {
|
||||
struct bcr_iccm_arcompact iccm;
|
||||
struct bcr_dccm_arcompact dccm;
|
||||
|
||||
READ_BCR(ARC_REG_ICCM_BUILD, iccm);
|
||||
if (iccm.ver) {
|
||||
cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
|
||||
cpu->iccm.base_addr = iccm.base << 16;
|
||||
}
|
||||
|
||||
READ_BCR(ARC_REG_DCCM_BUILD, dccm);
|
||||
if (dccm.ver) {
|
||||
unsigned long base;
|
||||
cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
|
||||
|
||||
base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
|
||||
cpu->dccm.base_addr = base & ~0xF;
|
||||
}
|
||||
} else {
|
||||
struct bcr_iccm_arcv2 iccm;
|
||||
struct bcr_dccm_arcv2 dccm;
|
||||
unsigned long region;
|
||||
|
||||
READ_BCR(ARC_REG_ICCM_BUILD, iccm);
|
||||
if (iccm.ver) {
|
||||
cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
|
||||
if (iccm.sz00 == 0xF && iccm.sz01 > 0)
|
||||
cpu->iccm.sz <<= iccm.sz01;
|
||||
|
||||
region = read_aux_reg(ARC_REG_AUX_ICCM);
|
||||
cpu->iccm.base_addr = region & 0xF0000000;
|
||||
}
|
||||
|
||||
READ_BCR(ARC_REG_DCCM_BUILD, dccm);
|
||||
if (dccm.ver) {
|
||||
cpu->dccm.sz = 256 << dccm.sz0;
|
||||
if (dccm.sz0 == 0xF && dccm.sz1 > 0)
|
||||
cpu->dccm.sz <<= dccm.sz1;
|
||||
|
||||
region = read_aux_reg(ARC_REG_AUX_DCCM);
|
||||
cpu->dccm.base_addr = region & 0xF0000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void read_arc_build_cfg_regs(void)
|
||||
{
|
||||
struct bcr_perip uncached_space;
|
||||
struct bcr_timer timer;
|
||||
struct bcr_generic bcr;
|
||||
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
|
||||
unsigned long perip_space;
|
||||
|
@ -53,7 +101,11 @@ static void read_arc_build_cfg_regs(void)
|
|||
READ_BCR(AUX_IDENTITY, cpu->core);
|
||||
READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
|
||||
|
||||
READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
|
||||
READ_BCR(ARC_REG_TIMERS_BCR, timer);
|
||||
cpu->extn.timer0 = timer.t0;
|
||||
cpu->extn.timer1 = timer.t1;
|
||||
cpu->extn.rtc = timer.rtc;
|
||||
|
||||
cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
|
||||
|
||||
READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
|
||||
|
@ -71,36 +123,11 @@ static void read_arc_build_cfg_regs(void)
|
|||
cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
|
||||
cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
|
||||
cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
|
||||
|
||||
/* Note that we read the CCM BCRs independent of kernel config
|
||||
* This is to catch the cases where user doesn't know that
|
||||
* CCMs are present in hardware build
|
||||
*/
|
||||
{
|
||||
struct bcr_iccm iccm;
|
||||
struct bcr_dccm dccm;
|
||||
struct bcr_dccm_base dccm_base;
|
||||
unsigned int bcr_32bit_val;
|
||||
|
||||
bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR);
|
||||
if (bcr_32bit_val) {
|
||||
iccm = *((struct bcr_iccm *)&bcr_32bit_val);
|
||||
cpu->iccm.base_addr = iccm.base << 16;
|
||||
cpu->iccm.sz = 0x2000 << (iccm.sz - 1);
|
||||
}
|
||||
|
||||
bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR);
|
||||
if (bcr_32bit_val) {
|
||||
dccm = *((struct bcr_dccm *)&bcr_32bit_val);
|
||||
cpu->dccm.sz = 0x800 << (dccm.sz);
|
||||
|
||||
READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base);
|
||||
cpu->dccm.base_addr = dccm_base.addr << 8;
|
||||
}
|
||||
}
|
||||
|
||||
READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
|
||||
|
||||
/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
|
||||
read_decode_ccm_bcr(cpu);
|
||||
|
||||
read_decode_mmu_bcr();
|
||||
read_decode_cache_bcr();
|
||||
|
||||
|
@ -208,9 +235,9 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
|
|||
(unsigned int)(arc_get_core_freq() / 10000) % 100);
|
||||
|
||||
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
|
||||
IS_AVAIL1(cpu->timers.t0, "Timer0 "),
|
||||
IS_AVAIL1(cpu->timers.t1, "Timer1 "),
|
||||
IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
|
||||
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
|
||||
IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
|
||||
IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
|
||||
CONFIG_ARC_HAS_RTC));
|
||||
|
||||
n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
|
||||
|
@ -232,8 +259,6 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
|
|||
|
||||
n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
|
||||
}
|
||||
n += scnprintf(buf + n, len - n, "%s",
|
||||
IS_USED_CFG(CONFIG_ARC_HAS_HW_MPY));
|
||||
}
|
||||
|
||||
n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
|
||||
|
@ -293,13 +318,13 @@ static void arc_chk_core_config(void)
|
|||
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
|
||||
int fpu_enabled;
|
||||
|
||||
if (!cpu->timers.t0)
|
||||
if (!cpu->extn.timer0)
|
||||
panic("Timer0 is not present!\n");
|
||||
|
||||
if (!cpu->timers.t1)
|
||||
if (!cpu->extn.timer1)
|
||||
panic("Timer1 is not present!\n");
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
|
||||
panic("RTC is not present\n");
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_DCCM
|
||||
|
@ -334,6 +359,7 @@ static void arc_chk_core_config(void)
|
|||
panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
|
||||
|
||||
if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic &&
|
||||
IS_ENABLED(CONFIG_ARC_HAS_LLSC) &&
|
||||
!IS_ENABLED(CONFIG_ARC_STAR_9000923308))
|
||||
panic("llock/scond livelock workaround missing\n");
|
||||
}
|
||||
|
|
|
@ -336,11 +336,8 @@ irqreturn_t do_IPI(int irq, void *dev_id)
|
|||
int rc;
|
||||
|
||||
rc = __do_IPI(msg);
|
||||
#ifdef CONFIG_ARC_IPI_DBG
|
||||
/* IPI received but no valid @msg */
|
||||
if (rc)
|
||||
pr_info("IPI with bogus msg %ld in %ld\n", msg, copy);
|
||||
#endif
|
||||
pending &= ~(1U << msg);
|
||||
} while (pending);
|
||||
|
||||
|
|
|
@ -62,7 +62,7 @@
|
|||
|
||||
/********** Clock Source Device *********/
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_GRTC
|
||||
#ifdef CONFIG_ARC_HAS_GFRC
|
||||
|
||||
static int arc_counter_setup(void)
|
||||
{
|
||||
|
@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
|||
|
||||
local_irq_save(flags);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_LO, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_LO, 0);
|
||||
stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_HI, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_HI, 0);
|
||||
stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
|||
}
|
||||
|
||||
static struct clocksource arc_counter = {
|
||||
.name = "ARConnect GRTC",
|
||||
.name = "ARConnect GFRC",
|
||||
.rating = 400,
|
||||
.read = arc_counter_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
|
|
|
@ -195,5 +195,7 @@ CFLAGS_font.o := -Dstatic=
|
|||
$(obj)/font.c: $(FONTC)
|
||||
$(call cmd,shipped)
|
||||
|
||||
AFLAGS_hyp-stub.o := -Wa,-march=armv7-a
|
||||
|
||||
$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S
|
||||
$(call cmd,shipped)
|
||||
|
|
|
@ -285,8 +285,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
/*
|
||||
* Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
|
||||
* mode") at poweroff. Most BeagleBone versions do not support RTC-only
|
||||
|
@ -307,17 +309,12 @@
|
|||
ti,pmic-shutdown-controller;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-name = "vdds_dpr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -327,7 +324,6 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -337,25 +333,21 @@
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-name = "vio,vrtc,vdds";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-name = "vdd_1v8";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-name = "vdd_3v3a";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
@ -128,21 +128,16 @@
|
|||
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-name = "vdds_dpr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -152,7 +147,6 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -162,28 +156,24 @@
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-name = "vio,vrtc,vdds";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-name = "vdd_1v8";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-name = "vdd_3v3d";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
|
|
|
@ -375,15 +375,11 @@
|
|||
wp-gpios = <&gpio3 18 0>;
|
||||
};
|
||||
|
||||
#include "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
/* +1.5V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1450000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
|
@ -392,7 +388,6 @@
|
|||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <915000>;
|
||||
|
@ -402,7 +397,6 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <915000>;
|
||||
|
@ -412,7 +406,6 @@
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
|
@ -421,7 +414,6 @@
|
|||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
|
@ -430,7 +422,6 @@
|
|||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
|
@ -439,7 +430,6 @@
|
|||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
|
|
|
@ -420,9 +420,9 @@
|
|||
vin-supply = <&vbat>;
|
||||
};
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
backlight {
|
||||
isel = <1>; /* ISET1 */
|
||||
fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
|
||||
|
@ -430,17 +430,12 @@
|
|||
};
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
/* VDD_1V8 system supply */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -450,7 +445,6 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -460,21 +454,18 @@
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
/* VRTC 1.8V always-on supply */
|
||||
regulator-name = "vrtc,vdds";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
/* 3.3V rail */
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
/* VDD_3V3A 3.3V rail */
|
||||
regulator-name = "vdd_3v3a";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
@ -482,7 +473,6 @@
|
|||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
/* VDD_3V3B 3.3V rail */
|
||||
regulator-name = "vdd_3v3b";
|
||||
regulator-always-on;
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_BACK>;
|
||||
debounce-interval = <1000>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
front_button {
|
||||
|
@ -54,7 +54,7 @@
|
|||
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_FRONT>;
|
||||
debounce-interval = <1000>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -375,19 +375,16 @@
|
|||
pinctrl-0 = <&uart4_pins>;
|
||||
};
|
||||
|
||||
#include "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
ti,pmic-shutdown-controller;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <7>; /* NNMI */
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
/* VDDS_DDR */
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
@ -395,7 +392,6 @@
|
|||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -405,7 +401,6 @@
|
|||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
|
@ -415,7 +410,6 @@
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
/* VRTC / VIO / VDDS*/
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
|
@ -423,7 +417,6 @@
|
|||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
/* VDD_3V3AUX */
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
@ -431,7 +424,6 @@
|
|||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
/* VDD_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
@ -439,7 +431,6 @@
|
|||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
/* VDD_3V3A */
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
|
|
@ -173,6 +173,8 @@
|
|||
|
||||
sound0_master: simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic3104>;
|
||||
assigned-clocks = <&clkoutmux2_clk_mux>;
|
||||
assigned-clock-parents = <&sys_clk2_dclk_div>;
|
||||
clocks = <&clkout2_clk>;
|
||||
};
|
||||
};
|
||||
|
@ -796,6 +798,8 @@
|
|||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mcasp3_pins_default>;
|
||||
pinctrl-1 = <&mcasp3_pins_sleep>;
|
||||
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
||||
assigned-clock-parents = <&sys_clkin2>;
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
|
|
|
@ -545,7 +545,7 @@
|
|||
ti,debounce-tol = /bits/ 16 <10>;
|
||||
ti,debounce-rep = /bits/ 16 <1>;
|
||||
|
||||
linux,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -70,8 +70,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
|
@ -76,8 +76,8 @@
|
|||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
|
|
@ -95,8 +95,8 @@
|
|||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
|
|
@ -65,8 +65,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
|
@ -70,8 +70,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
|
@ -68,8 +68,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
|
|
|
@ -64,8 +64,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
|
@ -65,9 +65,9 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
|
|
@ -78,8 +78,8 @@
|
|||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
|
||||
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
|
@ -1500,6 +1500,16 @@
|
|||
0x48485200 0x2E00>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Do not allow gating of cpsw clock as workaround
|
||||
* for errata i877. Keeping internal clock disabled
|
||||
* causes the device switching characteristics
|
||||
* to degrade over time and eventually fail to meet
|
||||
* the data manual delay time/skew specs.
|
||||
*/
|
||||
ti,no-idle;
|
||||
|
||||
/*
|
||||
* rx_thresh_pend
|
||||
* rx_pend
|
||||
|
|
|
@ -896,7 +896,6 @@
|
|||
#size-cells = <1>;
|
||||
reg = <0x2100000 0x10000>;
|
||||
ranges = <0 0x2100000 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
|
||||
<&clks IMX6QDL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6QDL_CLK_CAAM_IPG>,
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
#include "kirkwood-synology.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Synology DS111";
|
||||
model = "Synology DS112";
|
||||
compatible = "synology,ds111", "marvell,kirkwood";
|
||||
|
||||
memory {
|
||||
|
|
|
@ -228,6 +228,37 @@
|
|||
};
|
||||
};
|
||||
|
||||
&devbus_bootcs {
|
||||
status = "okay";
|
||||
devbus,keep-config;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec-flash";
|
||||
reg = <0 0x40000>;
|
||||
bank-width = <1>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
header@0 {
|
||||
reg = <0 0x30000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
uboot@30000 {
|
||||
reg = <0x30000 0xF000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
uboot_env@3F000 {
|
||||
reg = <0x3F000 0x1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
@ -283,7 +283,6 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
|
|
|
@ -90,7 +90,7 @@
|
|||
#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2)
|
||||
#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1)
|
||||
#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2)
|
||||
#define PIN_PA15 14
|
||||
#define PIN_PA15 15
|
||||
#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0)
|
||||
#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1)
|
||||
#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1)
|
||||
|
|
56
arch/arm/boot/dts/tps65217.dtsi
Normal file
56
arch/arm/boot/dts/tps65217.dtsi
Normal file
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Integrated Power Management Chip
|
||||
* http://www.ti.com/lit/ds/symlink/tps65217.pdf
|
||||
*/
|
||||
|
||||
&tps {
|
||||
compatible = "ti,tps65217";
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dcdc1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "dcdc1";
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "dcdc2";
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "dcdc3";
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "ldo1";
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo2";
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo3";
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo4";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -16,7 +16,7 @@
|
|||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
#include <asm/hardware/icst.h>
|
||||
|
||||
/*
|
||||
|
@ -29,7 +29,11 @@ EXPORT_SYMBOL(icst525_s2div);
|
|||
|
||||
unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
|
||||
{
|
||||
return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]);
|
||||
u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
|
||||
u32 divisor = (vco.r + 2) * p->s2div[vco.s];
|
||||
|
||||
do_div(dividend, divisor);
|
||||
return (unsigned long)dividend;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(icst_hz);
|
||||
|
@ -58,6 +62,7 @@ icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
|
|||
|
||||
if (f > p->vco_min && f <= p->vco_max)
|
||||
break;
|
||||
i++;
|
||||
} while (i < 8);
|
||||
|
||||
if (i >= 8)
|
||||
|
|
|
@ -292,24 +292,23 @@ CONFIG_FB=y
|
|||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_TILEBLITTING=y
|
||||
CONFIG_OMAP2_DSS=m
|
||||
CONFIG_OMAP5_DSS_HDMI=y
|
||||
CONFIG_OMAP2_DSS_SDI=y
|
||||
CONFIG_OMAP2_DSS_DSI=y
|
||||
CONFIG_FB_OMAP5_DSS_HDMI=y
|
||||
CONFIG_FB_OMAP2_DSS_SDI=y
|
||||
CONFIG_FB_OMAP2_DSS_DSI=y
|
||||
CONFIG_FB_OMAP2=m
|
||||
CONFIG_DISPLAY_ENCODER_TFP410=m
|
||||
CONFIG_DISPLAY_ENCODER_TPD12S015=m
|
||||
CONFIG_DISPLAY_CONNECTOR_DVI=m
|
||||
CONFIG_DISPLAY_CONNECTOR_HDMI=m
|
||||
CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
|
||||
CONFIG_DISPLAY_PANEL_DPI=m
|
||||
CONFIG_DISPLAY_PANEL_DSI_CM=m
|
||||
CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
|
||||
CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_FB_OMAP2_ENCODER_TFP410=m
|
||||
CONFIG_FB_OMAP2_ENCODER_TPD12S015=m
|
||||
CONFIG_FB_OMAP2_CONNECTOR_DVI=m
|
||||
CONFIG_FB_OMAP2_CONNECTOR_HDMI=m
|
||||
CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m
|
||||
CONFIG_FB_OMAP2_PANEL_DPI=m
|
||||
CONFIG_FB_OMAP2_PANEL_DSI_CM=m
|
||||
CONFIG_FB_OMAP2_PANEL_SONY_ACX565AKM=m
|
||||
CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02=m
|
||||
CONFIG_FB_OMAP2_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_FB_OMAP2_PANEL_TPO_TD028TTEC1=m
|
||||
CONFIG_FB_OMAP2_PANEL_TPO_TD043MTEA1=m
|
||||
CONFIG_FB_OMAP2_PANEL_NEC_NL8048HL11=m
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_LCD_PLATFORM=y
|
||||
|
|
|
@ -364,7 +364,7 @@ static struct crypto_alg aes_algs[] = { {
|
|||
.cra_blkcipher = {
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
.ivsize = 0,
|
||||
.setkey = ce_aes_setkey,
|
||||
.encrypt = ecb_encrypt,
|
||||
.decrypt = ecb_decrypt,
|
||||
|
@ -441,7 +441,7 @@ static struct crypto_alg aes_algs[] = { {
|
|||
.cra_ablkcipher = {
|
||||
.min_keysize = AES_MIN_KEY_SIZE,
|
||||
.max_keysize = AES_MAX_KEY_SIZE,
|
||||
.ivsize = AES_BLOCK_SIZE,
|
||||
.ivsize = 0,
|
||||
.setkey = ablk_set_key,
|
||||
.encrypt = ablk_encrypt,
|
||||
.decrypt = ablk_decrypt,
|
||||
|
|
|
@ -117,6 +117,7 @@ static inline u32 gic_read_iar(void)
|
|||
u32 irqstat;
|
||||
|
||||
asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));
|
||||
dsb(sy);
|
||||
return irqstat;
|
||||
}
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue