sh: Rework SuperH Mobile sleep mode code
Rework the SuperH Mobile sleep code from including board specific code to allowing each board to provide pre/post code snippets. These snippets should contain sdram management code to enter and leave self-refresh. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
eb0cd9e88c
commit
323ef8dba6
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@ -34,6 +34,33 @@ extern struct atomic_notifier_head sh_mobile_post_sleep_notifier_list;
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void sh_mobile_register_self_refresh(unsigned long flags,
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void *pre_start, void *pre_end,
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void *post_start, void *post_end);
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/* register structure for address/data information */
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struct sh_sleep_regs {
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unsigned long stbcr;
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};
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/* data area for low-level sleep code */
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struct sh_sleep_data {
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/* current sleep mode (SUSP_SH_...) */
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unsigned long mode;
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/* addresses of board specific self-refresh snippets */
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unsigned long sf_pre;
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unsigned long sf_post;
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/* register state saved and restored by the assembly code */
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unsigned long vbr;
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unsigned long spc;
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unsigned long sr;
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/* structure for keeping register addresses */
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struct sh_sleep_regs addr;
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/* structure for saving/restoring register state */
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struct sh_sleep_regs data;
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};
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#endif
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/* flags passed to assembly suspend code */
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@ -34,5 +34,15 @@ int main(void)
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DEFINE(PBE_NEXT, offsetof(struct pbe, next));
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DEFINE(SWSUSP_ARCH_REGS_SIZE, sizeof(struct swsusp_arch_regs));
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#endif
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DEFINE(SH_SLEEP_MODE, offsetof(struct sh_sleep_data, mode));
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DEFINE(SH_SLEEP_SF_PRE, offsetof(struct sh_sleep_data, sf_pre));
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DEFINE(SH_SLEEP_SF_POST, offsetof(struct sh_sleep_data, sf_post));
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DEFINE(SH_SLEEP_VBR, offsetof(struct sh_sleep_data, vbr));
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DEFINE(SH_SLEEP_SPC, offsetof(struct sh_sleep_data, spc));
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DEFINE(SH_SLEEP_SR, offsetof(struct sh_sleep_data, sr));
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DEFINE(SH_SLEEP_BASE_ADDR, offsetof(struct sh_sleep_data, addr));
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DEFINE(SH_SLEEP_BASE_DATA, offsetof(struct sh_sleep_data, data));
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DEFINE(SH_SLEEP_REG_STBCR, offsetof(struct sh_sleep_regs, stbcr));
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return 0;
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}
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@ -42,13 +42,14 @@ ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
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#define ILRAM_BASE 0xe5200000
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extern const unsigned char sh_mobile_standby[];
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extern const unsigned int sh_mobile_standby_size;
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void sh_mobile_call_standby(unsigned long mode)
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{
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void *onchip_mem = (void *)ILRAM_BASE;
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void (*standby_onchip_mem)(unsigned long, unsigned long) = onchip_mem;
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struct sh_sleep_data *sdp = onchip_mem;
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void (*standby_onchip_mem)(unsigned long, unsigned long);
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/* code located directly after data structure */
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standby_onchip_mem = (void *)(sdp + 1);
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atomic_notifier_call_chain(&sh_mobile_pre_sleep_notifier_list,
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mode, NULL);
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@ -60,10 +61,48 @@ void sh_mobile_call_standby(unsigned long mode)
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mode, NULL);
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}
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extern char sh_mobile_sleep_enter_start;
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extern char sh_mobile_sleep_enter_end;
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extern char sh_mobile_sleep_resume_start;
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extern char sh_mobile_sleep_resume_end;
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void sh_mobile_register_self_refresh(unsigned long flags,
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void *pre_start, void *pre_end,
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void *post_start, void *post_end)
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{
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void *onchip_mem = (void *)ILRAM_BASE;
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void *vp;
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struct sh_sleep_data *sdp;
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int n;
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/* part 0: data area */
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sdp = onchip_mem;
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sdp->addr.stbcr = 0xa4150020; /* STBCR */
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vp = sdp + 1;
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/* part 1: common code to enter sleep mode */
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n = &sh_mobile_sleep_enter_end - &sh_mobile_sleep_enter_start;
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memcpy(vp, &sh_mobile_sleep_enter_start, n);
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vp += roundup(n, 4);
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/* part 2: board specific code to enter self-refresh mode */
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n = pre_end - pre_start;
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memcpy(vp, pre_start, n);
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sdp->sf_pre = (unsigned long)vp;
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vp += roundup(n, 4);
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/* part 3: board specific code to resume from self-refresh mode */
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n = post_end - post_start;
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memcpy(vp, post_start, n);
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sdp->sf_post = (unsigned long)vp;
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vp += roundup(n, 4);
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/* part 4: common code to resume from sleep mode */
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WARN_ON(vp > (onchip_mem + 0x600));
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vp = onchip_mem + 0x600; /* located at interrupt vector */
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n = &sh_mobile_sleep_resume_end - &sh_mobile_sleep_resume_start;
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memcpy(vp, &sh_mobile_sleep_resume_start, n);
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}
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static int sh_pm_enter(suspend_state_t state)
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@ -83,13 +122,6 @@ static struct platform_suspend_ops sh_pm_ops = {
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static int __init sh_pm_init(void)
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{
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void *onchip_mem = (void *)ILRAM_BASE;
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/* Copy the assembly snippet to the otherwise ununsed ILRAM */
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memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
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wmb();
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ctrl_barrier();
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suspend_set_ops(&sh_pm_ops);
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sh_mobile_setup_cpuidle();
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return 0;
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@ -20,79 +20,49 @@
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* Kernel mode register usage, see entry.S:
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* k0 scratch
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* k1 scratch
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* k4 scratch
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*/
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#define k0 r0
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#define k1 r1
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#define k4 r4
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/* manage self-refresh and enter standby mode.
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/* manage self-refresh and enter standby mode. must be self-contained.
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* this code will be copied to on-chip memory and executed from there.
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*/
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.balign 4
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ENTRY(sh_mobile_sleep_enter_start)
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.balign 4096,0,4096
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ENTRY(sh_mobile_standby)
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/* save mode flags */
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mov.l r4, @(SH_SLEEP_MODE, r5)
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/* save original vbr */
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stc vbr, r1
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mova saved_vbr, r0
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mov.l r1, @r0
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stc vbr, r0
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mov.l r0, @(SH_SLEEP_VBR, r5)
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/* point vbr to our on-chip memory page */
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ldc r5, vbr
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/* save return address */
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mova saved_spc, r0
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sts pr, r5
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mov.l r5, @r0
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sts pr, r0
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mov.l r0, @(SH_SLEEP_SPC, r5)
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/* save sr */
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mova saved_sr, r0
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stc sr, r5
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mov.l r5, @r0
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stc sr, r0
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mov.l r0, @(SH_SLEEP_SR, r5)
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/* save mode flags */
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mova saved_mode, r0
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mov.l r4, @r0
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/* put mode flags in r0 */
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mov r4, r0
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/* save stbcr */
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bsr save_register
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mov #SH_SLEEP_REG_STBCR, r0
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/* call self-refresh entering code if needed */
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mov.l @(SH_SLEEP_MODE, r5), r0
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tst #SUSP_SH_SF, r0
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bt skip_set_sf
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#ifdef CONFIG_CPU_SUBTYPE_SH7724
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/* DBSC: put memory in self-refresh mode */
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mov.l dben_reg, r4
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mov.l dben_data0, r1
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mov.l r1, @r4
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mov.l dbrfpdn0_reg, r4
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mov.l dbrfpdn0_data0, r1
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mov.l r1, @r4
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mov.l dbcmdcnt_reg, r4
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mov.l dbcmdcnt_data0, r1
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mov.l r1, @r4
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mov.l dbcmdcnt_reg, r4
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mov.l dbcmdcnt_data1, r1
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mov.l r1, @r4
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mov.l dbrfpdn0_reg, r4
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mov.l dbrfpdn0_data1, r1
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mov.l r1, @r4
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#else
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/* SBSC: disable power down and put in self-refresh mode */
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mov.l 1f, r4
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mov.l 2f, r1
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mov.l @r4, r2
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or r1, r2
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mov.l 3f, r3
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and r3, r2
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mov.l r2, @r4
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#endif
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mov.l @(SH_SLEEP_SF_PRE, r5), r0
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jsr @r0
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nop
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skip_set_sf:
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mov.l @(SH_SLEEP_MODE, r5), r0
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tst #SUSP_SH_STANDBY, r0
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bt test_rstandby
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@ -123,124 +93,92 @@ force_sleep:
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do_sleep:
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/* setup and enter selected standby mode */
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mov.l 5f, r4
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mov.l r1, @r4
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bsr get_register
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mov #SH_SLEEP_REG_STBCR, r0
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mov.l r1, @r0
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again:
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sleep
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bra again
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nop
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restore_jump_vbr:
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save_register:
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add #SH_SLEEP_BASE_ADDR, r0
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mov.l @(r0, r5), r1
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add #-SH_SLEEP_BASE_ADDR, r0
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mov.l @r1, r1
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add #SH_SLEEP_BASE_DATA, r0
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mov.l r1, @(r0, r5)
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add #-SH_SLEEP_BASE_DATA, r0
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rts
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nop
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get_register:
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add #SH_SLEEP_BASE_ADDR, r0
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mov.l @(r0, r5), r0
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rts
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nop
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ENTRY(sh_mobile_sleep_enter_end)
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.balign 4
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ENTRY(sh_mobile_sleep_resume_start)
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/* figure out start address */
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bsr 0f
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nop
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0:
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sts pr, k1
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mov.l 1f, k0
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and k0, k1
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/* store pointer to data area in VBR */
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ldc k1, vbr
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/* setup sr with saved sr */
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mov.l @(SH_SLEEP_SR, k1), k0
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ldc k0, sr
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/* now: user register set! */
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stc vbr, r5
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/* setup spc with return address to c code */
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mov.l saved_spc, k0
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ldc k0, spc
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mov.l @(SH_SLEEP_SPC, r5), r0
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ldc r0, spc
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/* restore vbr */
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mov.l saved_vbr, k0
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ldc k0, vbr
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mov.l @(SH_SLEEP_VBR, r5), r0
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ldc r0, vbr
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/* setup ssr with saved sr */
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mov.l saved_sr, k0
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ldc k0, ssr
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mov.l @(SH_SLEEP_SR, r5), r0
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ldc r0, ssr
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/* get mode flags */
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mov.l saved_mode, k0
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/* restore sleep mode register */
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bsr restore_register
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mov #SH_SLEEP_REG_STBCR, r0
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done_sleep:
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/* reset standby mode to sleep mode */
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mov.l 5f, k4
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mov #0x00, k1
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mov.l k1, @k4
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tst #SUSP_SH_SF, k0
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/* call self-refresh resume code if needed */
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mov.l @(SH_SLEEP_MODE, r5), r0
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tst #SUSP_SH_SF, r0
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bt skip_restore_sf
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#ifdef CONFIG_CPU_SUBTYPE_SH7724
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/* DBSC: put memory in auto-refresh mode */
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mov.l dbrfpdn0_reg, k4
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mov.l dbrfpdn0_data0, k1
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mov.l k1, @k4
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mov.l @(SH_SLEEP_SF_POST, r5), r0
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jsr @r0
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nop
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nop /* sleep 140 ns */
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nop
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nop
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nop
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mov.l dbcmdcnt_reg, k4
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mov.l dbcmdcnt_data0, k1
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mov.l k1, @k4
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mov.l dbcmdcnt_reg, k4
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mov.l dbcmdcnt_data1, k1
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mov.l k1, @k4
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mov.l dben_reg, k4
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mov.l dben_data1, k1
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mov.l k1, @k4
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mov.l dbrfpdn0_reg, k4
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mov.l dbrfpdn0_data2, k1
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mov.l k1, @k4
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#else
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/* SBSC: set auto-refresh mode */
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mov.l 1f, k4
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mov.l @k4, k0
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mov.l 4f, k1
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and k1, k0
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mov.l k0, @k4
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mov.l 6f, k4
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mov.l 8f, k0
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mov.l @k4, k1
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mov #-1, k4
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add k4, k1
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or k1, k0
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mov.l 7f, k1
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mov.l k0, @k1
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#endif
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skip_restore_sf:
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/* jump to vbr vector */
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mov.l saved_vbr, k0
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mov.l offset_vbr, k4
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add k4, k0
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jmp @k0
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rte
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nop
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restore_register:
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add #SH_SLEEP_BASE_DATA, r0
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mov.l @(r0, r5), r1
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add #-SH_SLEEP_BASE_DATA, r0
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add #SH_SLEEP_BASE_ADDR, r0
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mov.l @(r0, r5), r0
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mov.l r1, @r0
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rts
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nop
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.balign 4
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saved_mode: .long 0
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saved_spc: .long 0
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saved_sr: .long 0
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saved_vbr: .long 0
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offset_vbr: .long 0x600
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#ifdef CONFIG_CPU_SUBTYPE_SH7724
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dben_reg: .long 0xfd000010 /* DBEN */
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dben_data0: .long 0
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dben_data1: .long 1
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dbrfpdn0_reg: .long 0xfd000040 /* DBRFPDN0 */
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dbrfpdn0_data0: .long 0
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dbrfpdn0_data1: .long 1
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dbrfpdn0_data2: .long 0x00010000
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dbcmdcnt_reg: .long 0xfd000014 /* DBCMDCNT */
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dbcmdcnt_data0: .long 2
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dbcmdcnt_data1: .long 4
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#else
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1: .long 0xfe400008 /* SDCR0 */
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2: .long 0x00000400
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3: .long 0xffff7fff
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4: .long 0xfffffbff
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#endif
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5: .long 0xa4150020 /* STBCR */
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6: .long 0xfe40001c /* RTCOR */
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7: .long 0xfe400018 /* RTCNT */
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8: .long 0xa55a0000
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/* interrupt vector @ 0x600 */
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.balign 0x400,0,0x400
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.long 0xdeadbeef
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.balign 0x200,0,0x200
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bra restore_jump_vbr
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nop
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sh_mobile_standby_end:
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ENTRY(sh_mobile_standby_size)
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.long sh_mobile_standby_end - sh_mobile_standby
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1: .long ~0x7ff
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ENTRY(sh_mobile_sleep_resume_end)
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