Depends:
- Based against v3.7-rc1
- Latest changes to arch/arm/mm/cache-tauros2.c
c2b7e05 ARM: cache: add dt support for tauros2 cache
Misc. fixes for latest changes to mach-dove/
Fixes build breakage for mach-dove
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Merge tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper:
Misc. fixes for latest changes to mach-dove/
Fixes build breakage for mach-dove
* tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux:
ARM: dove: Add crypto engine to DT
ARM: dove: Remove watchdog from DT
ARM: dove: Restructure SoC device tree descriptor
ARM: dove: Fix clock names of sata and gbe
ARM: dove: Fix tauros2 device tree init
ARM: dove: Add pcie clock support
This commit is contained in:
Olof Johansson
commit
327f81c455
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@ -4,21 +4,32 @@
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compatible = "marvell,dove";
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model = "Marvell Armada 88AP510 SoC";
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interrupt-parent = <&intc>;
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intc: interrupt-controller {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xf1020204 0x04>,
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<0xf1020214 0x04>;
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};
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mbus@f1000000 {
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soc@f1000000 {
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compatible = "simple-bus";
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ranges = <0 0xf1000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
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0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
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0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
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0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
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0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
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0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
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0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
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0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
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l2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0>;
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};
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intc: interrupt-controller {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20204 0x04>, <0x20214 0x04>;
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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@ -56,11 +67,6 @@
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status = "disabled";
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};
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wdt: wdt@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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};
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gpio0: gpio@d0400 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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@ -139,5 +145,14 @@
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nr-ports = <1>;
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status = "disabled";
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};
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crypto: crypto@30000 {
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compatible = "marvell,orion-crypto";
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reg = <0x30000 0x10000>,
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<0xc8000000 0x800>;
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reg-names = "regs", "sram";
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interrupts = <31>;
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status = "okay";
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};
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};
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};
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@ -32,6 +32,7 @@
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#include <linux/irq.h>
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#include <plat/time.h>
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#include <linux/platform_data/usb-ehci-orion.h>
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#include <plat/irq.h>
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#include <plat/common.h>
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#include <plat/addr-map.h>
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#include "common.h"
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@ -109,8 +110,8 @@ static void __init dove_clk_init(void)
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orion_clkdev_add(NULL, "orion-ehci.0", usb0);
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orion_clkdev_add(NULL, "orion-ehci.1", usb1);
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orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
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orion_clkdev_add("0", "sata_mv.0", sata);
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orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
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orion_clkdev_add(NULL, "sata_mv.0", sata);
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orion_clkdev_add("0", "pcie", pex0);
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orion_clkdev_add("1", "pcie", pex1);
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orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
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@ -399,7 +400,7 @@ static void __init dove_dt_init(void)
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(dove_tclk + 499999) / 1000000);
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init();
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tauros2_init(0);
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#endif
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dove_setup_cpu_mbus();
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@ -415,7 +416,6 @@ static void __init dove_dt_init(void)
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dove_ehci0_init();
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dove_ehci1_init();
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dove_pcie_init(1, 1);
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dove_crypto_init();
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of_platform_populate(NULL, of_default_bus_match_table,
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dove_auxdata_lookup, NULL);
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@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <video/vga.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/arch.h>
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@ -188,6 +189,10 @@ static void __init add_pcie_port(int index, void __iomem *base)
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if (orion_pcie_link_up(base)) {
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struct pcie_port *pp = &pcie_port[num_pcie_ports++];
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struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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printk(KERN_INFO "link up\n");
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