drm/radeon/kms: add pcie get/set lane support for r6xx/r7xx/evergreen
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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f598aa7593
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3313e3d433
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@ -558,10 +558,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
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/* FIXME wait for idle */
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if (rdev->family < CHIP_R600)
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link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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else
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link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
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case RADEON_PCIE_LC_LINK_WIDTH_X0:
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@ -3531,3 +3531,121 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
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} else
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WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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}
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void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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{
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u32 link_width_cntl, mask, target_reg;
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if (rdev->flags & RADEON_IS_IGP)
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return;
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if (!(rdev->flags & RADEON_IS_PCIE))
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return;
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/* x2 cards have a special sequence */
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if (ASIC_IS_X2(rdev))
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return;
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/* FIXME wait for idle */
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switch (lanes) {
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case 0:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
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break;
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case 1:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
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break;
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case 2:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
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break;
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case 4:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
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break;
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case 8:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
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break;
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case 12:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
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break;
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case 16:
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default:
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mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
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break;
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}
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link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
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(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
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return;
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if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
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return;
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link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
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RADEON_PCIE_LC_RECONFIG_NOW |
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R600_PCIE_LC_RENEGOTIATE_EN |
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R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
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link_width_cntl |= mask;
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WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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/* some northbridges can renegotiate the link rather than requiring
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* a complete re-config.
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* e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
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*/
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if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
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link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
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else
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link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
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WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
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RADEON_PCIE_LC_RECONFIG_NOW));
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if (rdev->family >= CHIP_RV770)
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target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
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else
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target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
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/* wait for lane set to complete */
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link_width_cntl = RREG32(target_reg);
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while (link_width_cntl == 0xffffffff)
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link_width_cntl = RREG32(target_reg);
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}
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int r600_get_pcie_lanes(struct radeon_device *rdev)
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{
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u32 link_width_cntl;
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if (rdev->flags & RADEON_IS_IGP)
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return 0;
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if (!(rdev->flags & RADEON_IS_PCIE))
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return 0;
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/* x2 cards have a special sequence */
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if (ASIC_IS_X2(rdev))
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return 0;
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/* FIXME wait for idle */
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link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
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switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
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case RADEON_PCIE_LC_LINK_WIDTH_X0:
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return 0;
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case RADEON_PCIE_LC_LINK_WIDTH_X1:
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return 1;
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case RADEON_PCIE_LC_LINK_WIDTH_X2:
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return 2;
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case RADEON_PCIE_LC_LINK_WIDTH_X4:
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return 4;
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case RADEON_PCIE_LC_LINK_WIDTH_X8:
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return 8;
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case RADEON_PCIE_LC_LINK_WIDTH_X16:
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default:
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return 16;
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}
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}
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@ -1317,6 +1317,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
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(rdev->family == CHIP_RV410) || \
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(rdev->family == CHIP_RS400) || \
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(rdev->family == CHIP_RS480))
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#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
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(rdev->ddev->pdev->device == 0x9443) || \
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(rdev->ddev->pdev->device == 0x944B) || \
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(rdev->ddev->pdev->device == 0x9506) || \
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(rdev->ddev->pdev->device == 0x9509) || \
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(rdev->ddev->pdev->device == 0x950F) || \
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(rdev->ddev->pdev->device == 0x689C) || \
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(rdev->ddev->pdev->device == 0x689D))
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#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
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#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
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(rdev->family == CHIP_RS690) || \
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@ -94,7 +94,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
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if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_HEMLOCK)) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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}
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@ -631,8 +631,8 @@ static struct radeon_asic r600_asic = {
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = &rv370_get_pcie_lanes,
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.set_pcie_lanes = NULL,
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = NULL,
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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@ -725,8 +725,8 @@ static struct radeon_asic rv770_asic = {
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = &rv370_get_pcie_lanes,
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.set_pcie_lanes = NULL,
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = &radeon_atom_set_clock_gating,
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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@ -772,8 +772,8 @@ static struct radeon_asic evergreen_asic = {
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = NULL,
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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@ -284,6 +284,8 @@ extern void r600_pm_misc(struct radeon_device *rdev);
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extern void r600_pm_init_profile(struct radeon_device *rdev);
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extern void rs780_pm_init_profile(struct radeon_device *rdev);
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extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
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extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
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extern int r600_get_pcie_lanes(struct radeon_device *rdev);
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/*
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* rv770,rv730,rv710,rv740
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@ -320,6 +320,15 @@
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# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
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# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
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# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
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# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
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# define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)
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# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)
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# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)
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# define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)
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# define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)
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#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
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#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
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#define RADEON_CACHE_CNTL 0x1724
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#define RADEON_CACHE_LINE 0x0f0c /* PCI */
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