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spi: stm32: fix fifo threshold level in case of short transfer 

When transfer is shorter than half of the fifo, set the data packet size
up to transfer size instead of up to half of the fifo.
Check also that threshold is set at least to 1 data frame.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alain Volmat <alain.volmat@st.com>
Link: https://lore.kernel.org/r/1597043558-29668-3-git-send-email-alain.volmat@st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
zero-sugar-mainline-defconfig
Amelie Delaunay 2020-08-10 09:12:35 +02:00 committed by Mark Brown
parent 135dd873d3
commit 3373e9004a
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 20 additions and 10 deletions
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30
drivers/spi/spi-stm32.c
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@ -467,20 +467,27 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
/**
* stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
* @spi: pointer to the spi controller data structure
* @xfer_len: length of the message to be transferred
*/
static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
{
u32 fthlv, half_fifo;
u32 fthlv, half_fifo, packet;
/* data packet should not exceed 1/2 of fifo space */
half_fifo = (spi->fifo_size / 2);
if (spi->cur_bpw <= 8)
fthlv = half_fifo;
else if (spi->cur_bpw <= 16)
fthlv = half_fifo / 2;
/* data_packet should not exceed transfer length */
if (half_fifo > xfer_len)
packet = xfer_len;
else
fthlv = half_fifo / 4;
packet = half_fifo;
if (spi->cur_bpw <= 8)
fthlv = packet;
else if (spi->cur_bpw <= 16)
fthlv = packet / 2;
else
fthlv = packet / 4;
/* align packet size with data registers access */
if (spi->cur_bpw > 8)
@ -488,6 +495,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
else
fthlv -= (fthlv % 4); /* multiple of 4 */
if (!fthlv)
fthlv = 1;
return fthlv;
}
@ -1393,7 +1403,7 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
STM32H7_SPI_CFG1_DSIZE;
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
@ -1588,6 +1598,8 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
spin_lock_irqsave(&spi->lock, flags);
spi->cur_xferlen = transfer->len;
if (spi->cur_bpw != transfer->bits_per_word) {
spi->cur_bpw = transfer->bits_per_word;
spi->cfg->set_bpw(spi);
@ -1635,8 +1647,6 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
goto out;
}
spi->cur_xferlen = transfer->len;
dev_dbg(spi->dev, "transfer communication mode set to %d\n",
spi->cur_comm);
dev_dbg(spi->dev,