crypto: ccp - add TEE support for Raven Ridge
Adds a PCI device entry for Raven Ridge. Raven Ridge is an APU with a dedicated AMD Secure Processor having Trusted Execution Environment (TEE) support. The TEE provides a secure environment for running Trusted Applications (TAs) which implement security-sensitive parts of a feature. This patch configures AMD Secure Processor's TEE interface by initializing a ring buffer (shared memory between Rich OS and Trusted OS) which can hold multiple command buffer entries. The TEE interface is facilitated by a set of CPU to PSP mailbox registers. The next patch will address how commands are submitted to the ring buffer. Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Co-developed-by: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com> Signed-off-by: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com> Signed-off-by: Rijo Thomas <Rijo-john.Thomas@amd.com> Acked-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Rijo Thomas
Herbert Xu
parent
f100ab62b6
commit
33960acccf
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@ -9,7 +9,8 @@ ccp-$(CONFIG_CRYPTO_DEV_SP_CCP) += ccp-dev.o \
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ccp-$(CONFIG_CRYPTO_DEV_CCP_DEBUGFS) += ccp-debugfs.o
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ccp-$(CONFIG_PCI) += sp-pci.o
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ccp-$(CONFIG_CRYPTO_DEV_SP_PSP) += psp-dev.o \
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sev-dev.o
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sev-dev.o \
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tee-dev.o
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obj-$(CONFIG_CRYPTO_DEV_CCP_CRYPTO) += ccp-crypto.o
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ccp-crypto-objs := ccp-crypto-main.o \
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@ -13,6 +13,7 @@
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#include "sp-dev.h"
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#include "psp-dev.h"
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#include "sev-dev.h"
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#include "tee-dev.h"
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struct psp_device *psp_master;
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@ -45,6 +46,9 @@ static irqreturn_t psp_irq_handler(int irq, void *data)
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if (status) {
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if (psp->sev_irq_handler)
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psp->sev_irq_handler(irq, psp->sev_irq_data, status);
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if (psp->tee_irq_handler)
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psp->tee_irq_handler(irq, psp->tee_irq_data, status);
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}
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/* Clear the interrupt status by writing the same value we read. */
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@ -109,6 +113,25 @@ static int psp_check_support(struct psp_device *psp,
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return 0;
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}
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static int psp_init(struct psp_device *psp, unsigned int capability)
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{
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int ret;
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if (!psp_check_sev_support(psp, capability)) {
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ret = sev_dev_init(psp);
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if (ret)
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return ret;
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}
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if (!psp_check_tee_support(psp, capability)) {
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ret = tee_dev_init(psp);
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if (ret)
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return ret;
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}
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return 0;
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}
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int psp_dev_init(struct sp_device *sp)
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{
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struct device *dev = sp->dev;
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@ -151,7 +174,7 @@ int psp_dev_init(struct sp_device *sp)
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goto e_err;
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}
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ret = sev_dev_init(psp);
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ret = psp_init(psp, capability);
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if (ret)
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goto e_irq;
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@ -189,6 +212,8 @@ void psp_dev_destroy(struct sp_device *sp)
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sev_dev_destroy(psp);
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tee_dev_destroy(psp);
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sp_free_psp_irq(sp, psp);
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}
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@ -204,6 +229,18 @@ void psp_clear_sev_irq_handler(struct psp_device *psp)
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psp_set_sev_irq_handler(psp, NULL, NULL);
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}
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void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
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void *data)
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{
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psp->tee_irq_data = data;
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psp->tee_irq_handler = handler;
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}
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void psp_clear_tee_irq_handler(struct psp_device *psp)
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{
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psp_set_tee_irq_handler(psp, NULL, NULL);
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}
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struct psp_device *psp_get_master_device(void)
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{
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struct sp_device *sp = sp_get_psp_master_device();
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@ -40,13 +40,21 @@ struct psp_device {
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psp_irq_handler_t sev_irq_handler;
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void *sev_irq_data;
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psp_irq_handler_t tee_irq_handler;
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void *tee_irq_data;
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void *sev_data;
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void *tee_data;
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};
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void psp_set_sev_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
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void *data);
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void psp_clear_sev_irq_handler(struct psp_device *psp);
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void psp_set_tee_irq_handler(struct psp_device *psp, psp_irq_handler_t handler,
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void *data);
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void psp_clear_tee_irq_handler(struct psp_device *psp);
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struct psp_device *psp_get_master_device(void);
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#endif /* __PSP_DEV_H */
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@ -2,7 +2,7 @@
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/*
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* AMD Secure Processor driver
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*
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* Copyright (C) 2017-2018 Advanced Micro Devices, Inc.
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* Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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* Author: Gary R Hook <gary.hook@amd.com>
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@ -45,8 +45,17 @@ struct sev_vdata {
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const unsigned int cmdbuff_addr_hi_reg;
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};
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struct tee_vdata {
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const unsigned int cmdresp_reg;
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const unsigned int cmdbuff_addr_lo_reg;
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const unsigned int cmdbuff_addr_hi_reg;
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const unsigned int ring_wptr_reg;
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const unsigned int ring_rptr_reg;
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};
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struct psp_vdata {
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const struct sev_vdata *sev;
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const struct tee_vdata *tee;
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const unsigned int feature_reg;
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const unsigned int inten_reg;
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const unsigned int intsts_reg;
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@ -2,7 +2,7 @@
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/*
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* AMD Secure Processor device driver
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*
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* Copyright (C) 2013,2018 Advanced Micro Devices, Inc.
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* Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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* Author: Gary R Hook <gary.hook@amd.com>
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@ -274,6 +274,14 @@ static const struct sev_vdata sevv2 = {
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.cmdbuff_addr_hi_reg = 0x109e4,
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};
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static const struct tee_vdata teev1 = {
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.cmdresp_reg = 0x10544,
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.cmdbuff_addr_lo_reg = 0x10548,
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.cmdbuff_addr_hi_reg = 0x1054c,
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.ring_wptr_reg = 0x10550,
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.ring_rptr_reg = 0x10554,
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};
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static const struct psp_vdata pspv1 = {
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.sev = &sevv1,
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.feature_reg = 0x105fc,
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@ -287,6 +295,13 @@ static const struct psp_vdata pspv2 = {
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.inten_reg = 0x10690,
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.intsts_reg = 0x10694,
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};
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static const struct psp_vdata pspv3 = {
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.tee = &teev1,
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.feature_reg = 0x109fc,
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.inten_reg = 0x10690,
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.intsts_reg = 0x10694,
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};
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#endif
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static const struct sp_dev_vdata dev_vdata[] = {
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@ -318,6 +333,15 @@ static const struct sp_dev_vdata dev_vdata[] = {
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#endif
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#ifdef CONFIG_CRYPTO_DEV_SP_PSP
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.psp_vdata = &pspv2,
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#endif
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},
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{ /* 4 */
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.bar = 2,
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#ifdef CONFIG_CRYPTO_DEV_SP_CCP
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.ccp_vdata = &ccpv5a,
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#endif
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#ifdef CONFIG_CRYPTO_DEV_SP_PSP
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.psp_vdata = &pspv3,
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#endif
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},
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};
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@ -326,6 +350,7 @@ static const struct pci_device_id sp_pci_table[] = {
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{ PCI_VDEVICE(AMD, 0x1456), (kernel_ulong_t)&dev_vdata[1] },
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{ PCI_VDEVICE(AMD, 0x1468), (kernel_ulong_t)&dev_vdata[2] },
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{ PCI_VDEVICE(AMD, 0x1486), (kernel_ulong_t)&dev_vdata[3] },
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{ PCI_VDEVICE(AMD, 0x15DF), (kernel_ulong_t)&dev_vdata[4] },
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/* Last entry must be zero */
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{ 0, }
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};
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238
drivers/crypto/ccp/tee-dev.c
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238
drivers/crypto/ccp/tee-dev.c
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@ -0,0 +1,238 @@
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// SPDX-License-Identifier: MIT
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/*
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* AMD Trusted Execution Environment (TEE) interface
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*
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* Author: Rijo Thomas <Rijo-john.Thomas@amd.com>
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* Author: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com>
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*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*/
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/gfp.h>
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#include <linux/psp-sev.h>
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#include "psp-dev.h"
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#include "tee-dev.h"
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static bool psp_dead;
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static int tee_alloc_ring(struct psp_tee_device *tee, int ring_size)
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{
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struct ring_buf_manager *rb_mgr = &tee->rb_mgr;
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void *start_addr;
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if (!ring_size)
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return -EINVAL;
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/* We need actual physical address instead of DMA address, since
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* Trusted OS running on AMD Secure Processor will map this region
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*/
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start_addr = (void *)__get_free_pages(GFP_KERNEL, get_order(ring_size));
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if (!start_addr)
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return -ENOMEM;
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rb_mgr->ring_start = start_addr;
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rb_mgr->ring_size = ring_size;
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rb_mgr->ring_pa = __psp_pa(start_addr);
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return 0;
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}
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static void tee_free_ring(struct psp_tee_device *tee)
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{
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struct ring_buf_manager *rb_mgr = &tee->rb_mgr;
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if (!rb_mgr->ring_start)
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return;
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free_pages((unsigned long)rb_mgr->ring_start,
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get_order(rb_mgr->ring_size));
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rb_mgr->ring_start = NULL;
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rb_mgr->ring_size = 0;
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rb_mgr->ring_pa = 0;
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}
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static int tee_wait_cmd_poll(struct psp_tee_device *tee, unsigned int timeout,
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unsigned int *reg)
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{
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/* ~10ms sleep per loop => nloop = timeout * 100 */
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int nloop = timeout * 100;
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while (--nloop) {
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*reg = ioread32(tee->io_regs + tee->vdata->cmdresp_reg);
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if (*reg & PSP_CMDRESP_RESP)
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return 0;
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usleep_range(10000, 10100);
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}
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dev_err(tee->dev, "tee: command timed out, disabling PSP\n");
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psp_dead = true;
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return -ETIMEDOUT;
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}
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static
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struct tee_init_ring_cmd *tee_alloc_cmd_buffer(struct psp_tee_device *tee)
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{
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struct tee_init_ring_cmd *cmd;
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cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
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if (!cmd)
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return NULL;
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cmd->hi_addr = upper_32_bits(tee->rb_mgr.ring_pa);
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cmd->low_addr = lower_32_bits(tee->rb_mgr.ring_pa);
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cmd->size = tee->rb_mgr.ring_size;
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dev_dbg(tee->dev, "tee: ring address: high = 0x%x low = 0x%x size = %u\n",
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cmd->hi_addr, cmd->low_addr, cmd->size);
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return cmd;
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}
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static inline void tee_free_cmd_buffer(struct tee_init_ring_cmd *cmd)
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{
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kfree(cmd);
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}
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static int tee_init_ring(struct psp_tee_device *tee)
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{
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int ring_size = MAX_RING_BUFFER_ENTRIES * sizeof(struct tee_ring_cmd);
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struct tee_init_ring_cmd *cmd;
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phys_addr_t cmd_buffer;
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unsigned int reg;
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int ret;
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BUILD_BUG_ON(sizeof(struct tee_ring_cmd) != 1024);
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ret = tee_alloc_ring(tee, ring_size);
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if (ret) {
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dev_err(tee->dev, "tee: ring allocation failed %d\n", ret);
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return ret;
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}
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tee->rb_mgr.wptr = 0;
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cmd = tee_alloc_cmd_buffer(tee);
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if (!cmd) {
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tee_free_ring(tee);
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return -ENOMEM;
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}
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cmd_buffer = __psp_pa((void *)cmd);
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/* Send command buffer details to Trusted OS by writing to
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* CPU-PSP message registers
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*/
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iowrite32(lower_32_bits(cmd_buffer),
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tee->io_regs + tee->vdata->cmdbuff_addr_lo_reg);
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iowrite32(upper_32_bits(cmd_buffer),
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tee->io_regs + tee->vdata->cmdbuff_addr_hi_reg);
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iowrite32(TEE_RING_INIT_CMD,
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tee->io_regs + tee->vdata->cmdresp_reg);
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ret = tee_wait_cmd_poll(tee, TEE_DEFAULT_TIMEOUT, ®);
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if (ret) {
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dev_err(tee->dev, "tee: ring init command timed out\n");
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tee_free_ring(tee);
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goto free_buf;
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}
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if (reg & PSP_CMDRESP_ERR_MASK) {
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dev_err(tee->dev, "tee: ring init command failed (%#010x)\n",
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reg & PSP_CMDRESP_ERR_MASK);
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tee_free_ring(tee);
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ret = -EIO;
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}
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free_buf:
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tee_free_cmd_buffer(cmd);
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return ret;
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}
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static void tee_destroy_ring(struct psp_tee_device *tee)
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{
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unsigned int reg;
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int ret;
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if (!tee->rb_mgr.ring_start)
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return;
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if (psp_dead)
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goto free_ring;
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iowrite32(TEE_RING_DESTROY_CMD,
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tee->io_regs + tee->vdata->cmdresp_reg);
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ret = tee_wait_cmd_poll(tee, TEE_DEFAULT_TIMEOUT, ®);
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if (ret) {
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dev_err(tee->dev, "tee: ring destroy command timed out\n");
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} else if (reg & PSP_CMDRESP_ERR_MASK) {
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dev_err(tee->dev, "tee: ring destroy command failed (%#010x)\n",
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reg & PSP_CMDRESP_ERR_MASK);
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}
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free_ring:
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tee_free_ring(tee);
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}
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int tee_dev_init(struct psp_device *psp)
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{
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struct device *dev = psp->dev;
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struct psp_tee_device *tee;
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int ret;
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ret = -ENOMEM;
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tee = devm_kzalloc(dev, sizeof(*tee), GFP_KERNEL);
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if (!tee)
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goto e_err;
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psp->tee_data = tee;
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tee->dev = dev;
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tee->psp = psp;
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tee->io_regs = psp->io_regs;
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tee->vdata = (struct tee_vdata *)psp->vdata->tee;
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if (!tee->vdata) {
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ret = -ENODEV;
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dev_err(dev, "tee: missing driver data\n");
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goto e_err;
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}
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ret = tee_init_ring(tee);
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if (ret) {
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dev_err(dev, "tee: failed to init ring buffer\n");
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goto e_err;
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}
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dev_notice(dev, "tee enabled\n");
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return 0;
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e_err:
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psp->tee_data = NULL;
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dev_notice(dev, "tee initialization failed\n");
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return ret;
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}
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void tee_dev_destroy(struct psp_device *psp)
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{
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struct psp_tee_device *tee = psp->tee_data;
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if (!tee)
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return;
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tee_destroy_ring(tee);
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}
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109
drivers/crypto/ccp/tee-dev.h
Normal file
109
drivers/crypto/ccp/tee-dev.h
Normal file
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@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Author: Rijo Thomas <Rijo-john.Thomas@amd.com>
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* Author: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/* This file describes the TEE communication interface between host and AMD
|
||||
* Secure Processor
|
||||
*/
|
||||
|
||||
#ifndef __TEE_DEV_H__
|
||||
#define __TEE_DEV_H__
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#define TEE_DEFAULT_TIMEOUT 10
|
||||
#define MAX_BUFFER_SIZE 992
|
||||
|
||||
/**
|
||||
* enum tee_ring_cmd_id - TEE interface commands for ring buffer configuration
|
||||
* @TEE_RING_INIT_CMD: Initialize ring buffer
|
||||
* @TEE_RING_DESTROY_CMD: Destroy ring buffer
|
||||
* @TEE_RING_MAX_CMD: Maximum command id
|
||||
*/
|
||||
enum tee_ring_cmd_id {
|
||||
TEE_RING_INIT_CMD = 0x00010000,
|
||||
TEE_RING_DESTROY_CMD = 0x00020000,
|
||||
TEE_RING_MAX_CMD = 0x000F0000,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tee_init_ring_cmd - Command to init TEE ring buffer
|
||||
* @low_addr: bits [31:0] of the physical address of ring buffer
|
||||
* @hi_addr: bits [63:32] of the physical address of ring buffer
|
||||
* @size: size of ring buffer in bytes
|
||||
*/
|
||||
struct tee_init_ring_cmd {
|
||||
u32 low_addr;
|
||||
u32 hi_addr;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
#define MAX_RING_BUFFER_ENTRIES 32
|
||||
|
||||
/**
|
||||
* struct ring_buf_manager - Helper structure to manage ring buffer.
|
||||
* @ring_start: starting address of ring buffer
|
||||
* @ring_size: size of ring buffer in bytes
|
||||
* @ring_pa: physical address of ring buffer
|
||||
* @wptr: index to the last written entry in ring buffer
|
||||
*/
|
||||
struct ring_buf_manager {
|
||||
void *ring_start;
|
||||
u32 ring_size;
|
||||
phys_addr_t ring_pa;
|
||||
u32 wptr;
|
||||
};
|
||||
|
||||
struct psp_tee_device {
|
||||
struct device *dev;
|
||||
struct psp_device *psp;
|
||||
void __iomem *io_regs;
|
||||
struct tee_vdata *vdata;
|
||||
struct ring_buf_manager rb_mgr;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum tee_cmd_state - TEE command states for the ring buffer interface
|
||||
* @TEE_CMD_STATE_INIT: initial state of command when sent from host
|
||||
* @TEE_CMD_STATE_PROCESS: command being processed by TEE environment
|
||||
* @TEE_CMD_STATE_COMPLETED: command processing completed
|
||||
*/
|
||||
enum tee_cmd_state {
|
||||
TEE_CMD_STATE_INIT,
|
||||
TEE_CMD_STATE_PROCESS,
|
||||
TEE_CMD_STATE_COMPLETED,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tee_ring_cmd - Structure of the command buffer in TEE ring
|
||||
* @cmd_id: refers to &enum tee_cmd_id. Command id for the ring buffer
|
||||
* interface
|
||||
* @cmd_state: refers to &enum tee_cmd_state
|
||||
* @status: status of TEE command execution
|
||||
* @res0: reserved region
|
||||
* @pdata: private data (currently unused)
|
||||
* @res1: reserved region
|
||||
* @buf: TEE command specific buffer
|
||||
*/
|
||||
struct tee_ring_cmd {
|
||||
u32 cmd_id;
|
||||
u32 cmd_state;
|
||||
u32 status;
|
||||
u32 res0[1];
|
||||
u64 pdata;
|
||||
u32 res1[2];
|
||||
u8 buf[MAX_BUFFER_SIZE];
|
||||
|
||||
/* Total size: 1024 bytes */
|
||||
} __packed;
|
||||
|
||||
int tee_dev_init(struct psp_device *psp);
|
||||
void tee_dev_destroy(struct psp_device *psp);
|
||||
|
||||
#endif /* __TEE_DEV_H__ */
|
||||
Loading…
Reference in a new issue