OMAPDSS: HDMI: rewrite HDMI PLL calculation code
The code calculating HDMI PLL parameters has always been very confusing. Now that we are implementing a common PLL library for the DSS, it's important that the PLL code is understandable. This patch rewrites the calculation code, and removes a few hacks that were used there. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>hifive-unleashed-5.1
Tomi Valkeinen
parent
31dd0f4be4
commit
33f13120e5
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@ -191,7 +191,9 @@ struct hdmi_pll_info {
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u32 regmf;
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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unsigned long clkdco;
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unsigned long clkout;
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};
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struct hdmi_audio_format {
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@ -313,11 +315,13 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
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int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
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unsigned long target_tmds);
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
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/* HDMI PHY funcs */
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int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
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int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
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unsigned long lfbitclk);
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void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
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int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
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@ -180,7 +180,6 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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int r;
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struct omap_video_timings *p;
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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unsigned long phy;
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struct hdmi_wp_data *wp = &hdmi.wp;
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r = hdmi_power_on_core(dssdev);
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@ -195,10 +194,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
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/* the functions below use kHz pixel clock. TODO: change to Hz */
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phy = p->pixelclock / 1000;
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
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@ -207,7 +203,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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goto err_pll_enable;
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}
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r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
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r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
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hdmi.pll.info.clkout);
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if (r) {
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DSSDBG("Failed to configure PHY\n");
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goto err_phy_cfg;
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@ -198,7 +198,6 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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int r;
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struct omap_video_timings *p;
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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unsigned long phy;
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r = hdmi_power_on_core(dssdev);
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if (r)
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@ -208,10 +207,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
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/* the functions below use kHz pixel clock. TODO: change to Hz */
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phy = p->pixelclock / 1000;
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
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/* disable and clear irqs */
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hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
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@ -225,7 +221,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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goto err_pll_enable;
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}
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r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
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r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
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hdmi.pll.info.clkout);
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if (r) {
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DSSDBG("Failed to start PHY\n");
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goto err_phy_cfg;
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@ -20,9 +20,7 @@
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struct hdmi_phy_features {
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bool bist_ctrl;
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bool calc_freqout;
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bool ldo_voltage;
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unsigned long dcofreq_min;
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unsigned long max_phy;
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};
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@ -132,7 +130,8 @@ static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
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REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
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}
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int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
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int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
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unsigned long lfbitclk)
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{
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u8 freqout;
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@ -149,20 +148,16 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
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if (phy_feat->bist_ctrl)
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REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
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if (phy_feat->calc_freqout) {
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/* DCOCLK/10 is pixel clock, compare pclk with DCOCLK_MIN/10 */
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u32 dco_min = phy_feat->dcofreq_min / 10;
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u32 pclk = cfg->timings.pixelclock;
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if (pclk < dco_min)
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freqout = 0;
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else if ((pclk >= dco_min) && (pclk < phy_feat->max_phy))
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freqout = 1;
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else
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freqout = 2;
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} else {
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/*
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* If the hfbitclk != lfbitclk, it means the lfbitclk was configured
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* to be used for TMDS.
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*/
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if (hfbitclk != lfbitclk)
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freqout = 0;
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else if (hfbitclk / 10 < phy_feat->max_phy)
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freqout = 1;
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}
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else
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freqout = 2;
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/*
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* Write to phy address 0 to configure the clock
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@ -184,17 +179,13 @@ int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
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static const struct hdmi_phy_features omap44xx_phy_feats = {
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.bist_ctrl = false,
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.calc_freqout = false,
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.ldo_voltage = true,
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.dcofreq_min = 500000000,
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.max_phy = 185675000,
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};
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static const struct hdmi_phy_features omap54xx_phy_feats = {
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.bist_ctrl = true,
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.calc_freqout = true,
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.ldo_voltage = false,
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.dcofreq_min = 750000000,
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.max_phy = 186000000,
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};
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@ -20,14 +20,9 @@
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#include "dss.h"
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#include "hdmi.h"
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#define HDMI_DEFAULT_REGN 16
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#define HDMI_DEFAULT_REGM2 1
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struct hdmi_pll_features {
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bool has_refsel;
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bool sys_reset;
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/* this is a hack, need to replace it with a better computation of M2 */
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bool bound_dcofreq;
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unsigned long fint_min, fint_max;
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u16 regm_max;
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unsigned long dcofreq_low_min, dcofreq_low_max;
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@ -52,56 +47,62 @@ void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
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DUMPPLL(PLLCTRL_CFG4);
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}
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
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unsigned long target_tmds)
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{
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struct hdmi_pll_info *pi = &pll->info;
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unsigned long refclk;
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u32 mf;
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unsigned long fint, clkdco, clkout;
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unsigned long target_bitclk, target_clkdco;
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unsigned long min_dco;
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unsigned n, m, mf, m2, sd;
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/* use our funky units */
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clkin /= 10000;
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DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
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/*
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* Input clock is predivided by N + 1
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* out put of which is reference clk
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*/
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target_bitclk = target_tmds * 10;
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pi->regn = HDMI_DEFAULT_REGN;
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/* Fint */
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n = DIV_ROUND_UP(clkin, pll_feat->fint_max);
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fint = clkin / n;
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refclk = clkin / pi->regn;
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/* adjust m2 so that the clkdco will be high enough */
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min_dco = roundup(pll_feat->dcofreq_low_min, fint);
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m2 = DIV_ROUND_UP(min_dco, target_bitclk);
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if (m2 == 0)
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m2 = 1;
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/* temorary hack to make sure DCO freq isn't calculated too low */
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if (pll_feat->bound_dcofreq && phy <= 65000)
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pi->regm2 = 3;
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target_clkdco = target_bitclk * m2;
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m = target_clkdco / fint;
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clkdco = fint * m;
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/* adjust clkdco with fractional mf */
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if (WARN_ON(target_clkdco - clkdco > fint))
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mf = 0;
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else
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pi->regm2 = HDMI_DEFAULT_REGM2;
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mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
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/*
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* multiplier is pixel_clk/ref_clk
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* Multiplying by 100 to avoid fractional part removal
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*/
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pi->regm = phy * pi->regm2 / refclk;
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if (mf > 0)
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clkdco += (u32)div_u64((u64)mf * fint, 262144);
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/*
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* fractional multiplier is remainder of the difference between
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* multiplier and actual phy(required pixel clock thus should be
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* multiplied by 2^18(262144) divided by the reference clock
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*/
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mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
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pi->regmf = pi->regm2 * mf / refclk;
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clkout = clkdco / m2;
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/*
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* Dcofreq should be set to 1 if required pixel clock
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* is greater than 1000MHz
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*/
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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/* sigma-delta */
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sd = DIV_ROUND_UP(fint * m, 250000000);
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
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n, m, mf, m2, sd);
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DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
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pi->regn = n;
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pi->regm = m;
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pi->regmf = mf;
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pi->regm2 = m2;
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pi->regsd = sd;
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pi->clkdco = clkdco;
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pi->clkout = clkout;
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}
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static int hdmi_pll_config(struct hdmi_pll_data *pll)
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{
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u32 r;
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@ -123,7 +124,7 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll)
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if (pll_feat->has_refsel)
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r = FLD_MOD(r, 0x3, 22, 21); /* REFSEL = SYSCLK */
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if (fmt->dcofreq)
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if (fmt->clkdco > pll_feat->dcofreq_low_max)
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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else
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r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
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@ -210,7 +211,6 @@ void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
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static const struct hdmi_pll_features omap44xx_pll_feats = {
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.sys_reset = false,
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.bound_dcofreq = false,
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.fint_min = 500000,
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.fint_max = 2500000,
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.regm_max = 4095,
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@ -223,7 +223,6 @@ static const struct hdmi_pll_features omap44xx_pll_feats = {
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static const struct hdmi_pll_features omap54xx_pll_feats = {
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.has_refsel = true,
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.sys_reset = true,
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.bound_dcofreq = true,
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.fint_min = 620000,
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.fint_max = 2500000,
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.regm_max = 2046,
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